CN109496363A - Tunneling field-effect transistor device making method and tunneling field-effect transistor device - Google Patents
Tunneling field-effect transistor device making method and tunneling field-effect transistor device Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 68
- 230000005669 field effect Effects 0.000 title claims description 9
- 230000005641 tunneling Effects 0.000 title claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 101
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 101
- 239000010703 silicon Substances 0.000 claims abstract description 101
- 239000000758 substrate Substances 0.000 claims abstract description 90
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 39
- 229920005591 polysilicon Polymers 0.000 claims abstract description 37
- 239000000463 material Substances 0.000 claims abstract description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 87
- 238000005530 etching Methods 0.000 claims description 47
- 239000000377 silicon dioxide Substances 0.000 claims description 43
- 230000008569 process Effects 0.000 claims description 28
- 235000012239 silicon dioxide Nutrition 0.000 claims description 27
- 238000001259 photo etching Methods 0.000 claims description 23
- 238000000407 epitaxy Methods 0.000 claims description 22
- 238000005468 ion implantation Methods 0.000 claims description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 19
- 238000000227 grinding Methods 0.000 claims description 14
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 10
- 229910052785 arsenic Inorganic materials 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 9
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 7
- 239000011574 phosphorus Substances 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims 1
- 229910052906 cristobalite Inorganic materials 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 229910052682 stishovite Inorganic materials 0.000 claims 1
- 229910052905 tridymite Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 32
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000011049 filling Methods 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 230000010415 tropism Effects 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000002242 deionisation method Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-O phosphonium Chemical compound [PH4+] XYFCBTPGUUZFHI-UHFFFAOYSA-O 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
A kind of TFET device making method and TFET device, belong to transistor fabrication techniques field.This method comprises: forming main shaft pattern above silicon substrate (21), the material of main shaft pattern is polysilicon (23)；Form the side wall (251) for surrounding main shaft pattern；First electrode is formed in the first area of silicon substrate (21) using self-registered technology, first area refers to the region for not covering main shaft pattern and side wall (251), and first electrode is source electrode (91) or drain electrode (92)；Second area using self-registered technology in silicon substrate (21) forms second electrode, second area refers to the corresponding region of main shaft pattern, second electrode is source electrode (91) or drain electrode (92), and second electrode is different from the first electrode；Grid (93) are formed in the corresponding region of side wall (251).Its TFET device for realizing manufacture accurate-size, and while increasing TFET device on-state current, reduce its leakage current.
Description
This application involves transistor fabrication techniques field, in particular to a kind of tunneling field-effect transistor (Tunneling Field Effect Transistor, TFET) device making method and TFET device.
With the progress of transistor fabrication, the size of transistor constantly reduces, correspondingly, the grid length of transistor also constantly reduces.But, it is influenced by the graceful heat distribution of current-carrying wavelet Wurz, the reduction of grid length causes the quiescent dissipation of metal-oxide semiconductor fieldeffect transistor (Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET) to dramatically increase.TFET, to have lesser quiescent dissipation, is increasingly becoming the potential replacer of MOSFET because not influenced by the graceful heat distribution of current-carrying wavelet Wurz.
The working principle of TFET device is band-to-band-tunneling (band-to-band-tunneling) mechanism, in order to improve tunnelling probability, to increase tunnelling current, needs to increase the tunnelling area between grid and source electrode.As shown in Figure 1, TFET device includes source electrode 11, drain electrode 12 and grid 13, wherein grid 13 is designed to pectinate texture.Using this design, the contact area between grid 13 and source electrode 11 is larger, to increase the tunnelling area between grid 13 and source electrode 11, and then increases the tunnelling current between grid 13 and source electrode 11.
However, the grid of the pectinate texture of accurate-size can not be formed on TFET device using existing manufacturing process since the size of TFET device is smaller.
Summary of the invention
In order to solve the problem of that this application provides a kind of TFET device making method and TFET devices in the related technology due to the smaller pectinate texture grid that can not form accurate-size on TFET device using existing manufacturing process of the size of TFET device.The technical solution is as follows:
In a first aspect, a kind of TFET device making method is provided, this method comprises:
Main shaft pattern is formed above silicon substrate, the material of main shaft pattern is polysilicon；
Form the side wall (Spacer) for surrounding main shaft pattern；
First electrode is formed in the first area of silicon substrate using self-registered technology, first area refers to the region for not covering main shaft pattern and side wall, and first electrode is source electrode or drain electrode；
Second electrode is formed in the second area of silicon substrate using self-registered technology, second area refers to the corresponding region of main shaft pattern, and second electrode is source electrode or drain electrode, and second electrode is different from the first electrode；
Grid is formed in the corresponding region of side wall.
It is different from traditional TFET device fabrication; in the embodiment of the present application; the main shaft pattern of polycrystalline silicon material is formed first above silicon substrate; and side wall is formed around main shaft pattern; under the protection of main shaft pattern and side wall; the subsequent source electrode and drain electrode that can form accurate-size on silicon substrate by self-registered technology, and then the sidewall areas between source electrode and drain electrode forms the grid of accurate-size, it is ensured that the TFET device produced meets accurate process requirements；Meanwhile grid is formed in the sidewall areas around main shaft pattern, the contact area between grid and source electrode can greatly be increased, to increase between grid and source electrode
Tunnelling current, while increasing on-state current, reduce leakage current, improve TFET device electrical property.
In an alternative embodiment, main shaft pattern is formed above silicon substrate, comprising:
Oxide layer is covered above silicon substrate, the material of oxide layer is silica (SiO2)；
One layer of polysilicon is deposited in oxide layer；
One layer of hard exposure mask (Hard Mask) of side's deposition on the polysilicon, the material of hard exposure mask are silicon nitride (SiN), silicon oxynitride (SiON) or SiONO；
Main shaft pattern is formed using photoetching process, the surface of main shaft pattern is hard exposure mask, and the lower section of hard exposure mask is polysilicon.
In the present embodiment, oxide layer is covered above silicon substrate, effective protection can be played to silicon substrate in the fabrication process；Meanwhile main shaft pattern is formed using hard exposure mask and photoetching process, it can be ensured that the accuracy of main shaft pattern dimension.
In an alternative embodiment, main shaft pattern is cross pattern, and main shaft pattern is located at silicon substrate center, and the size of main shaft pattern is greater than the size of silicon substrate；Grid includes four L-type grids between source electrode and drain electrode.
In the present embodiment, by by main shaft design be it is cross, can reduce the manufacture difficulty of TFET device, be conducive to improve TFET device the accuracy of manufacture；Also, in the present embodiment, source electrode and four L-type gate contacts in TFET device, compared to traditional TFET device, the contact area of source electrode and grid is multiplied, and greatly improves the on-state current of TFET device.
In an alternative embodiment, the side wall for surrounding main shaft pattern is formed, comprising:
In main shaft pattern and silicon substrate disposed thereon silicon nitride layer；
Side wall is formed using isotropic etch process, the material of side wall is silicon nitride.
In an alternative embodiment, TFET device is N-type TFET device, forms first electrode in the first area of silicon substrate using self-registered technology, comprising:
N-type TFET device area is defined using lay photoetching mask plate；
By the way of ion implantation, first electrode is formed in first area, it includes arsenic (As) or phosphorus (P) in n-type doping that first electrode, which is n-type doping,；Or,
First area is performed etching, and the first area by the way of extension after etching forms first electrode, first electrode is N-type epitaxy layer, and the material of N-type epitaxy layer is phosphatization silicon (SiP).
Second area using self-registered technology in the silicon substrate forms second electrode, comprising:
N-type TFET device area is defined using lay photoetching mask plate；
By the way of ion implantation, second electrode is formed in second area, it includes boron (B) or boron difluoride (BF in p-type doping that second electrode, which is p-type doping,2)；Or,
Second area is performed etching, and using extension by the way of second area after etching form second electrode, second electrode is p-type epitaxial layer, and the material of p-type epitaxial layer is the SiGe (SiGe) of boracic.
In an alternative embodiment, when TFET device is p-type TFET device, first electrode is formed in the first area of the silicon substrate using self-registered technology, comprising:
P-type TFET device area is defined using lay photoetching mask plate；
By the way of ion implantation, first electrode is formed in first area, it includes B or BF in p-type doping that first electrode, which is p-type doping,2；Or,
First area is performed etching, and the first area by the way of extension after etching forms first electrode, first electrode is p-type epitaxial layer, and the material of p-type epitaxial layer is the SiGe of boracic.
Second area using self-registered technology in silicon substrate forms second electrode, comprising:
P-type TFET device area is defined using lay photoetching mask plate；
By the way of ion implantation, second electrode is formed in second area, it includes As or P in n-type doping that second electrode, which is n-type doping,；Or,
Second area is performed etching, and using extension by the way of second area after etching form second electrode, second electrode is N-type epitaxy layer, and the material of N-type epitaxy layer is SiP.
In the present embodiment, it can be adulterated in the different zones of silicon substrate according to actual needs or form different epitaxial layers, so that N-type TFET device or p-type TFET device be made, enrich the type of the TFET device produced；Meanwhile using ion implanting or etching epitaxy technique setting source electrode or drain electrode, it can guarantee the dimensional accuracy of source electrode or drain electrode, improve the yields of TFET device.
In an alternative embodiment, using self-registered technology before the second area of silicon substrate forms second electrode, further includes:
A silicon dioxide layer is deposited, and the surface of silicon dioxide layer is ground, after milled processed, the surfacing of silicon dioxide layer；
Using the hard exposure mask of etching and chemical grinding removal main shaft patterned surfaces；
By the way of dry etching or wet etching, the polysilicon in main shaft patterned surfaces is removed.
In the present embodiment, in such a way that silica deposits and grinds, planarization process is carried out to the surface of TFET device, and further remove the hard exposure mask of main shaft patterned surfaces, so that hard exposure mask be avoided to have an impact to second electrode process is formed.
In an alternative embodiment, the grid of TFET device is formed in the corresponding region of side wall, comprising:
A silicon dioxide layer is deposited, and the surface of silicon dioxide layer is ground, after milled processed, the surfacing of silicon dioxide layer；
Using etching and chemical grinding mode, it is ground to exposed sidewalls；
Side wall is removed by the way of dry etching or wet etching；
Grid is formed using region of high-dielectric constant metal grid pole (High-K Metal Gate, the HKMG) technique after removing side wall.
In the present embodiment, grid is formed using the sidewall areas being centered around around main shaft pattern, increases the contact area between grid and source electrode, improves the on-state current of TFET device.
In an alternative embodiment, using self-registered technology after the second area of the silicon substrate forms second electrode, further includes:
Using the fringe region of nitride grid mask excision side wall, fringe region is the sidewall areas other than silicon substrate.
Under the premise of not influencing TFET device performance, the sidewall areas other than silicon substrate is cut off using nitride grid mask, further decreases the size for the TFET device being finally made.
Second aspect provides a kind of TFET device, which is fabricated by manufacturing method described in first aspect, which includes:
Grid, source electrode and drain electrode；
Source electrode is located at the region on TFET device where main shaft pattern, and grid surrounds source electrode, and the region being located on TFET device in addition to source electrode and grid that drains；Or,
Drain electrode is located at main shaft pattern region on TFET device, and grid is around drain electrode, and source electrode is located at the region on TFET device in addition to drain and gate.
In an alternative embodiment, main shaft pattern is cross pattern, and grid includes four between source electrode and drain electrode
A L-type grid.
Fig. 1 is the structural schematic diagram using the TFET device of pectinate texture grid；
Fig. 2 is the flow chart for the TFET device making method that the application one embodiment provides；
Fig. 3 A is the flow chart to form main shaft patterning process；
Fig. 3 B is the sectional view and top view for the main shaft pattern to be formed；
Fig. 4 A is the flow chart to form side wall process；
Fig. 4 B is the sectional view and top view for the side wall to be formed；
Fig. 5 A is the flow chart that first electrode and second electrode process are formed when manufacturing N-type TFET device；
Fig. 5 B is the sectional view and top view for the N-type epitaxy layer to be formed；
Fig. 5 C is the sectional view and top view of intermediary device after grinding；
Fig. 5 D is the sectional view and top view of intermediary device after removing polysilicon；
Fig. 5 E is the sectional view and top view for the p-type epitaxial layer to be formed；
Fig. 6 A is the flow chart to form gate process；
Fig. 6 B is the implementation diagram for cutting off side wall fringe region process；
Fig. 6 C is the sectional view and top view of intermediary device after grinding；
Fig. 6 D is the sectional view and top view of intermediary device after removing side wall；
Fig. 7 is the flow chart that first electrode and second electrode process are formed when manufacturing p-type TFET device；
Fig. 8 (a) and Fig. 8 (b) show the schematic diagram of TFET device provided by the embodiments of the present application He tradition TFET device；
Fig. 9 is the IV curve graph for obtain after emulation experiment to different TFET devices.
To keep the purposes, technical schemes and advantages of the application clearer, the application embodiment is described in further detail below in conjunction with attached drawing.
Fig. 2 is the flow chart for the TFET device making method that the application one embodiment provides.This method may include steps of.
Step 201, main shaft pattern is formed above silicon substrate, the material of main shaft pattern is polysilicon.
In order to increase the tunnelling area in TFET device between grid and source electrode, and realize the accurate-size of TFET device, the embodiment of the present application uses the source electrode and drain electrode that self-registered technology is formed on TFET device.And before forming source electrode and drain electrode using self-registered technology; firstly the need of the main shaft pattern for forming polysilicon (Poly-Si) material above silicon substrate (material is monocrystalline silicon); to carry out autoregistration using main shaft pattern in subsequent manufacturing processes, and source electrode or grid are protected as barrier layer.
In a kind of possible embodiment, the main shaft pattern is formed by photoetching process, and main shaft pattern is formed in the cross pattern in silicon substrate center, and the size of main shaft pattern is greater than the size of silicon substrate, under the segmentation of main shaft pattern, silicon substrate is divided into centrally located cross region and the square region positioned at quadrangle.
Step 202, the side wall for surrounding main shaft pattern is formed.
After forming main shaft pattern, circular side wall further is formed in main shaft pattern surrounding, wherein side wall profile is consistent with the shape of main shaft pattern contour (size of side wall profile is larger), and side wall region is grid region in TFET device.
In a kind of possible embodiment, first formed main shaft pattern silicon substrate surface deposit one layer of silicon nitride, then using etc. tropisms etching technics silicon nitride is performed etching, thus formed surround main shaft pattern silicon nitride sidewall.
Step 203, first electrode is formed in the first area of silicon substrate using self-registered technology, first area refers to the region for not covering main shaft pattern and side wall, and first electrode is source electrode or drain electrode.
After forming main shaft pattern and side wall, using self-registered technology in first area (region not covered by main shaft pattern and side wall) the formation source electrode of silicon substrate or drain electrode.Under the protection of main shaft pattern and side wall; the silicon substrate of first area can only be handled using self-registered technology; it in the case where the first electrode for ensuring to be formed meets accurate-size demand, avoids polluting other regions on silicon substrate, improves the yields of TFET device.
Optionally, first electrode can be formed using ion implanting or etching epitaxy technique, and when first area carries out n-type doping or forms N-type epitaxy layer, TFET device caused by final system is NTFET device, when first area carries out p-type doping or forms p-type epitaxial layer, TFET device caused by final system is PTFET.
Step 204, second electrode is formed in the second area of silicon substrate using self-registered technology, second area refers to the corresponding region of main shaft pattern, and second electrode is source electrode or drain electrode, and second electrode is different from first electrode.
It is similar with above-mentioned steps 203, after completing first electrode manufacture, continue to form the second electrode opposite with first electrode on the second area (the corresponding region of main shaft pattern) of silicon substrate using self-registered technology.Under the protection of side wall; the used self-registered technology of this step can only be handled the silicon substrate of second area; it in the case where the second electrode for ensuring to be formed meets accurate-size demand, avoids polluting other regions on silicon substrate, improves the yields of TFET device.
Optionally, second electrode can be formed using ion implanting or etching epitaxy technique；Also, in order to avoid main shaft pattern has an impact second electrode formation, before forming second electrode, the polysilicon of main shaft pattern is removed using etching technics, thus the silicon substrate under exposure main shaft pattern protection.
Wherein, when second area carries out p-type doping or forms p-type epitaxial layer, TFET device caused by final system is NTFET device, and when second area carries out n-type doping or forms N-type epitaxy layer, TFET device caused by final system is PTFET device.
Step 205, grid is formed in the corresponding region of side wall.
Through the above steps 203 and 204, the specified region of silicon substrate is formed with source electrode and drain electrode, and further includes the side wall to be formed above silicon substrate.In order to increase the tunnelling area between grid and source electrode, the side wall above etching technics removal silicon substrate can be used, and the region after removing side wall forms the grid of TFET device.
Optionally, grid is formed by traditional HKMG technique.
In a kind of possible embodiment, when using cross main shaft pattern, finally formed grid is four L-type grids, correspondingly, forming four L-type tunnelling faces between source electrode and grid.Compared in traditional TFET device, the tunnelling face of source electrode and grid is only the length of silicon substrate a line, is significantly increased using the area in the tunnelling face of TFET device caused by the present embodiment system, and then the on-state current of the TFET device improved.
It should be noted that first area be drain electrode and second area be source electrode TFET device electrical property better than second area be drain electrode and first area be source electrode TFET device electrical property.
In conclusion the main shaft pattern of polycrystalline silicon material is formed above silicon substrate, and form side wall around main shaft pattern in the present embodiment, it is subsequent to form accurate ruler on silicon substrate by self-registered technology under the protection of main shaft pattern and side wall
Very little source electrode and drain electrode, and then the sidewall areas between source electrode and drain electrode forms the grid of accurate-size, it is ensured that the TFET device produced meets accurate process requirements；Meanwhile grid is formed in the sidewall areas around main shaft pattern, the contact area between grid and source electrode can greatly be increased, to increase the tunnelling current between grid and source electrode, while increasing on-state current, reduce leakage current, improves the electrical property of TFET device.
For the process for forming main shaft pattern in above-described embodiment, in a kind of possible embodiment, as shown in Figure 3A, above-mentioned steps 201 include the following steps.
Step 201A, covers oxide layer above silicon substrate, and the material of oxide layer is silica.
Optionally, when manufacturing TFET device as substrate using monocrystalline silicon, layer of silicon dioxide film is generated in monocrystalline silicon surface using thermal oxide mode.
Schematically, as shown in Figure 3B, when manufacturing TFET device, each silicon substrate 21 is isolated by shallow-trench isolation (Shallow Trench Isolation, STI) technique first, and forms silicon dioxide layer 22 in the upper surface of silicon substrate 21.
Step 201B deposits one layer of polysilicon in oxide layer.
Optionally, using chemical vapor deposition process, one layer of polysilicon is deposited on silicon substrate surface oxide layer.It should be noted that covering polysilicon above the shallow slot between entire silicon substrate and silicon substrate after completing polysilicon deposition.
Step 201C, side deposits one layer of hard exposure mask on the polysilicon.
Further, continue to deposit one layer of hard exposure mask above the polysilicon layer of formation, wherein the material of the hard exposure mask is that the material of hard exposure mask is SiN, SiON or SiONO.
By above-mentioned steps 201A to 201C, it is followed successively by hard exposure mask, polysilicon layer, silicon dioxide layer from top to bottom above silicon substrate.
Step 201D forms main shaft pattern using photoetching process, and the surface of main shaft pattern is hard exposure mask, and the lower section of hard exposure mask is polysilicon.
According to the size of main shaft pattern predetermined, the specific part of the hard exposure mask of polysilicon surface is removed using photoetching process, the hard exposure mask and the polysilicon below hard exposure mask for only retaining main shaft pattern part.
In a kind of possible embodiment, the main shaft pattern of predetermined definition is cross pattern, and the size of the cross pattern is slightly larger than the size of silicon substrate.By photoetching process silicon substrate center formed main shaft pattern after as shown in the top view in Fig. 3 B.Correspondingly, the top of silicon substrate 21 is respectively silicon dioxide layer 22, polysilicon 23 and hard exposure mask 24, and wherein polysilicon 23 and hard exposure mask 24 constitute the main shaft pattern for protruding from 21 surface of silicon substrate as shown in the sectional view in Fig. 3 B.
For the process for forming main shaft pattern side side wall in above-described embodiment, in a kind of possible embodiment, as shown in Figure 4 A, above-mentioned steps 202 include the following steps.
Step 202A, in main shaft pattern and silicon substrate disposed thereon silicon nitride layer.
In a kind of possible embodiment, when using silicon nitride as around the side wall of silicon substrate, first by the way of chemical vapor deposition, in main shaft pattern and the disposed thereon silicon nitride layer of silicon substrate.
Schematically, as shown in the sectional view in Fig. 4 B, the top (surface of silica 22) of hard exposure mask 24 (main shaft patterned surfaces) and silicon substrate 21 is deposited with silicon nitride layer 25.
Step 202B forms side wall using isotropic etch process, and the material of side wall is silicon nitride.
Since the side wall around main shaft pattern will finally be made into the grid of TFET device, in order to ensure grid size
Consistency, using etc. tropisms etching technics silicon nitride layer is performed etching, to form the side wall of consistency of thickness.
Schematically, as shown in the sectional view in Fig. 4 B, by etc. after tropisms etching, the two sides of polysilicon 23 form the side wall 251 of equal thickness；As shown in the top view in Fig. 4 B, the side of cross main shaft pattern has surrounded cross side wall.
For the process for forming first electrode and second electrode in above-described embodiment, in a kind of possible embodiment, when TFET device making method is used to manufacture N-type TFET device, as shown in Figure 5A, above-mentioned steps 203 include step 203A to 203C, and step 204 includes step 204A to 204C.
Step 203A defines N-type TFET device area using lay photoetching mask plate.
In practical manufacturing process, it may need using manufacturing equipment while manufacture N-type TFET device and p-type TFET device, in order to avoid the two manufacturing process has an impact, when forming the first electrode of N-type TFET device, it needs to define region locating for N-type TFET device using mask version, and p-type TFET device is covered.
In a kind of possible embodiment, N-type TFET device area is defined using NTFET lay photoetching mask plate.
Step 203B forms first electrode in first area, it includes arsenic or phosphorus in n-type doping that first electrode, which is n-type doping, by the way of ion implantation.
After defining N-type TFET device area, n-type doping (first electrode) can be formed in first area by self-registered technology in a manner of further using ion implantation.In a kind of possible embodiment, ion implantation is the first area by arsenic ion or phosphonium ion implantation silicon substrate, so that including arsenic or phosphorus in the n-type doping formed.
Due on silicon substrate in addition to first area the equal main shaft pattern in region or side wall covering, ion implantation process the region other than first area will not be impacted, it is ensured that the accuracy of ion implantation.
Step 203C, performs etching first area, and the first area by the way of extension after etching forms first electrode, and first electrode is N-type epitaxy layer, and the material of N-type epitaxy layer is phosphatization silicon.
Other than forming first electrode using ion implantation mode, first electrode can also be formed in first area by the way of extension.
Schematically, as shown in the sectional view in Fig. 5 B, when forming first electrode using extensional mode, the silicon substrate 21 at first area is removed (including the silicon dioxide layer above the silicon substrate of first area) first by way of etching, form pit, then by the way of extension, pit forms N-type epitaxy layer 26, and the material of the N-type epitaxy layer is phosphatization silicon or arsenic SiClx.As shown in the top view in Fig. 5 B, when using cross main shaft pattern, four angles of silicon substrate are respectively formed on N-type epitaxy layer.
It should be noted that manufacturer can also be formed outside first electrode using the other modes other than deionization implantation and extensional mode, the embodiment of the present application is defined not to this.
After first area forms first electrode, need further to form second electrode in the second area of silicon substrate.However, due to being covered with main shaft pattern above second area, before forming second electrode, need to be removed by 206 to 208 pairs of main shaft patterns of following step.
Step 206, a silicon dioxide layer is deposited, and the surface of silicon dioxide layer is ground, after milled processed, the surfacing of silicon dioxide layer.
In order to be protected to established first electrode; before forming second electrode; first choice needs to deposit silica on the surface of manufactured intermediary device; to fill the gap between main shaft pattern and silicon substrate surface; and in such a way that etching arranges in pairs or groups chemical mechanical grinding, planarization process is carried out to the silicon dioxide layer of formation.
Wherein, FCVD, HARP, HDP, TEOS, TOSZ, the modes such as SOG can be used when depositing silica.
Schematically, as shown in the sectional view in Fig. 5 C, after passing through filling silica and being ground, the surfacing of silicon dioxide layer.
Step 207, using the hard exposure mask of etching and chemical grinding removal main shaft patterned surfaces.
Before the polysilicon in removal main shaft pattern, the surface of intermediary device is ground using etching and chemical grinding mode first, until the hard exposure mask of removal main shaft patterned surfaces.
Schematically, as shown in the sectional view in Fig. 5 C, after grinding, the hard exposure mask 24 of 23 top of polysilicon is removed；As shown in the top view in Fig. 5 C, the surface of intermediary device includes polysilicon, side wall and the silica of filling (for the overall structure for embodying TFET device, the N shape epitaxial layer below silica is still shown in the top view of Fig. 5 C).
Step 208, by the way of dry etching or wet etching, the polysilicon in main shaft pattern is removed.
In a kind of possible embodiment, chemical reagent, such as tetramethylammonium hydroxide (TMAH) or ammonium hydroxide (NH can use4OH), polysilicon is performed etching, without to intermediate device surface silica and side wall have an impact.
Schematically, as shown in the sectional view and top view in Fig. 5 D, after dry type or wet etching, the polysilicon in main shaft pattern is removed, and is initially positioned at the silicon substrate below polysilicon and is appeared (silicon substrate surface is still by oxide layer).
Step 204A defines N-type TFET device area using lay photoetching mask plate.
It is similar, when second area forms second electrode, it is still required to define N-type TFET device area using lay photoetching mask plate.
Step 204B forms second electrode in second area, it includes boron or boron difluoride in p-type doping that second electrode, which is p-type doping, by the way of ion implantation.
Different from being implanted into arsenic or phosphorus in the first area of silicon substrate, when second area forms second electrode, boron or boron difluoride by the way of ion implantation, to form p-type doping (second electrode) in second area.
Step 204C, performs etching second area, and using extension by the way of second area after etching form second electrode, second electrode is p-type epitaxial layer, and the material of p-type epitaxial layer is the SiGe of boracic.
It is similar with above-mentioned steps 203C, other than forming second electrode using ion implantation mode, second electrode can also be formed in second area by the way of extension.
Schematically, as shown in the sectional view in Fig. 5 E, when forming second electrode using extensional mode, the silicon substrate 21 at second area is removed (including the silicon dioxide layer above second area silicon substrate) first by way of etching, form pit, then by the way of extension, pit forms p-type epitaxial layer 27, and the material of the p-type epitaxial layer is the SiGe of boracic.As shown in the top view in Fig. 5 B, when using cross main shaft pattern, the central cross region (second area) of silicon substrate forms p-type epitaxial layer.
It should be noted that manufacturer can also be formed outside second electrode using the other modes other than deionization implantation and extensional mode, the embodiment of the present application is defined not to this.
It further include step 209 before above-mentioned steps 205 as shown in Figure 6A, step 205 includes step 205A to 205D in a kind of possible embodiment for the process for forming grid in above-described embodiment.
Step 209, using the fringe region of nitride grid mask excision side wall, fringe region is the sidewall areas other than silicon substrate.
In order to further decrease the size for the TFET device being finally made, after forming first electrode and second electrode, the fringe region to the lateral wall of silicon substrate is needed to cut off.
Optionally, the fringe region of side wall is cut off using nitride grid mask, to improve the accuracy of excision.
Schematically, as shown in Figure 6B, the fringe region 28 of c-type is defined using nitride grid mask, and the side wall gone out to fringe region 28 is removed, to form four L-type side walls between first electrode and second electrode.
Step 205A deposits a silicon dioxide layer, and is ground to the surface of silicon dioxide layer, after milled processed, the surfacing of silicon dioxide layer.
Established first electrode and second electrode are had an impact when grid in order to avoid being formed, it needs to deposit silica in intermediary device before forming grid, to fill the gap for removing and leaving after polysilicon, and further the silicon dioxide layer of formation is ground, makes the surfacing of intermediary device.
Step 205B is ground to exposed sidewalls using etching and chemical grinding mode.
Since grid is located at sidewall areas in the TFET device that is finally made, it is therefore desirable to further be ground using etching and chemical grinding mode to intermediary device, until exposed sidewalls.
Schematically, as shown in the sectional view in Fig. 6 C, behind the silica-filled gap of deposition, continue to grind the surface of intermediary device by the way of grinding, so that side wall 251 is exposed.As shown in the top view in Fig. 6 C, after grinding, the surface of intermediary device includes the silica of four L-type side walls and filling.
Step 205C removes side wall by the way of dry etching or wet etching.
In a kind of possible embodiment, when side wall material is silicon nitride, wet etching can be carried out to intermediate device surface using phosphoric acid, to remove silicon nitride sidewall, generate etching without the silica to intermediate device surface.
Schematically, as shown in the sectional view of Fig. 6 D, after dry etching or wet etching, side wall is removed, to form gap between the silica of filling；The silicon substrate below four L-type side walls is initially positioned at as shown in the top view of Fig. 6 D to be exposed.
Step 205D forms grid using region of the HKMG technique after removing side wall.
Further, the manufacture that after completing side wall removal, grid is formed in original sidewall areas using traditional HKMG technique, and passes through techniques the complete entire TFET device such as silication (Silicidation), contact hole, metal be online.
In above-described embodiment, it is illustrated for manufacturing N-type TFET device, when using above method manufacture p-type TFET device, on the basis of Fig. 5 A, as shown in Figure 7, above-mentioned steps 203A to step 203C may alternatively be step 203D to 203F, and step 204A to step 203C may alternatively be step 204D to 204F.
Step 203D defines p-type TFET device area using lay photoetching mask plate.
It is similar with above-mentioned steps 203A, before the first electrode for forming p-type TFET device, p-type TFET device area is defined using PTFET lay photoetching mask plate first.
Step 203E forms first electrode in first area, it includes boron or boron difluoride in p-type doping that first electrode, which is p-type doping, by the way of ion implantation.
Step 203F, performs etching first area, and the first area by the way of extension after etching forms first electrode, and first electrode is p-type epitaxial layer, and the material of p-type epitaxial layer is the SiGe of boracic.
With manufacture N-type TFET device on the contrary, when manufacturing p-type TFET device, the first area of silicon substrate carries out p-type doping or is added to p-type epitaxial layer, wherein ion implantation is similar to the aforementioned embodiment with the concrete mode for increasing epitaxial layer, and details are not described herein for the present embodiment.
Step 204D defines p-type TFET device area using lay photoetching mask plate.
It is similar with above-mentioned steps 204A, before the second electrode for forming p-type TFET device, p-type TFET device area is defined using PTFET lay photoetching mask plate first.
Step 204E forms second electrode in second area, it includes arsenic or phosphorus in n-type doping that second electrode, which is n-type doping, by the way of ion implantation.
Step 204F, performs etching second area, and using extension by the way of second area after etching form second electrode, second electrode is N-type epitaxy layer, and the material of N-type epitaxy layer is phosphatization silicon.
With manufacture N-type TFET device on the contrary, when manufacturing p-type TFET device, the second area of silicon substrate carries out n-type doping or is added to N-type epitaxy layer, wherein ion implantation is similar to the aforementioned embodiment with the concrete mode for increasing epitaxial layer, and details are not described herein for the present embodiment.
The TFET device for using manufacturing method provided by the above embodiment to produce is planar structure.TFET device includes grid, source electrode and drain electrode, wherein, when TFET device is source grid leak (Source-Gate-Drain, SGD) when the TFET device of structure, source electrode is located at the region on TFET device where main shaft pattern, grid surrounds source electrode, and the region being located on TFET device in addition to source electrode and grid that drains；When TFET device is the TFET device of drain-gate source (Drain-Gate-Source, DGS) structure, drain electrode is located at main shaft pattern region on TFET device, and grid is around drain electrode, and source electrode is located at the region on TFET device in addition to drain and gate.In a kind of possible embodiment, as shown in Fig. 8 (a), when main shaft pattern is cross pattern, source electrode 91 is located at the cross region in TFET device center, drain electrode 92 is located at TFET device quadrangle square region, and grid 93 is then four L-type grids between source electrode 91 and drain electrode 92, the contact surface between source electrode 91 and grid 93 is 4 L-type regions.And in tradition TFET device shown in Fig. 8 (b), grid 96 is located at the bar-shaped zone between source electrode 94 and drain electrode 95, and only includes a contact surface between source electrode 94 and grid 96.Since the contact surface of source electrode and grid dramatically increases, TFET device provided by the embodiments of the present application is bigger compared to the on-state current of traditional TFET device, has better electrical property.
As shown in figure 9, it illustrates the IV curves of the TFET device of traditional TFET device, the TFET device of SGD structure and DGS structure.
In Fig. 9, Gate voltage be -1 to 0V or 0 to+1V when, be defined as out, on-state current at this time is higher better；When Gate voltage is 0V, be defined as closing, electric current at this time is leakage current, leakage current it is lower better.Obviously, (source electrode is at main shaft pattern for the TFET device of the SGD structure produced using above-mentioned manufacturing method, including S-G-D NTFET and S-G-D PTFET) electrical property it is optimal, (drain electrode is at main shaft pattern for the TFET device of the DGS structure followed by produced using above-mentioned manufacturing method, including D-G-S NTFET and D-G-S PTFET), and the electrical property of traditional TFET device (including Standard NTFET and Standard PTFET) is worst.
The foregoing is merely the alternative embodiments of the application, and not to limit the application, within the spirit and principles of this application, any modification, equivalent replacement, improvement and so on be should be included within the scope of protection of this application.
Claims (14)
- A kind of tunneling field-effect transistor TFET device making method, which is characterized in that the described method includes:Main shaft pattern is formed above silicon substrate, the material of the main shaft pattern is polysilicon；Form the side wall for surrounding the main shaft pattern；First electrode is formed in the first area of the silicon substrate using self-registered technology, the first area refers to the region for not covering the main shaft pattern and the side wall, and the first electrode is source electrode or drain electrode；Second electrode is formed in the second area of the silicon substrate using self-registered technology, the second area refers to the corresponding region of the main shaft pattern, and the second electrode is source electrode or drain electrode, and the second electrode is different from the first electrode；Grid is formed in the corresponding region of the side wall.
- The method according to claim 1, wherein described form main shaft pattern above silicon substrate, comprising:Oxide layer is covered above the silicon substrate, the material of the oxide layer is silica SiO2；One layer of polysilicon is deposited in the oxide layer；One layer of hard exposure mask of side's deposition on the polysilicon, the material of the hard exposure mask are silicon nitride SiN, silicon oxynitride SiON or SiONO；The main shaft pattern is formed using photoetching process, the surface of the main shaft pattern is the hard exposure mask, and the lower section of the hard exposure mask is polysilicon.
- According to right want 1 or 2 described in method, which is characterized in that the main shaft pattern is cross pattern, and the main shaft pattern is located at silicon substrate center, and the size of the main shaft pattern is greater than the size of the silicon substrate.
- According to the method described in claim 3, it is characterized in that, the grid includes four L-type grids between source electrode and drain electrode.
- The method according to claim 1, wherein described form the side wall for surrounding the main shaft pattern, comprising:In the main shaft pattern and the silicon substrate disposed thereon silicon nitride layer；The side wall is formed using isotropic etch process, the material of the side wall is silicon nitride.
- The method according to claim 1, wherein TFET device is N-type TFET device, it is described that first electrode is formed in the first area of the silicon substrate using self-registered technology, comprising:N-type TFET device area is defined using lay photoetching mask plate；By the way of ion implantation, the first electrode is formed in the first area, it includes arsenic As or phosphorus P in the n-type doping that the first electrode, which is n-type doping,；Or,The first area is performed etching, and the first area by the way of extension after etching forms the first electrode, the first electrode is N-type epitaxy layer, and the material of the N-type epitaxy layer is phosphatization silicon SiP.
- According to the method described in claim 6, it is characterized in that, the second area using self-registered technology in the silicon substrate forms second electrode, comprising:N-type TFET device area is defined using lay photoetching mask plate；By the way of ion implantation, the second electrode is formed in the second area, it includes boron or boron difluoride BF in the p-type doping that the second electrode, which is p-type doping,2；Or,The second area is performed etching, and using extension by the way of second area after etching form the second electrode, the second electrode is p-type epitaxial layer, and the material of the p-type epitaxial layer is the SiGe SiGe of boracic.
- The method according to claim 1, wherein TFET device is p-type TFET device, it is described that first electrode is formed in the first area of the silicon substrate using self-registered technology, comprising:P-type TFET device area is defined using lay photoetching mask plate；By the way of ion implantation, the first electrode is formed in the first area, it includes boron or boron difluoride BF in the p-type doping that the first electrode, which is p-type doping,2；Or,The first area is performed etching, and the first area by the way of extension after etching forms the first electrode, the first electrode is p-type epitaxial layer, and the material of the p-type epitaxial layer is the SiGe SiGe of boracic.
- According to the method described in claim 8, it is characterized in that, the second area using self-registered technology in the silicon substrate forms second electrode, comprising:P-type TFET device area is defined using lay photoetching mask plate；By the way of ion implantation, the second electrode is formed in the second area, it includes arsenic As or phosphorus P in the n-type doping that the second electrode, which is n-type doping,；Or,The second area is performed etching, and using extension by the way of second area after etching form the second electrode, the second electrode is N-type epitaxy layer, and the material of the N-type epitaxy layer is phosphatization silicon SiP.
- According to the method described in claim 2, it is characterized in that, it is described using self-registered technology the silicon substrate second area formed second electrode before, further includes:A silicon dioxide layer is deposited, and the surface of silicon dioxide layer is ground, after milled processed, the surfacing of silicon dioxide layer；The hard exposure mask of the main shaft patterned surfaces is removed using etching and chemical grinding；By the way of dry etching or wet etching, the polysilicon in the main shaft pattern is removed.
- The method according to claim 1, wherein described form grid in the corresponding region of the side wall, comprising:A silicon dioxide layer is deposited, and the surface of silicon dioxide layer is ground, after milled processed, the surfacing of silicon dioxide layer；Using etching and chemical grinding mode, it is ground to the exposure side wall；The side wall is removed by the way of dry etching or wet etching；Grid is formed using region of the high-dielectric constant metal grid pole HKMG technique after removing side wall.
- The method according to claim 1, wherein it is described using self-registered technology the silicon substrate second area formed second electrode after, further includes:The fringe region of the side wall is cut off using nitride grid mask, the fringe region is the sidewall areas other than the silicon substrate.
- A kind of TFET device, which is characterized in that the TFET device is fabricated by the method as described in the claims 1 to 12 are any, and the TFET device includes:Grid, source electrode and drain electrode；The source electrode is located at the region on the TFET device where the main shaft pattern, and the grid surrounds the source electrode, and the drain electrode is located at the region on the TFET device in addition to the source electrode and the grid；Or,The drain electrode is located at main shaft pattern region on the TFET device, and the grid surrounds the drain electrode, and the source electrode is located at the region on the TFET device in addition to the drain electrode and the grid.
- TFET device according to claim 13, which is characterized in that the main shaft pattern is cross pattern, and the grid includes four L-type grids between the source electrode and the drain electrode.
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| JP2006332098A (en) * | 2005-05-23 | 2006-12-07 | Renesas Technology Corp | Semiconductor device and its fabrication process |
| CN101958325B (en) * | 2009-07-16 | 2013-09-11 | 中芯国际集成电路制造(上海)有限公司 | SONOS (Silicon Oxide Nitride Oxide Semiconductor) flash memory unit and formation method thereof |
| CN102544104A (en) * | 2012-01-12 | 2012-07-04 | 清华大学 | High-voltage resistant tunneling transistor and preparation method thereof |
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| US5965914A (en) * | 1997-06-18 | 1999-10-12 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor having a branched gate and channel |
| US6232633B1 (en) * | 1998-06-08 | 2001-05-15 | International Business Machines Corporation | NVRAM cell using sharp tip for tunnel erase |
| CN101609816A (en) * | 2008-06-20 | 2009-12-23 | 东部高科股份有限公司 | The manufacture method of semiconductor device |
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Application publication date: 20190319 |