CN109446021B - DDR monitoring method for dual-core SOC of aerostat occultation receiver - Google Patents
DDR monitoring method for dual-core SOC of aerostat occultation receiver Download PDFInfo
- Publication number
- CN109446021B CN109446021B CN201811166699.3A CN201811166699A CN109446021B CN 109446021 B CN109446021 B CN 109446021B CN 201811166699 A CN201811166699 A CN 201811166699A CN 109446021 B CN109446021 B CN 109446021B
- Authority
- CN
- China
- Prior art keywords
- core
- ddr
- code
- data
- codes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/61—Installation
- G06F8/63—Image based installation; Cloning; Build to order
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4406—Loading of operating system
- G06F9/441—Multiboot arrangements, i.e. selecting an operating system to be loaded
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Quality & Reliability (AREA)
- Computer Security & Cryptography (AREA)
- Storage Device Security (AREA)
- Hardware Redundancy (AREA)
Abstract
The invention discloses a DDR monitoring method for a dual-core SOC of a occultation receiver of an aerostat, which comprises the steps of dividing a DDR space for code operation in two kernel code configuration files of the SOC, and compiling and manufacturing a burning file of codes; making an FPGA bit stream file and a system starting file; respectively distributing the core 0 and core 1 burning program three backups to fixed addresses in the FLASH; after the system is powered on and operated, the starting code loads the three-backup core 0 and core 1 programs into corresponding addresses of the DDR after respectively taking 2 from 3, and after the core 0 is started, the core 1 is guided to operate; in normal operation of the system, the DDR monitoring function in any core code of the core 0 or the core 1 respectively reads three backup files of the core 0 and the core 1 in the FLASH and compares the three backup files with data of corresponding addresses in the DDR. The invention only uses 1 kernel to monitor the write-back of the dual-core code, enhances the single event resistance of the system and reduces the risk of delayed interrupt response of the system.
Description
Technical Field
The invention belongs to the technical field of memory monitoring, and particularly relates to a DDR (double data rate) monitoring method for a dual-core SOC (system on chip) of an aerostat occultation receiver.
Background
A large amount of high-energy charged particles exist in a space environment, and the potential of the CMOS device is easy to jump. Program storage devices such as SRAM, DDR and the like in the on-track device are susceptible to single event, so that codes are abnormally operated, and the space device can be seriously failed, therefore, an SRAM chip with an EDAC function is selected or a memory device monitoring method is designed.
The SRAM memory chip with the EDAC function can correct error bits by using an EDAC error correction circuit when single bit upset occurs, so that normal operation of a system is guaranteed, but when multi-bit upset occurs, the EDAC function cannot effectively correct error data, and abnormal operation is caused.
The current memory monitoring scheme mainly aims at a single-core controller such as a single-core DSP, an ARM chip and the like, reads data in FLASH and compares the data with programs in SRAM, and writes back if the data is inconsistent with the programs in SRAM. In a conventional monitoring scheme, when a control chip reads a serial FLASH (such as QSPI-FLASH), a fixed read timing sequence needs to be followed, so that an interrupt needs to be temporarily shielded, and the read timing sequence is prevented from being disordered and data errors are prevented. Masking interrupts entails the risk that the interrupt response is delayed, so that conventional solutions are not suitable for use in systems where interrupts are frequent and where there is a strict requirement for interrupt response.
With the development of technology, a Multi-core control chip is developed, and in an Asymmetric Multi-processor mode (abbreviated as AMP), each core can independently run different programs, and perform inter-core data interaction by sharing a memory. One multi-core chip can complete the task which can be completed only by the joint operation of a plurality of chips, thereby reducing the peripheral circuit design of the traditional chip and the data communication design among the chips and enhancing the reliability of the system. At present, a multi-core chip is already applied to the field of aerospace, for monitoring a multi-core control chip memory, the Harbin industry university proposes a monitoring scheme adopting a dual-core mutual detection method, the dual cores run the same codes, and the codes are mutually detected during running so as to ensure the code correctness. However, for a multi-core control chip, the technical advantages of the multi-core controller are not exerted by the fact that the dual cores run the same code.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides a DDR monitoring method for a dual-core SOC of an aerostat occultation receiver, only 1 kernel is used for monitoring and writing back dual-core codes, the single-particle resistance of a system is enhanced, and the risk that the interrupt response of the system is delayed is reduced.
In order to solve the technical problems, the invention adopts the technical scheme that: a DDR monitoring method for a double-core SOC of an aerostat occultation receiver comprises the following steps:
(1) Dividing DDR space for code operation in two kernel code configuration files of the SOC, and compiling a burning file for manufacturing the code;
(2) Making an FPGA bit stream file and a system starting file;
(3) Making a burning file, and respectively distributing the three backups of the burning programs of the core 0 and the core 1 to fixed addresses in the FLASH when the burning file is made;
(4) After the system is powered on and operated, the starting code loads the three-backup core 0 and core 1 programs into corresponding addresses of the DDR after respectively taking 2 out of 3, then jumps to the core 0 to start operation, and after the core 0 is started, guides the core 1 to operate and starts the whole system;
(5) In normal operation of the system, the DDR monitoring function in any core code of the core 0 or the core 1 respectively reads three backup files of the core 0 and the core 1 in the FLASH, the three backup files are compared with codes of corresponding addresses in the DDR, and when the two backup files are not consistent, the codes in the DDR are rewritten.
Preferably, the FLASH type is QSPI-FLASH.
Preferably, in step (5), the DDR monitoring function is located in a background task of the core 1 code, and during the idle period of the system, the function is continuously running, and the main logic of the function is:
(a) Reading a code in the DDR of the core 0;
(b) Reading a code in a QSPI-FLASH corresponding to the core 0;
(c) Comparing the two codes, and rewriting the codes in the DDR if the two codes are not consistent;
(d) Reading codes in the DDR of the core 1;
(e) Reading a code in a QSPI-FLASH corresponding to the core 1;
(f) And comparing the two codes, and rewriting the codes in the DDR if the two codes are not consistent.
Preferably, the core 0 code 3 backup is stored in a fixed address of the QSPI-FLASH chip.
Preferably, the core 1 code 3 backup is stored in a fixed address of the QSPI-FLASH chip.
Preferably, any one of the core 0 or the core 1 reads the three backup data of the core 0 in real time, performs the operation of taking 2 out of 3, compares the data with the data in the DDR address corresponding to the core 0, and rewrites the data in the DDR if the data do not match with the data in the DDR address corresponding to the core 0.
Preferably, any one of the core 0 or the core 1 reads the triple backup data of the core 1 in real time, performs a fetch 2 from 3 operation, compares the triple backup data with the data in the DDR address corresponding to the core 1, and if the triple backup data do not match with the data in the DDR address corresponding to the core 1, rewrites the data in the DDR.
Compared with the prior art, the invention has the beneficial effects that:
1. in the invention, the operation of taking 2 out of 3 of the program is realized in the initial loading and normal running processes of the system, and the correctness of the loaded program is ensured.
2. In the invention, any core carries out DDR monitoring in the normal running process of the system, compared with the scheme that each core independently maintains the DDR code of the core, the other core does not need to shield interruption and then operate QSPI-FLASH to cause interruption response delay, and the rapidity of the system for interruption response is ensured. The reliability of the space electronic equipment is enhanced.
3. In the invention, the dual cores of the system run different codes to process different tasks, thereby exerting the technical advantages of the multi-core processor.
Drawings
FIG. 1 is a schematic flow chart of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
The embodiment of the invention discloses a DDR monitoring method for a double-core SOC of an aerostat occultation receiver, which comprises the following steps as shown in the figure:
(1) Dividing DDR space for code operation in two kernel code configuration files of the SOC, and compiling a burning file for manufacturing the code;
(2) Making an FPGA bit stream file and a system starting file;
(3) Making a burning file, and respectively distributing the three backups of the burning programs of the core 0 and the core 1 to fixed addresses in the FLASH when the burning file is made;
(4) After the system is powered on and operated, the starting code loads the three-backup core 0 and core 1 programs into corresponding addresses of the DDR after respectively taking 2 out of 3, then jumps to the core 0 to start operation, and after the core 0 is started, guides the core 1 to operate and starts the whole system;
(5) In the normal operation of the system, the DDR monitoring function in any one of the core codes of the core 0 or the core 1 respectively reads the three backup files of the core 0 and the core 1 in the FLASH, the three backup files are compared with the codes of the corresponding addresses in the DDR, and when the two backup files are not consistent, the codes in the DDR are rewritten.
In this embodiment, the FLASH type is QSPI-FLASH.
In this embodiment, in step (5), the DDR monitor function is located in a background task of the core 1 code, and during the idle period of the system, the function is continuously run, and the main logic of the function is:
(a) Reading a DDR middle code of the core 0;
(b) Reading a code in a QSPI-FLASH corresponding to the core 0;
(c) Comparing the two codes, and rewriting the codes in the DDR if the two codes are not consistent;
(d) Reading codes in the DDR of the core 1;
(e) Reading a code in a QSPI-FLASH corresponding to the core 1;
(f) And comparing the two codes, and rewriting the codes in the DDR if the two codes are not consistent.
In this embodiment, the core 0 code 3 backup is stored in the fixed address of the QSPI-FLASH chip.
In this embodiment, the core 1 code 3 is backed up and stored in the fixed address of the QSPI-FLASH chip.
In this embodiment, any one of the core 0 or the core 1 reads the three backup data of the core 0 in real time, performs the operation of taking 2 from 3, compares the three backup data with the data in the DDR address corresponding to the core 0, and if the three backup data are not consistent with the data in the DDR address corresponding to the core 0, rewrites the data in the DDR.
In this embodiment, any one of the core 0 or the core 1 reads the triple backup data of the core 1 in real time, performs the operation of taking 2 out of 3, compares the triple backup data with the data in the DDR address corresponding to the core 1, and if the triple backup data are not consistent with the data in the DDR address corresponding to the core 1, rewrites the data in the DDR.
In this embodiment, the core control chip of the aerostat occultation receiver is a dual-core SOC chip, and operates in an AMP mode, the core 0 and the core 1 run different codes, wherein one core processes frequently interrupted tasks, and the other core processes tasks insensitive to interrupt delay, such as system control, data management, and DDR monitoring.
The present invention has been described in detail with reference to the embodiments, but the description is only illustrative of the present invention and should not be construed as limiting the scope of the invention. The scope of the invention is defined by the claims. The technical solutions of the present invention or those skilled in the art, based on the teachings of the technical solutions of the present invention, should be within the scope of the present invention, and the claims of the present invention should also cover the scope of the present invention by designing similar technical solutions to achieve the above technical effects or by making equivalent changes and improvements in the scope of the present invention. It should be noted that for the sake of clarity, parts of the description of the invention have been omitted where there is no direct explicit connection with the scope of protection of the invention, but where components and processes are known to those skilled in the art.
Claims (5)
1. A DDR monitoring method for a dual-core SOC of an aerostat occultation receiver is characterized by comprising the following steps:
(1) Dividing DDR space for code operation in two kernel code configuration files of the SOC, and compiling a burning file for manufacturing the codes;
(2) Making an FPGA bit stream file and a system starting file;
(3) Making a burning file, and respectively distributing the three backups of the burning programs of the core 0 and the core 1 to fixed addresses in the FLASH when the burning file is made;
(4) After the system is powered on and operated, the starting code loads the three-backup core 0 and core 1 programs which are respectively 3-2 into corresponding addresses of the DDR, then jumps to the core 0 to start operation, guides the core 1 to operate after the core 0 is started, and starts the whole system;
(5) In the normal operation of the system, a DDR monitoring function in any core code of the core 0 or the core 1 respectively reads the three backup files of the core 0 and the core 1 in the FLASH, the three backup files are compared with the codes of corresponding addresses in the DDR, and when the two backup files are inconsistent, the codes in the DDR are rewritten; the FLASH type is QSPI-FLASH; the DDR monitoring function is located in a background task of a core 1 code, the function is continuously operated during the idle period of the system, and the logic of the function is as follows:
(a) Reading a DDR middle code of the core 0;
(b) Reading a code in a QSPI-FLASH corresponding to the core 0;
(c) Comparing the two codes, and rewriting the codes in the DDR if the two codes are not consistent;
(d) Reading a code in a DDR of the core 1;
(e) Reading a code in a QSPI-FLASH corresponding to the core 1;
(f) And comparing the two codes, and rewriting the codes in the DDR if the two codes are not consistent.
2. The DDR monitoring method for the dual core SOC of the occultation receiver of the aerostat according to claim 1, wherein the core 0 code 3 backup is stored in a fixed address of the QSPI-FLASH chip.
3. The DDR monitoring method for the dual core SOC of the occultation receiver of the aerostat according to claim 1, wherein the core 1 code 3 backup is stored in a fixed address of the QSPI-FLASH chip.
4. The DDR monitoring method for the dual-core SOC of the occultation receiver of the aerostat as recited in claim 1, wherein any one of the core 0 or the core 1 reads three backup data of the core 0 in real time, and performs a 2 out of 3 operation, compares the data with data in a DDR address corresponding to the core 0, and rewrites the data in the DDR if the data is inconsistent.
5. The DDR monitoring method for the dual-core SOC of the occultation receiver of the aerostat as recited in claim 1, wherein any one of the core 0 and the core 1 reads three backup data of the core 1 in real time, and performs a 2 out of 3 operation, compares the data with data in a DDR address corresponding to the core 1, and if the data are not consistent, rewrites the data in the DDR.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811166699.3A CN109446021B (en) | 2018-09-30 | 2018-09-30 | DDR monitoring method for dual-core SOC of aerostat occultation receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811166699.3A CN109446021B (en) | 2018-09-30 | 2018-09-30 | DDR monitoring method for dual-core SOC of aerostat occultation receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109446021A CN109446021A (en) | 2019-03-08 |
| CN109446021B true CN109446021B (en) | 2022-11-22 |
Family
ID=65544632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811166699.3A Active CN109446021B (en) | 2018-09-30 | 2018-09-30 | DDR monitoring method for dual-core SOC of aerostat occultation receiver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109446021B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106484581A (en) * | 2016-10-25 | 2017-03-08 | 哈尔滨工业大学 | Programmable SOC device single-particle inversion detecting system and method under space radiation environment |
| CN108021530A (en) * | 2017-12-22 | 2018-05-11 | 北京卫星信息工程研究所 | The in-orbit reconstructing method of general signal processing platform based on SOC |
| CN108228525A (en) * | 2016-12-13 | 2018-06-29 | 北京迪文科技有限公司 | A kind of the application solutions device and method of 8051 processor SOC of multinuclear |
| CN108279935A (en) * | 2016-12-30 | 2018-07-13 | 北京中科晶上科技股份有限公司 | A kind of os starting bootstrap technique for system on chip |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2554349B (en) * | 2016-09-13 | 2018-10-17 | Imagination Tech Ltd | Build-time memory manangement for multi-core embedded system |
-
2018
- 2018-09-30 CN CN201811166699.3A patent/CN109446021B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106484581A (en) * | 2016-10-25 | 2017-03-08 | 哈尔滨工业大学 | Programmable SOC device single-particle inversion detecting system and method under space radiation environment |
| CN108228525A (en) * | 2016-12-13 | 2018-06-29 | 北京迪文科技有限公司 | A kind of the application solutions device and method of 8051 processor SOC of multinuclear |
| CN108279935A (en) * | 2016-12-30 | 2018-07-13 | 北京中科晶上科技股份有限公司 | A kind of os starting bootstrap technique for system on chip |
| CN108021530A (en) * | 2017-12-22 | 2018-05-11 | 北京卫星信息工程研究所 | The in-orbit reconstructing method of general signal processing platform based on SOC |
Non-Patent Citations (2)
| Title |
|---|
| 双核处理器AMP模式在电力设备控制中的应用;吴相楠等;《单片机与嵌入式***应用》;20180601(第06期);全文 * |
| 基于TMS320C6678的国产DSP操作***引导程序设计;马云等;《电子技术与软件工程》;20180327(第06期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109446021A (en) | 2019-03-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9891917B2 (en) | System and method to increase lockstep core availability | |
| CN102270162B (en) | Fault-tolerant guide method applied to SPARCV8 structure computer | |
| KR102460513B1 (en) | Recovery After Consolidation Package | |
| US8862953B2 (en) | Memory testing with selective use of an error correction code decoder | |
| US20120221884A1 (en) | Error management across hardware and software layers | |
| US20090044044A1 (en) | Device and method for correcting errors in a system having at least two execution units having registers | |
| EP2770507B1 (en) | Memory circuits, method for accessing a memory and method for repairing a memory | |
| US10062451B2 (en) | Background memory test apparatus and methods | |
| US7363544B2 (en) | Program debug method and apparatus | |
| TWI510912B (en) | Fault tolerance in a multi-core circuit | |
| CN103226499A (en) | Method and device for restoring abnormal data in internal memory | |
| US11960748B2 (en) | SSD supporting read-only mode after PLP backup failure | |
| US10108469B2 (en) | Microcomputer and microcomputer system | |
| CN110704236B (en) | On-line checking method for chip flash data and computer storage medium | |
| CN104484202A (en) | Aerospace embedded software on-orbit reloading method applicable to 8051 microcontroller | |
| CN109446021B (en) | DDR monitoring method for dual-core SOC of aerostat occultation receiver | |
| US20140095859A1 (en) | Apparatus and method for managing register information in a processing system | |
| Eichler et al. | Neverlast: an NVM-centric operating system for persistent edge systems | |
| US20050015649A1 (en) | Method and system for correcting errors in a memory device | |
| US20160328240A1 (en) | Bios system with simulated cmos | |
| CN111061591B (en) | System and method for implementing data integrity check based on memory integrity check controller | |
| US20180253349A1 (en) | Fault tolerant operating metohd and electronic device using the same | |
| CN109213627B (en) | Fault-tolerant operation method and electronic device using same | |
| JPH0644238B2 (en) | Instruction re-execution control method | |
| Schneider et al. | Multicore vs safety |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |