CN109446021A - A kind of DDR monitoring method for aerostatics Occultation receiver double-core SOC - Google Patents
A kind of DDR monitoring method for aerostatics Occultation receiver double-core SOC Download PDFInfo
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- CN109446021A CN109446021A CN201811166699.3A CN201811166699A CN109446021A CN 109446021 A CN109446021 A CN 109446021A CN 201811166699 A CN201811166699 A CN 201811166699A CN 109446021 A CN109446021 A CN 109446021A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4406—Loading of operating system
- G06F9/441—Multiboot arrangements, i.e. selecting an operating system to be loaded
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Abstract
The present invention discloses a kind of DDR monitoring method for aerostatics Occultation receiver double-core SOC, in two kernel code configuration files of SOC, divides the space DDR of code operation, the recordable paper of rear compiling production code；Make FPGA bit stream file and System startup files；Core 0,1 burning program three of core are backed up into the fixing address being assigned in FLASH respectively；System electrification operation after, starting code by three backup core 0,1 program of core respectively 3 take 2 after, be loaded into the corresponding address of DDR, core 0 start after, guidance core 1 run；During system operates normally, the DDR monitoring function in any core code in core 0 or core 1 reads the three backup files of core 0, core 1 in FLASH respectively, is compared with the data of corresponding address in DDR.The present invention is only monitored write-back with verification double-core code in 1, enhances the anti-single particle ability of system, while reducing system break and responding the risk being delayed by.
Description
Technical field
It is the invention belongs to internal memory monitoring technical field, in particular to a kind of for aerostatics Occultation receiver double-core SOC's
DDR monitoring method.
Background technique
There is a large amount of high energy charged particles in space environment, and the current potential of cmos device is easy to cause to jump.?
Program storage device such as SRAM, DDR in rail equipment etc. are influenced vulnerable to single event, cause code operation abnormal, sternly
Weight will lead to Space Facilities failure, therefore select sram chip or design memory device monitoring side with EDAC function
Method.
SRAM storage chip with EDAC function, can be right using EDAC error correction circuit when single bit upset occurs
Error bit is corrected, thus guarantee the normal operation of system, but when more bit reversals occur, EDAC function can not have
Effect corrects wrong data, causes to be operating abnormally.
Current internal memory monitoring scheme is read mainly in single core controller such as monokaryon DSP, ARM chip etc.
Data are compared with program in SRAM in FLASH, inconsistent then write-back.In traditional monitoring scheme, control chip is reading string
When row FLASH (such as QSPI-FLASH), need to follow fixed reading timing, it is therefore desirable to temporarily be shielded, be prevented to interruption
It is only interrupted and interrupts, cause to read timing entanglement reading error in data.The risk that interrupt response can be brought to be delayed by is interrupted in shielding,
Therefore traditional scheme is not suitable for interrupting frequently, and has in the system of strict demand to interrupt response.
With the development of technology, there is multicore control the chip, (Asymmetric under asymmetric multiprocessor system mode
Multi Processing, is abbreviated as AMP), each core can independent operating distinct program, and core is carried out by way of shared drive
Between data interaction.One achievable tradition of multi core chip needs multiple chips to be operated together could completing for task, reduces
Traditional die periphery circuit design and the design of chip chamber data communication, enhance the reliability of system.Multi core chip has been at present
Through being applied to aerospace field, for multicore control chip memory monitoring, Harbin Institute of Technology proposes mutual using double-core
The monitoring scheme of detecting method, double-core run same code, carry out code in operation and mutually examine, to guarantee code correctness.But it is right
Chip is controlled in multicore, double-core operation same code does not play the technical advantage of multicore controller.
Summary of the invention
The present invention for the technical problems in the prior art, provides a kind of for aerostatics Occultation receiver double-core
The DDR monitoring method of SOC is monitored write-back using only double-core code is checked in 1, enhances the anti-single particle energy of system
Power, while reducing system break and responding the risk being delayed by.
In order to solve the above technical problems, the technical solution adopted by the present invention is that: one kind is double for aerostatics Occultation receiver
The DDR monitoring method of core SOC, comprising the following steps:
(1) in two kernel code configuration files of SOC, the space DDR of code operation is divided, rear compiling production code
Recordable paper；
(2) FPGA bit stream file and System startup files are made；
(3) recordable paper is made, in recordable paper production, is respectively assigned to core 0, the backup of 1 burning program three of core
Fixing address in FLASH；
(4) system electrification operation after, starting code by three backup core 0,1 program of core respectively 3 take 2 after, be loaded into DDR's
In corresponding address, the starting operation of core 0 is then branched to, after core 0 starts, guidance core 1 is run, whole system starting；
(5) during system operates normally, the DDR monitoring function in any core code in core 0 or core 1 reads core 0, core respectively
The 1 three backup files in FLASH are compared with the code of corresponding address in DDR, when the two is inconsistent, rewrite in DDR
Code.
Preferably, FLASH type is QSPI-FLASH.
Preferably, DDR monitoring function is located in the background task of 1 code of core in step (5), during system is idle,
The function is constantly run, the main logic of the function are as follows:
(a) code in the DDR of core 0 is read；
(b) code in the corresponding QSPI-FLASH of core 0 is read；
(c) the two is compared, if it is inconsistent, rewriting the code in DDR；
(d) code in the DDR of core 1 is read；
(e) code in the corresponding QSPI-FLASH of core 1 is read；
(f) the two is compared, if it is inconsistent, rewriting the code in DDR.
Preferably, the backup of 0 code 3 of core is stored in the fixing address of QSPI-FLASH chip.
Preferably, the backup of 1 code 3 of core is stored in the fixing address of QSPI-FLASH chip.
Preferably, reading three Backup Datas of core 0 when any verification in core 0 or core 1, and carries out 3 and take 2 operations, with
Data in the corresponding address DDR of core 0 are compared, if inconsistent, rewrite data in DDR.
Preferably, reading three Backup Datas of core 1 when any verification in core 0 or core 1, and carries out 3 and take 2 operations, with
Data in the corresponding address DDR of core 1 are compared, if inconsistent, rewrite data in DDR.
Compared with prior art, the present invention has the beneficial effects that
1. in the present invention, in system initial loading and normal course of operation, realizing the 3 of program and taking 2 operations, ensure that
The correctness of loading procedure.
2. in the present invention, in system normal course of operation, carrying out DDR monitoring by any core, solely being tieed up compared to each vouching
The scheme for protecting itself DDR code, operation QSPI-FLASH causes to interrupt after making another core that need not shield interruption in the process of running
Operating lag ensure that system for the rapidity of interrupt response.Enhance the reliability of space electronic equipment.
3. in the present invention, the double-core of system runs different code, different task is handled, the technology of multi-core processor has been played
Advantage.
Detailed description of the invention
Fig. 1 is flow diagram of the invention.
Specific embodiment
Technical solution in order to enable those skilled in the art to better understand the present invention, in the following with reference to the drawings and specific embodiments
It elaborates to the present invention.
Embodiment of the invention discloses a kind of DDR monitoring methods for aerostatics Occultation receiver double-core SOC, such as scheme
It is shown comprising following steps:
(1) in two kernel code configuration files of SOC, the space DDR of code operation is divided, rear compiling production code
Recordable paper；
(2) FPGA bit stream file and System startup files are made；
(3) recordable paper is made, in recordable paper production, is respectively assigned to core 0, the backup of 1 burning program three of core
Fixing address in FLASH；
(4) system electrification operation after, starting code by three backup core 0,1 program of core respectively 3 take 2 after, be loaded into DDR's
In corresponding address, the starting operation of core 0 is then branched to, after core 0 starts, guidance core 1 is run, whole system starting；
(5) during system operates normally, the DDR monitoring function in any core code in core 0 or core 1 reads core 0, core respectively
The 1 three backup files in FLASH are compared with the code of corresponding address in DDR, when the two is inconsistent, rewrite in DDR
Code.
In the present embodiment, FLASH type is QSPI-FLASH.
In the present embodiment, in step (5), DDR monitoring function is located in the background task of 1 code of core, in system idle periods
Between, which constantly runs, the main logic of the function are as follows:
(a) code in the DDR of core 0 is read；
(b) code in the corresponding QSPI-FLASH of core 0 is read；
(c) the two is compared, if it is inconsistent, rewriting the code in DDR；
(d) code in the DDR of core 1 is read；
(e) code in the corresponding QSPI-FLASH of core 1 is read；
(f) the two is compared, if it is inconsistent, rewriting the code in DDR.
In the present embodiment, the backup of 0 code 3 of core is stored in the fixing address of QSPI-FLASH chip.
In the present embodiment, the backup of 1 code 3 of core is stored in the fixing address of QSPI-FLASH chip.
In the present embodiment, when any verification in core 0 or core 1, reads three Backup Datas of core 0, and carries out 3 and take 2 operations,
It is compared with the data in the corresponding address DDR of core 0, if inconsistent, rewrites data in DDR.
In the present embodiment, when any verification in core 0 or core 1, reads three Backup Datas of core 1, and carries out 3 and take 2 operations,
It is compared with the data in the corresponding address DDR of core 1, if inconsistent, rewrites data in DDR.
In the present embodiment, aerostatics Occultation receiver kernel control chip is a double-core SOC chip, is worked in AMP mould
Formula, 0 core 1 of core run different code, wherein a core handles frequent interrupt task, another core processing system control, data management,
DDR monitoring etc. is to the interrupting delay-insensitive of the task.
It is described the invention in detail above by embodiment, but the content is only exemplary implementation of the invention
Example, should not be considered as limiting the scope of the invention.Protection scope of the present invention is defined by the claims.All utilizations
Technical solutions according to the invention or those skilled in the art are under the inspiration of technical solution of the present invention, in reality of the invention
In matter and protection scope, designs similar technical solution and reach above-mentioned technical effect, or to made by application range
All the changes and improvements etc. should still belong to patent of the invention and cover within protection scope.It should be noted that in order to clear
It is stated, part and protection scope of the present invention is omitted in explanation of the invention without being directly significantly associated with but this field skill
The statement of component known to art personnel and processing.
Claims (7)
1. a kind of DDR monitoring method for aerostatics Occultation receiver double-core SOC, which comprises the following steps:
(1) in two kernel code configuration files of SOC, the space DDR of code operation, the burning of rear compiling production code are divided
File；
(2) FPGA bit stream file and System startup files are made；
(3) recordable paper is made, in recordable paper production, core 0, the backup of 1 burning program three of core are assigned in FLASH respectively
Fixing address；
(4) system electrification operation after, starting code by three backup core 0,1 program of core respectively 3 take 2 after, be loaded into the correspondence of DDR
In address, the starting operation of core 0 is then branched to, after core 0 starts, guidance core 1 is run, whole system starting；
(5) during system operates normally, function reads core 0 to the DDR monitoring in any core code in core 0 or core 1 respectively, core 1 exists
Three backup files in FLASH, are compared with the code of corresponding address in DDR, when the two is inconsistent, rewrite in DDR
Code.
2. a kind of DDR monitoring method for aerostatics Occultation receiver double-core SOC according to claim 1, feature
It is, FLASH type is QSPI-FLASH.
3. a kind of DDR monitoring method for aerostatics Occultation receiver double-core SOC according to claim 2, feature
It is, in step (5), DDR monitoring function is located in the background task of 1 code of core, and during system is idle, which is constantly transported
Row, the main logic of the function are as follows:
(a) code in the DDR of core 0 is read；
(b) code in the corresponding QSPI-FLASH of core 0 is read；
(c) the two is compared, if it is inconsistent, rewriting the code in DDR；
(d) code in the DDR of core 1 is read；
(e) code in the corresponding QSPI-FLASH of core 1 is read；
(f) the two is compared, if it is inconsistent, rewriting the code in DDR.
4. a kind of DDR monitoring method for aerostatics Occultation receiver double-core SOC according to claim 2, feature
It is, the backup of 0 code 3 of core is stored in the fixing address of QSPI-FLASH chip.
5. a kind of DDR monitoring method for aerostatics Occultation receiver double-core SOC according to claim 2, feature
It is, the backup of 1 code 3 of core is stored in the fixing address of QSPI-FLASH chip.
6. a kind of DDR monitoring method for aerostatics Occultation receiver double-core SOC according to claim 1, feature
It is, when any verification in core 0 or core 1, reads three Backup Datas of core 0, and carries out 3 and take 2 operations, DDR corresponding with core 0
Data in location are compared, if inconsistent, rewrite data in DDR.
7. a kind of DDR monitoring method for aerostatics Occultation receiver double-core SOC according to claim 1, feature
It is, when any verification in core 0 or core 1, reads three Backup Datas of core 1, and carries out 3 and take 2 operations, DDR corresponding with core 1
Data in location are compared, if inconsistent, rewrite data in DDR.
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| CN201811166699.3A CN109446021B (en) | 2018-09-30 | 2018-09-30 | DDR monitoring method for dual-core SOC of aerostat occultation receiver |
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| CN201811166699.3A CN109446021B (en) | 2018-09-30 | 2018-09-30 | DDR monitoring method for dual-core SOC of aerostat occultation receiver |
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