CN109427658B - 掩模组件和用于制造芯片封装件的方法 - Google Patents

掩模组件和用于制造芯片封装件的方法 Download PDF

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CN109427658B
CN109427658B CN201810460875.8A CN201810460875A CN109427658B CN 109427658 B CN109427658 B CN 109427658B CN 201810460875 A CN201810460875 A CN 201810460875A CN 109427658 B CN109427658 B CN 109427658B
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alignment
mask
photoresist layer
opening
conductive
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CN109427658A (zh
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陈洁
陈宪伟
刘醇鸿
陈英儒
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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Abstract

依次提供第一掩模和第二掩模以实施多步曝光和显影工艺。通过第一掩模和第二掩模的适当的重叠设计，形成具有可接受重叠偏移的导电布线。本发明的实施例还涉及掩模组件和用于制造芯片封装件的方法。

Description

掩模组件和用于制造芯片封装件的方法
技术领域
本发明的实施例涉及掩模组件和用于制造芯片封装件的方法。
背景技术
由于各个电组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续改进，半导体工业已经经历了快速增长。对于大部分而言，这种集成密度的改进来自于最小部件尺寸的连续减小，这使得更多的组件集成到给定的区域。这些更小的电组件也需要比先前的封装件利用更小面积的更小封装件。用于半导体组件的一些更小类型的封装件包括四方扁平封装(QFP)、引脚网格阵列(PGA)封装、球栅阵列(BGA)封装等。
集成扇出封装件是用于芯片和***之间异构集成的强有力的解决方案。集成扇出封装件提供的改进的可布线性和可靠性是用于未来封装件的关键因素。如何简化制造工艺并且减小集成扇出封装件的制造成本是一个重要问题。
发明内容
本发明的实施例提供了一种用于制造导电布线的方法，包括：图案化光刻胶层，包括：提供包括第一布局图案的第一掩模；实施经由所述第一掩模的第一曝光工艺和第一显影工艺，以在所述光刻胶层的第一部分中形成多个第一布线开口，并且所述光刻胶层的第一部分由所述第一掩模覆盖；提供包括第二布局图案的第二掩模；实施经由所述第二掩模的第二曝光工艺和第二显影工艺，以在所述光刻胶层的第二部分中形成多个第二布线开口，所述光刻胶层的第一部分和第二部分的重叠部分由所述第二掩模覆盖，所述第一布线开口和所述第二布线开口在所述重叠部分处连通，并且当实施所述第二曝光工艺时，所述第二掩模的所述第二布局图案与形成在所述光刻胶层中的所述第一布线开口对准；以及在所述第一布线开口和所述第二布线开口中形成导电布线。
本发明的另一实施例提供了一种用于制造导电布线的方法，包括：图案化光刻胶层，包括：提供包括第一对准图案和第一布局图案的第一掩模；实施经由所述第一掩模的第一曝光工艺和第一显影工艺，以在所述光刻胶层的第一部分中形成第一对准开口和多个第一布线开口，并且所述光刻胶层的第一部分由所述第一掩模覆盖；提供包括第二对准图案和第二布局图案的第二掩模；实施经由所述第二掩模的第二曝光工艺和第二显影工艺，以在所述光刻胶层的第二部分中形成多个第二布线开口，所述光刻胶层的第一部分和第二部分的重叠部分由所述第二掩模覆盖，并且当实施所述第二曝光工艺时，所述第二掩模的所述第二对准图案与形成在所述光刻胶层中的所述第一对准开口对准；在所述第一对准开口中形成对准标记；以及在所述第一布线开口和所述第二布线开口中形成导电布线。
本发明的又一实施例提供了一种用于制造芯片封装件的方法，包括：形成绝缘密封件以横向密封至少一个集成电路组件的侧壁；在所述至少一个集成电路组件和所述绝缘密封件上形成导电层；在所述导电层上形成光刻胶层，并且实施多步曝光和显影工艺以图案化所述光刻胶层，其中，实施所述多步曝光和显影工艺以图案化所述光刻胶层包括：提供包括第一对准图案和第一布局图案的第一掩模；实施经由所述第一掩模的第一步曝光工艺和第一显影工艺，以在所述光刻胶层的第一部分中形成第一对准开口和多个第一布线开口，并且所述光刻胶层的第一部分由所述第一掩模覆盖；提供包括第二对准图案和第二布局图案的第二掩模；实施经由所述第二掩模的第二步曝光工艺和第二显影工艺，以在所述光刻胶层的第二部分中形成多个第二布线开口，所述光刻胶层的第一部分和第二部分的一部分由所述第二掩模覆盖，并且当实施所述第二步曝光工艺时，所述第二掩模的所述第二对准图案与形成在所述光刻胶层中的所述第一对准开口对准；在所述第一对准开口中形成对准标记；在所述第一布线开口和所述第二布线开口中形成多个导电布线，其中，所述导电布线电连接至所述至少一个集成电路组件。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图5示意性示出了根据本发明的一些实施例的用于制造集成电路组件的工艺流程。
图6至图13示意性示出了根据本发明的一些实施例的用于制造芯片封装件的工艺流程。
图14是根据本发明的一些实施例的示出堆叠式封装(POP)结构的截面图。
图15示意性示出了根据本发明的一些实施例的用于制造导电布线的流程图。
图16A至图16F示意性示出了根据本发明的一些实施例用于在再分布电路结构220中制造导电布线(即，再分布导电层224)的工艺流程。
图17A示意性示出了根据本发明的一些实施例的图16A所示的第一掩模M1和图16B所示的重叠部分OL的俯视图。
图17B示意性示出了根据本发明的一些实施例的图16C所示的第二掩模M2和图16D所示的重叠部分OL的俯视图。
图17C示意性示出了根据本发明的一些实施例的图16E所示的重叠部分OL的俯视图。
图18A示意性示出了根据本发明的一些可选实施例的图16A所示的第一掩模M1和图16B所示的重叠部分OL的俯视图。
图18B示意性示出了根据本发明的一些可选实施例的图16C所示的第二掩模M2和图16D所示的重叠部分OL的俯视图。
图18C示意性示出了根据本发明的一些可选实施例的图16E所示的重叠部分OL的俯视图。
图19示意性示出了根据本发明的一些实施例的用于制造导电布线的另一工艺流程。
图20A示意性示出了根据本发明的一些可选实施例的图16A所示的第一掩模M1和图16B所示的重叠部分OL的俯视图。
图20B示意性示出了根据本发明的一些可选实施例的图16C所示的第二掩模M2和图16D所示的重叠部分OL的俯视图。
图20C示意性示出了根据本发明的一些可选实施例的图16E所示的重叠部分OL的俯视图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
也可以包括其它部件和工艺。例如，可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘，以允许使用探针和/或探针卡等测试3D封装件或3DIC。可以在中间结构以及最终结构上实施验证测试。此外，本文公开的结构和方法可以与结合已知良好管芯的中间验证的测试方法结合使用以提高良率和降低成本。
图1至图5示意性示出了根据本发明的一些实施例的用于制造集成电路组件的工艺流程。参照图1，提供了包括布置为阵列的多个集成电路组件100的晶圆W。如图1所示，在对晶圆W实施晶圆锯切或切割工艺之前，晶圆W的集成电路组件100彼此物理连接。在一些实施例中，每个集成电路组件100均包括半导体衬底110和设置在半导体衬底110上的互连结构 120。半导体衬底110可以是硅衬底，硅衬底包括形成在其中的有源组件(例如，晶体管等)和无源组件(例如，电阻器、电容器、电感器等)。互连结构120可以包括交替堆叠的多个介电层122和多个图案化导电层124。例如，介电层122可以是氧化硅层、氮化硅层、氮氧化硅层或由其它合适的介电材料形成的介电层，并且图案化导电层124可以是图案化铜层或其它合适的图案化金属层。
如图1所示，最顶图案化导电层124由介电层122的最顶介电层122 覆盖，并且最顶图案化导电层124由最顶介电层122的多个开口O1暴露。
参照图2，在晶圆W上形成多个导电柱130，导电柱130可以通过镀工艺形成。在一些实施例中，可以在晶圆W上溅射晶种层(例如，Ti/Cu 晶种层)并且之后，在晶种层上形成图案化的光刻胶。将其上形成有晶种层和图案化的光刻胶的晶圆W浸入镀槽中，从而将导电柱130镀在由图案化的光刻胶暴露的晶种层的一部分上。导电柱130对应于最顶介电层122 的开口O1。在将导电柱130镀至暴露的晶种层上之后，去除图案化的光刻胶。之后，通过使用导电柱130作为硬掩模去除并且图案化晶种层，直至暴露最顶介电层122。在一些实施例中，导电柱130可以是铜柱或其它合适的金属柱。
如图2所示，导电柱130可以包括柱部分132和位于柱部分132与最顶图案化导电层124之间的晶种图案134。在一些实施例中，导电柱130 的柱部分132的材料和最顶图案化导电层124的材料基本相同。导电柱130 的晶种图案134与柱部分132和最顶图案化导电层124接触。通过适当选择晶种图案134和最顶图案化导电层124的材料，可以增强导电柱130(例如，晶种图案134)和最顶图案化导电层124之间的粘合。铜柱部分132 和Ti/Cu晶种图案134对电迁移具有良好的抗性并且具有低电阻率，并且最顶图案化导电层124(例如铜层)与Ti/Cu晶种图案134之间的界面可以引起较少等效串联电感(ESL)及/或等效串联电阻(ESR)。
参照图3，为了检查导电柱130和/或集成电路组件100的电特性，在导电柱130的顶面上形成多个导电帽CAP。在一些实施例中，导电帽CAP 可以是焊帽。例如，上述焊帽可以是无铅焊帽。之后，对导电帽CAP实施芯片探测工艺，以检查导电柱130和/或集成电路组件100的电特性。在芯片探测工艺期间，将检测探针压至导电帽CAP，并且因此可以在导电帽CAP的顶面上形成探测标记。然而，因为导电帽CAP将被去除，所以形成在导电帽CAP的顶面上的探测标记不会使导电柱130和集成电路组件100的可靠性劣化，如图8所示。
参照图4，在晶圆W上方形成保护层140，从而使得导电帽CAP和导电柱130由保护层140覆盖或密封。导电帽CAP和导电柱130由保护层140 保护。在一些实施例中，保护层140可以是聚酰亚胺(PI)层、聚苯并恶唑(PBO)层或其它合适的聚合物或有机层。在形成保护层140之后，可以实施晶圆W的背侧研磨工艺，从而减薄晶圆W至具有预定厚度。在晶圆W的背侧研磨工艺期间，保护层140保护导电柱130免受损坏。
参照图5，沿着划线SL实施晶圆切割工艺或晶圆分割工艺，从而使得晶圆W被分割成多个集成电路组件100a。每个分割的集成电路组件100a 均包括半导体衬底110a、设置在半导体衬底110a上的互连结构120a、导电柱130和保护层140a。保护层140a覆盖互连结构120a。导电柱130由保护层140a密封。在晶圆切割或分割工艺期间，保护层140a保护导电柱130免受损坏。
图6至图13示意性示出了根据本发明的一些实施例的用于制造芯片封装件的工艺流程。
参照图6，提供其上形成有分离层DB和介电层DI的载体C，其中，分离层DB位于载体C和介电层DI之间。在一些实施例中，例如，载体C 是玻璃衬底，分离层DB是形成在玻璃衬底上的光热转换(LTHC)释放层，并且介电层DI是形成在分离层DB上的聚苯并恶唑(PBO)层。在一些可选实施例中，分离层DB可以是通过光固化工艺降低粘性的可光固化释放膜或通过热固化工艺降低粘性的可热固化释放膜，并且介电层DI可以由其它光敏或非光敏介电材料制成。在提供其上形成有分离层DB和介电层DI 的载体C之后，在介电层DI上形成多个导电绝缘通孔(穿过绝缘体的导电通孔)TIV。在一些实施例中，通过光刻胶涂覆、光刻、镀和光刻胶剥离工艺形成导电绝缘通孔TIV。例如，导电绝缘通孔TIV包括铜杆或其它合适的金属杆。
在一些实施例中，将至少一个分割的集成电路组件100a(包括分布在其上的导电柱130)拾取和放置在介电层DI上。集成电路组件100a通过管芯附着膜(DAF)、粘合胶等附接或粘合至介电层DI上。在一些可选实施例中，可以将两个或多个集成电路组件100a拾取和放置在介电层DI上，并且放置在介电层DI上的集成电路组件100a可以布置为阵列。
参照图7，将集成电路组件100a拾取和放置在介电层DI上。在一些实施例中，在导电绝缘通孔TIV的形成之后将集成电路组件100a拾取和放置在介电层DI上。在一些可选实施例中，在导电绝缘通孔TIV的形成之前将集成电路组件100a拾取和放置在介电层DI上。
如图7所示，在介电层DI上形成绝缘密封件210以覆盖至少一个集成电路组件100a和导电绝缘通孔TIV。在一些实施例中，绝缘密封件210是通过模制工艺(例如压缩模制工艺)形成的模塑料。集成电路组件100a的导电柱130和保护层140a由绝缘密封件210覆盖。换句话说，集成电路组件100a的导电柱130和保护层140a没有被暴露并且由绝缘密封件210保护。在一些实施例中，绝缘密封件210包括环氧树脂或其它合适的介电材料。
参照图7和图8，研磨绝缘密封件210直至暴露导电柱130的顶面和保护层140a的顶面。在一些实施例中，通过机械研磨工艺和/或化学机械抛光(CMP)工艺研磨绝缘密封件210。在研磨绝缘密封件210之后，在介电层DI上方形成绝缘密封件210’。在绝缘密封件210的研磨期间，研磨保护层140a、导电帽CAP和导电柱130直至暴露导电柱130的顶面。由于研磨导电帽CAP，因此形成在导电帽CAP的顶面上的探测标记不会使导电柱130和集成电路组件100a的可靠性劣化。在实施绝缘密封件210的研磨工艺之后，形成研磨的保护层140a’。在一些实施例中，在绝缘密封件210 的研磨工艺期间，也部分地研磨导电绝缘通孔TIV。
如图8所示，绝缘密封件210’横向密封至少一个集成电路组件100a的侧壁，绝缘密封件210’由导电绝缘通孔TIV穿透。换句话说，集成电路组件100a和导电绝缘通孔TIV嵌入在绝缘密封件210’内。应该注意，导电绝缘通孔TIV的顶面、绝缘密封件210’的顶面以及导电柱130的顶面可以与保护层140a’的顶面基本共面。
参照图9，在形成绝缘密封件210’和保护层140a’之后，在导电绝缘通孔TIV的顶面、绝缘密封件210’的顶面、导电柱130的顶面以及保护层140a’的顶面上形成再分布电路结构220，再分布电路结构220电连接至集成电路组件100a的导电柱130。如图9所示，再分布电路结构220包括交替堆叠的多个介电层222和多个再分布导电层224。在一些实施例中，导电柱 130的顶面和导电绝缘通孔TIV的顶面与再分布电路结构220接触。在本实施例中，如图9所示，例如，介电层222包括四个介电层222，并且再分布导电层224包括三个再分布导电层224。
此外，多个焊盘230形成在最顶的一个介电层222上，并且电连接至最顶的一个再分布导电层224。焊盘230包括用于植球的多个球下金属 (UBM)图案230a和用于安装无源组件的多个连接焊盘230b。焊盘230 通过再分布层224电连接至集成电路组件100a的导电柱130和导电绝缘柱 TIV。应该注意，UBM图案230a和连接焊盘230b的数量不限于本发明。
由于由至少一个集成电路组件100a、绝缘密封件210’和导电绝缘通孔 TIV提供的上述再分布电路结构220的布局面积非常大，因此再分布电路结构220中的再分布导电层224和/或介电层222的图案化工艺(即，光刻工艺)可能由于工具容量而不能经由单个掩模实施。应该注意，再分布导电层224和介电层222可以具有不同的图案，并且因此，在本实施例中，每个包括多个掩模的不同掩模配置均可以用于再分布导电层224和介电层 222的制造工艺。在一些可选实施例中，再分布电路结构220可以仅包括两个介电层222和夹在两个介电层222之间的一个再分布导电层224。应该注意，介电层222和再分布导电层224的数量不限于本发明。
结合图15、图16A至图16F、图17A至图17C、图18A至图18C、图 19和图20A至图20C描述再分布电路结构220中的至少一个再分布导电层 224的制造。
参照图10，在形成UBM图案230a和连接焊盘230b之后，将多个导电球240放置在球下金属图案230a上，并且将多个无源组件250安装在连接焊盘230b上。在一些实施例中，可以通过球植工艺将导电球240放置在球下金属图案230a上，并且可以通过焊料或回流工艺将无源组件250安装在连接焊盘230b上。在一些实施例中，例如，导电球240的高度大于无源组件250的高度。应该注意，在将无源组件250安装在连接焊盘230b上之后，最顶部图案化导电层124(例如，铜层)与Ti/Cu晶种图案134之间的界面可以引起较少等效串联电感(ESL)及/或等效串联电阻(ESR)。
参照图10和图11，在将导电球240和无源组件250安装在焊盘230 上之后，将形成在绝缘密封件210’的底面上的介电层DI与分离层DB分离，使得介电层DI与载体C分离。在一些实施例中，分离层DB(例如，LTHC 释放层)可以由UV激光照射，从而使得介电层DI从载体C剥离。
如图12所示，之后，图案化介电层DI，从而形成多个接触开口O2以暴露导电绝缘通孔TIV的底面。接触开口O2的数量和位置对应于导电绝缘通孔TIV的数量。在一些实施例中，通过激光钻孔工艺或其它合适的图案化工艺形成介电层DI的接触开口O2。在一些可选实施例中，可以从绝缘密封件210’的底面完全去除介电层DI，以暴露导电绝缘通孔TIV的底面。
参照图13，在介电层DI中形成接触开口O2之后，将多个导电球260 放置在导电绝缘通孔TIV的由接触开口O2暴露的底面上。而且，例如回流导电球260以与导电绝缘通孔TIV的底面接合。如图13所示，在形成导电球240和导电球260之后，完成具有双侧端子设计(即，导电球240和 260)的集成电路100的集成扇出封装件。
图14是根据本发明的一些实施例的示出堆叠式封装(POP)结构的截面图。参照图14，之后，提供另一封装件300。封装件300是例如存储器器件或其它合适的半导体器件。封装件300堆叠在图13示出的集成扇出封装件上方并且通过导电球260电连接至集成扇出封装件，从而制造堆叠式封装(POP)结构。在一些实施例中，堆叠式封装(POP)结构还可以包括设置在封装件300和图13示出的集成扇出封装件之间的底部填充物(未示出)。底部填充物可以密封导电球260以增强堆叠式封装(POP)结构的可靠性和耐久性。
图15示意性示出了根据本发明的一些实施例的用于制造导电布线的流程图；图16A至图16F示意性示出了根据本发明的一些实施例用于在再分布电路结构220中制造导电布线(即，再分布导电层224)的工艺流程；图17A示意性示出了根据本发明的一些实施例的图16A所示的第一掩模 M1和图16B所示的重叠部分OL的俯视图；图17B示意性示出了根据本发明的一些实施例的图16C所示的第二掩模M2和图16D所示的重叠部分 OL的俯视图；并且图17C示意性示出了根据本发明的一些实施例的图16E 所示的重叠部分OL的俯视图。
参照图15和图16A至图16F，在一些实施例中，用于制造导电布线(在图16F中示出)的方法可以包括图案化光刻胶层PR(步骤S10)并且在光刻胶层中形成导电布线PR(步骤S20)。在一些可选实施例中，用于制造导电布线的方法还可以包括在光刻胶层PR中形成导电布线之后去除光刻胶PR(步骤S30)。应该注意，步骤S30在本发明中是可选的。如图15 所示，实施用于图案化光刻胶层PR的多步曝光和显影工艺(即步骤S10)，并且多步曝光和显影工艺可以包括以下步骤(即，步骤S11、S12、S13和 S14)。
如图16A所示，在一些实施例中，在至少一个集成电路组件100a和绝缘密封件210’上形成导电层C。在形成导电层C之前，可以在至少一个集成电路组件100a和绝缘密封件210’上形成介电层122。介电层122可以包括暴露导电柱130和导电绝缘通孔TIV的顶面的多个接触开口。在形成导电层C之后，在导电层C上形成光刻胶层PR。在一些实施例中，例如，导电层C用作晶种层并且通过溅射工艺形成，而光刻胶层PR通过旋涂工艺形成在导电层C上。
如图15、图16A、图16B和图17A所示，提供包括第一布局图案P1 的第一掩模M1(步骤S11)。第一掩模M1覆盖光刻胶层PR的第一部分 PR1(例如，左部分)，但第一掩模M1不覆盖光刻胶层PR的第二部分PR2 (例如，右部分)。第一掩模M1包括第一重叠区OL1。在一些实施例中，第一掩模M1的第一布局图案P1可以包括具有多个第一光透射区域T1的第一光屏蔽图案。之后，实施经由第一掩模M1的第一曝光工艺E1和第一显影工艺(步骤S12)，以在光刻胶层PR的第一部分PR1中形成多个第一布线开口OP1。通过第一掩模M1的第一布局图案P1的屏蔽，部分图案化光刻胶层PR，并且可以在光刻胶层PR的第一部分PR1中形成对应于第一光透射区域T1的第一布线开口OP1。如图16B所示，导电层C由形成在光刻胶层PR的第一部分PR1中的第一布线开口OP1部分地暴露。
在一些实施例中，为了防止暴露光刻胶层PR的第二部分PR2，第一掩模M1可以由光屏蔽构件SH1(在图17A中示出)固定，并且光屏蔽构件 SH1可以屏蔽光刻胶层PR的第二部分PR2。在一些可选实施例中，为了防止暴露光刻胶层PR的第二部分PR2，可以提供光屏蔽构件SH1(在图17A 中示出)来屏蔽光刻胶层PR的第二部分PR2，并且第一掩模M1可以不由光屏蔽构件SH1固定。在另一实施例中，通过适当地控制在第一曝光工艺 E1中使用的光源，可以防止光刻胶层PR的第二部分PR2的不期望的曝光。例如，可以电控制(例如，仅导通对应于光刻胶层PR的重叠部分OL和第一部分PR1的光源的部分区)或光控制(例如，由光屏蔽构件屏蔽对应于光刻胶层PR的第二部分PR2的光源的部分区)由在第一曝光工艺E1中使用的光源提供的光，以局部地照射在光刻胶层PR的重叠部分OL和第一部分PR1上。也可以在本发明中使用用于防止暴露光刻胶层PR的第二部分 PR2的其它合适的方法。
如图15、图16C、图16D和图17B所示，提供包括第二布局图案P2 的第二掩模M2(步骤S13)。第二掩模M2覆盖光刻胶层PR的重叠部分 OL和第二部分PR2(例如，右部分)。重叠部分OL是依次由第一掩模 M1(在图16A中示出)和第二掩模M2覆盖的区。换句话说，重叠部分OL是第一部分PR1的一部分，并且对应于第一掩膜M1的第一重叠区OL1。除了重叠部分OL之外，光刻胶层PR的第一部分PR1(例如，左部分)未由第二掩模M2覆盖。第二掩模M2包括第二重叠区OL2，并且第二重叠区OL2覆盖并且对应于重叠部分OL。在一些实施例中，第二掩模M2的第二布局图案P2可以包括具有多个第二光透射区域T2的第二光屏蔽图案。之后，实施经由第二掩模M2的第二曝光工艺E2和第二显影工艺(步骤 S14)，以在光刻胶层PR的第二部分PR2中形成多个第二布线开口OP2。当实施第二曝光工艺E2时，第二掩模M2的第二布局图案P2与形成在光刻胶层PR的重叠部分OL中的第一布线开口OP1基本对准。换句话说，当实施第二曝光工艺E2时，第二光透射区域T2与形成在光刻胶层PR的重叠部分OL中的第一布线开口OP1基本对准。通过第二掩模M2的第二布局图案P2的屏蔽，进一步图案化光刻胶层PR，并且可以在光刻胶层PR 的第二部分PR2中形成对应于第二光透射区域T2的第二布线开口OP2。如图16D所示，导电层C由形成在光刻胶层PR中的第一布线开口OP1和第二布线开口OP2部分地暴露。
在一些实施例中，为了防止暴露未由第二掩模M2覆盖的第一部分 PR1，第二掩模M2可以由光屏蔽构件SH2(在图17B中示出)固定，并且光屏蔽构件SH2可以屏蔽未由第二掩模M2覆盖的第一部分PR1。在一些可选实施例中，为了防止暴露未由第二掩模M2覆盖的第一部分PR1，可以提供光屏蔽构件SH2(在图17B中示出)来屏蔽未由第二掩模M2覆盖的第一部分PR1，并且第二掩模M2可以不由光屏蔽构件SH2固定。在另一实施例中，通过适当地控制在第二曝光工艺E2中使用的光源，可以防止未由第二掩模M2覆盖的第一部分PR1的不期望的曝光。例如，可以电控制(例如，仅导通对应于光刻胶层PR的重叠部分OL和第二部分PR2 的光源的部分区)或光控制(例如，由光屏蔽构件屏蔽对应于光刻胶层PR 的第一部分PR1的光源的部分区)由在第二曝光工艺E2中使用的光源提供的光，以局部地照射在光刻胶层PR的重叠部分OL和第二部分PR2上。也可以在本发明中使用用于防止不期望地暴露光刻胶层PR的第一部分 PR1的其它合适方法。
在实施第二曝光工艺E2和第二显影工艺之后，形成在光刻胶层PR中的第一布线开口OP1和第二布线开口OP2在重叠部分OL处连通。如图17B 所示，由于对准偏移(即，重叠偏移)，在第一布线开口OP1和第二布线开口OP2之间可能发生重叠偏移。
如图15、图16E和图17B所示，在形成第一布线开口OP1和第二布线开口OP2之后，通过例如镀工艺在第一布线开口OP1和第二布线开口 OP2中形成多个导电布线。换句话说，导电布线形成(例如，镀)在由第一布线开口OP1和第二布线开口OP2部分地暴露的导电层C上。在一些实施例中，在光刻胶层PR的第一布线开口OP1和第二布线开口OP2中形成均包括第一导电段W1和第二导电段W2的导电布线(S20)。换句话说，导电布线的第一导电段W1形成在第一布线开口OP1中并且导电布线的第二导电段W2形成在第二布线开口OP2中。
如图16F和图17C所示，在光刻胶层PR的第一布线开口OP1和第二布线开口OP2中形成导电布线之后，去除光刻胶层PR的第一部分PR1和第二部分PR2(步骤S30)。在去除第一部分PR1和第二部分PR2之后，通过例如蚀刻工艺去除未由第一导电段W1和第二导电段W2覆盖的导电层C的部分，直至暴露介电层122。在一些可选实施例中，可以省略导电层C的形成和图案化工艺。如图17C所示，在一些实施例中，第一导电段 W1和第二导电段W2在重叠部分OL处连接，并且由于对准偏移(即，重叠偏移)，在第一导电段W1和第二导电段W2之间可能发生重叠偏移。应该注意，可以通过上述重叠偏移容易地判断掩模M1和/或M2的对准偏移。
图18A示意性示出了根据本发明的一些可选实施例的图16A所示的第一掩模M1和图16B所示的重叠部分OL的俯视图；图18B示意性示出了根据本发明的一些可选实施例的图16C所示的第二掩模M2和图16D所示的重叠部分OL的俯视图；并且图18C示意性示出了根据本发明的一些可选实施例的图16E所示的重叠部分OL的俯视图。
参照图18A至图18C，形成在重叠部分OL中的第一布线开口OP1的宽度WD1大于形成在未由第二掩模M2覆盖的第一部分PR1中的第一布线开口OP1的宽度WD2。例如，宽度WD1和宽度WD2的比率(即，WD1/WD2) 可以在从约1.2至约2的范围内。在一些实施例中，形成在第一部分PR1 中的第一布线开口OP1的宽度WD2基本等于形成在第二部分PR2中的第二布线开口OP2的宽度WD3。由于重叠偏移，第一布线开口OP1的宽度 WD1可以增加至WD4。应该注意，可以通过上述重叠偏移容易地判断掩模M1和/或M2的对准偏移。
图19示意性示出了根据本发明的一些实施例的用于制造导电布线的另一工艺流程；图20A示意性示出了根据本发明的一些可选实施例的图 16A所示的第一掩模M1和图16B所示的重叠部分OL的俯视图；图20B 示意性示出了根据本发明的一些可选实施例的图16C所示的第二掩模M2 和图16D所示的重叠部分OL的俯视图；并且图20C示意性示出了根据本发明的一些可选实施例的图16E所示的重叠部分OL的俯视图。
参照图19，在一些实施例中，提供用于制造导电布线的方法，包括：图案化光刻胶层(S40)，在光刻胶层中形成对准标记(S50)，以及在光刻胶层中形成导电布线(S60)。在一些实施例中，可以同时或依次实施在光刻胶中形成对准标记(S50)和在光刻胶层中形成导电布线(S60)的步骤。例如，可以在光刻胶层中形成导电布线之前或之后形成对准标记。可选地，可以通过相同的工艺(例如，镀工艺)形成对准标记和导电布线。在一些可选实施例中，用于制造导电布线的方法还可以包括在光刻胶层中形成导电布线之后去除光刻胶层(步骤S70)。应该注意，步骤S70在本发明中是可选的。
如图19所示，实施用于图案化光刻胶层的多步曝光和显影工艺(即步骤S40)，并且多步曝光和显影工艺可以包括以下步骤(即，步骤S41、S42、 S43和S44)。提供包括第一对准图案和第一布局图案的第一掩模(步骤 S41)。实施经由第一掩模的第一曝光工艺和第一显影工艺，以在光刻胶层的第一部分中形成第一对准开口和多个第一布线开口，其中，光刻胶层的第一部分由第一掩模覆盖(步骤S42)。提供包括第二对准图案和第二布局图案的第二掩模(步骤S43)。实施经由第二掩模的第二曝光工艺和第二显影工艺，以在光刻胶层的第二部分中形成多个第二布线开口，其中，光刻胶层的第一部分和第二部分的重叠部分由第二掩模覆盖，并且当实施第二曝光工艺时，第二掩模的第二对准图案与形成在光刻胶层中的第一对准开口基本对准(步骤S44)。
除了图19中示出的导电布线的制造工艺还包括对准标记的制造(即，步骤S40和S50)之外，用于制造图19中示出的导电布线的方法与图15 中示出的类似。因此，省略关于导电布线的详细描述。
参照图19和图20A，提供了包括第一对准图案AP1和第一布局图案 P1(在图17A或图18A中示出)的第一掩模M1(步骤S41)。例如，在第一掩模M1上，第一对准图案AP1可以连接至第一布局图案P1。第一掩模M1覆盖光刻胶层PR的第一部分PR1(例如，左部分)，但第一掩模 M1不覆盖光刻胶层PR的第二部分PR2(例如，右部分)。第一掩模M1 包括第一重叠区OL1，并且第一对准图案AP1分布在第一重叠区OL1中。在一些实施例中，第一掩模M1的第一对准图案AP1可以包括具有多个第三光透射区域T3的第一光屏蔽图案。之后，实施经由第一掩模M1的第一曝光工艺和第一显影工艺(步骤S42)，以在光刻胶PR的第一部分PR1 中形成第一对准开口OP3和多个第一布线开口OP1(在图17A或图18A中示出)。通过第一掩模M1的第一对准图案AP1和第一布局图案P1的屏蔽，部分地图案化光刻胶层PR，从而使得可以在光刻胶层PR的第一部分PR1 中形成对应于第三光透射区域T3的第一对准开口OP3和对应于第一光透射区域T1的第一布线开口OP1。在一些实施例中，导电层C(在图16E中示出)由形成在光刻胶层PR的第一部分PR1中的第一对准开口OP3和第一布线开口OP1部分地暴露。
参照图19和图20B，提供包括第二对准图案AP2和第二布局图案P2 的第二掩模M2(步骤S43)。例如，在第二掩模M2上，第二对准图案 AP2可以连接至第二布局图案P2。第二掩模M2覆盖光刻胶层PR的重叠部分OL和第二部分PR2(例如，右部分)。重叠部分OL是由第一掩模 M1(在图16A中示出)和第二掩模M2依次覆盖的区。换句话说，重叠部分OL是第一部分PR1的一部分，并且对应于第一掩膜M1的第一重叠区 OL1。除了重叠部分OL之外，光刻胶层PR的第一部分PR1(例如，左部分)未由第二掩模M2覆盖。第二掩模M2包括第二重叠区OL2，并且第二重叠区OL2对应于重叠部分OL。第二对准图案AP2分布在第二重叠区 OL2中。在一些实施例中，第二掩模M2的第二对准图案AP2可以包括具有多个第四光透射区域T4的第四光屏蔽图案。然后，实施经由第二掩模 M2的第二曝光工艺和第二显影工艺(步骤S44)，以在刻胶层PR的重叠部分OL中形成多个第二布线开口OP2。在一些实施例中，在实施第二曝光工艺和第二显影工艺之后，可以在光刻胶层PR中进一步形成与第一对准开口OP3对准的第二对准开口OP4。当实施第二曝光工艺时，第二掩模 M2的第二对准图案AP2与形成在光刻胶层PR的重叠部分OL中的第一对准开口OP3基本对准或对应。换句话说，当实施第二曝光工艺时，第四光透射区域T4与形成在光刻胶层PR的重叠部分OL中的第一对准开口OP3 基本对准。通过第二掩膜M2的第二对准图案AP2的屏蔽，图案化光刻胶层PR，并且可以在光刻胶层PR的重叠部分OL中形成对应于第四光透射区域T4的第二对准开口OP4。如图20B所示，导电层C(在图16E中示出)由形成在光刻胶层PR中的第一对准开口OP3和第二对准开口OP4部分地暴露。
在实施第二曝光工艺和第二显影工艺之后，形成在光刻胶层PR中的第一对准开口OP3和第二对准开口OP4在重叠部分OL处彼此对准。如图20B 所示，第二对准开口OP4可以与第一对准开口OP3间隔开。此外，由于对准偏移(即，重叠偏移)，第一布线开口OP1与第二布线开口OP2之间可能发生重叠偏移。
如图19、图20B和图20C所示，在形成第一对准开口OP3和第二对准开口OP4之后，通过例如镀工艺在第一对准开口OP3和第二对准开口 OP4中形成至少一个对准标记(例如，对准标记AM1和AM2)。换句话说，对准标记AM1和AM2形成(例如，镀)在由第一对准开口OP3和第二对准开口OP4部分地暴露的导电层C上(在图16E中示出)。在一些实施例中，可以通过相同的镀工艺形成导电布线和对准标记AM1和AM2。
如图20C所示，在光刻胶层PR的第一对准开口OP3和第二对准开口 OP4中形成对准标记AM1和AM2(步骤S50)之后，去除光刻胶层PR的第一部分PR1和第二部分PR2。在去除第一部分PR1和第二部分PR2之后，通过例如蚀刻工艺去除未由对准标记AM1和AM2覆盖的导电层C(在图 16E中示出)的部分，直至暴露介电层122。在一些可选实施例中，可以省略导电层C(在图16E中示出)的形成和图案化工艺。
在一些实施例中，对准标记AM1具有对准凹口并且对准标记AM2延伸至对准凹口中。在一些可选实施例中，对准标记AM2具有对准凹口并且对准标记AM1延伸至对准凹口中。对准标记AM1和AM2的形状不限于本发明中。对准标记AM1和AM2在重叠部分OL处彼此间隔开，并且由于对准偏移(即，重叠偏移)，在对准标记AM1和AM2之间可能发生重叠偏移。应该注意，可以通过对准标记AM1和AM2之间的距离容易地判断掩模M1和/或M2的对准偏移。对准标记AM1和AM2之间的距离可以为约5微米。
虽然上述制造工艺描述为在再分布电路结构220中制造再分布导电层 224，但是上述制造工艺也可以用于在再分布电路结构220中制造介电层 222(在图9中示出)。
根据一些实施例，提供了用于制造导电布线的方法，包括：图案化光刻胶层并且在光刻胶层中形成导电布线。图案化光刻胶层包括以下步骤。提供包括第一布局图案的第一掩模。实施经由第一掩模的第一曝光工艺和第一显影工艺，以在光刻胶层的第一部分中形成多个第一布线开口，其中，光刻胶层的第一部分由第一掩模覆盖。提供包括第二布局图案的第二掩模。实施经由第二掩模的第二曝光工艺和第二显影工艺，以在光刻胶层的第二部分中形成多个第二布线开口，其中，光刻胶层的第一部分和第二部分的重叠部分由第二掩模覆盖，第一布线开口和第二布线开口在重叠部分处连通，并且当实施第二曝光工艺时，第二掩模的第二布局图案与形成在光刻胶层中的第一布线开口基本对准。在光刻胶层的第一布线开口和第二布线开口中形成导电布线。
在上述方法中，其中，所述第一掩模的所述第一布局图案包括第一光屏蔽图案，所述第一光屏蔽图案具有对应于所述第一布线开口的多个第一光透射区域，并且所述第二掩模的所述第二布局图案包括第二光屏蔽图案，所述第二光屏蔽图案具有对应于所述第二布线开口的多个第二光透射区域。
在上述方法中，其中，所述第一掩模包括对应于所述重叠部分的第一重叠区，并且所述第二掩模包括对应于所述重叠部分的第二重叠区。
在上述方法中，其中，形成在所述重叠部分中的所述第一布线开口的第一宽度大于形成在未由所述第二掩模覆盖的所述第一部分中的所述第一布线开口的第二宽度。
在上述方法中，其中，所述导电布线包括形成在所述第一布线开口中的多个第一导电段以及形成在所述第二布线开口中的多个第二导电段。
在上述方法中，其中，所述导电布线包括形成在所述第一布线开口中的多个第一导电段以及形成在所述第二布线开口中的多个第二导电段，其中，在所述第一导电段和所述第二导电段之间发生重叠偏移。
根据一些可选实施例，提供了用于制造导电布线的方法，包括：图案化光刻胶层，在光刻胶层中形成对准标记以及在光刻胶层中形成导电布线。图案化光刻胶层包括以下步骤。提供包括第一对准图案和第一布局图案的第一掩模。实施经由第一掩模的第一曝光工艺和第一显影工艺，以在光刻胶层的第一部分中形成第一对准开口和多个第一布线开口，其中，光刻胶层的第一部分由第一掩模覆盖。提供包括第二对准图案和第二布局图案的第二掩模。实施经由第二掩模的第二曝光工艺和第二显影工艺，以在光刻胶层的第二部分中形成多个第二布线开口，其中，光刻胶层的第一部分和第二部分的重叠部分由第二掩模覆盖，并且当实施第二曝光工艺时，第二掩模的第二对准图案与形成在光刻胶层中的第一对准开口基本对准。在第一对准开口中形成对准标记。在第一布线开口和第二布线开口中形成导电布线。
在上述方法中，其中，通过实施所述第二曝光工艺和所述第二显影工艺在所述光刻胶层中进一步形成与所述第一对准开口对准的第二对准开口，并且在所述第一对准开口和所述第二对准开口中形成所述对准标记。
在上述方法中，其中，通过实施所述第二曝光工艺和所述第二显影工艺在所述光刻胶层中进一步形成与所述第一对准开口间隔开的第二对准开口，并且在所述第一对准开口和所述第二对准开口中形成所述对准标记。
在上述方法中，其中，通过实施所述第二曝光工艺和所述第二显影工艺在所述光刻胶层中进一步形成与所述第一对准开口间隔开的第二对准开口，并且在所述第一对准开口和所述第二对准开口中形成所述对准标记，其中，所述第一对准标记具有对准凹口，并且所述第二对准标记延伸至所述对准凹口中。
在上述方法中，其中，通过实施所述第二曝光工艺和所述第二显影工艺在所述光刻胶层中进一步形成与所述第一对准开口间隔开的第二对准开口，并且在所述第一对准开口和所述第二对准开口中形成所述对准标记，其中，所述第二对准标记具有对准凹口，并且所述第一对准标记延伸至所述对准凹口中。
在上述方法中，其中，所述第一掩模的所述第一布局图案包括第一光屏蔽图案，所述第一光屏蔽图案具有对应于所述第一布线开口的多个第一光透射区域，并且所述第二掩模的所述第二布局图案包括第二光屏蔽图案，所述第二光屏蔽图案具有对应于所述第二布线开口的多个第二光透射区域。
在上述方法中，其中，所述第一掩模包括对应于所述重叠部分的第一重叠区，所述第二掩模包括对应于所述重叠部分的第二重叠区，所述第一对准图案分布在所述第一掩模的所述第一重叠区中，所述第二对准图案分布在所述第二掩模的所述第二重叠区中，并且所述第二掩模的所述第二重叠区覆盖形成在所述光刻胶层中的所述第一对准开口。
根据一些可选实施例，提供了包括以下步骤的用于制造芯片封装件的方法。形成绝缘密封件以横向密封至少一个集成电路组件的侧壁。在至少一个集成电路组件和绝缘密封件上形成导电层。在导电层上形成光刻胶层，并且实施多步曝光和显影工艺以图案化光刻胶层。在光刻胶层中形成对准标记。在光刻胶层中形成多个导电布线。实施多步曝光和显影工艺以图案化光刻胶层，并且多步曝光和显影工艺包括以下步骤。提供包括第一对准图案和第一布局图案的第一掩模。实施经由第一掩模的第一步曝光工艺和第一显影工艺，以在光刻胶层的第一部分中形成第一对准开口和多个第一布线开口，其中，光刻胶层的第一部分由第一掩模覆盖。提供包括第二对准图案和第二布局图案的第二掩模。实施经由第二掩模的第二步曝光工艺和第二显影工艺，以在光刻胶层的第二部分中形成多个第二布线开口，其中，光刻胶层的第一部分和第二部分的一部分由第二掩模覆盖，并且当实施第二步曝光工艺时，第二掩模的第二对准图案与形成在光刻胶层中的第一对准开口基本对准。在第一对准开口中形成对准标记。在第一布线开口和第二布线开口中形成导电布线，其中，导电布线电连接至至少一个集成电路组件。
在上述方法中，其中，通过实施所述第二步曝光工艺和所述第二显影工艺在所述光刻胶层中进一步形成与所述第一对准开口对准的第二对准开口，并且在所述第一对准开口和所述第二对准开口中形成所述对准标记。
在上述方法中，其中，通过实施所述第二步曝光工艺和所述第二显影工艺在所述光刻胶层中进一步形成与所述第一对准开口间隔开的第二对准开口，并且在所述第一对准开口和所述第二对准开口中形成所述对准标记。
在上述方法中，其中，通过实施所述第二步曝光工艺和所述第二显影工艺在所述光刻胶层中进一步形成与所述第一对准开口间隔开的第二对准开口，并且在所述第一对准开口和所述第二对准开口中形成所述对准标记，其中，所述第一对准标记具有对准凹口，并且所述第二对准标记延伸至所述对准凹口中。
在上述方法中，其中，通过实施所述第二步曝光工艺和所述第二显影工艺在所述光刻胶层中进一步形成与所述第一对准开口间隔开的第二对准开口，并且在所述第一对准开口和所述第二对准开口中形成所述对准标记，其中，所述第二对准标记具有对准凹口，并且所述第一对准标记延伸至所述对准凹口中。
在上述方法中，其中，所述第一掩模的所述第一布局图案包括第一光屏蔽图案，所述第一光屏蔽图案具有对应于所述第一布线开口的多个第一光透射区域，并且所述第二掩模的所述第二布局图案包括第二光屏蔽图案，所述第二光屏蔽图案具有对应于所述第二布线开口的多个第二光透射区域。
在上述方法中，其中，所述第一掩模包括对应于所述重叠部分的第一重叠区，并且所述第二掩模包括对应于所述重叠部分的第二重叠区，所述第一对准图案分布在所述第一掩模的所述第一重叠区中，所述第二对准图案分布在所述第二掩模的所述第二重叠区中，并且所述第二掩模的所述第二重叠区覆盖形成在所述光刻胶层中的所述第一对准开口。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (20)

1.一种用于制造导电布线的方法，包括：
图案化光刻胶层，包括：
提供包括第一对准图案和第一布局图案的第一掩模；
实施经由所述第一掩模的第一曝光工艺和第一显影工艺，以在所述光刻胶层的第一部分中形成第一对准开口和多个第一布线开口，并且所述光刻胶层的第一部分由所述第一掩模覆盖；
提供包括第二对准图案和第二布局图案的第二掩模；
实施经由所述第二掩模的第二曝光工艺和第二显影工艺，以在所述光刻胶层的第二部分中形成多个第二布线开口，所述光刻胶层的第一部分和第二部分的重叠部分由所述第二掩模覆盖，所述第一布线开口和所述第二布线开口在所述重叠部分处连通，并且当实施所述第二曝光工艺时，所述第二掩模的所述第二布局图案与形成在所述光刻胶层中的所述第一布线开口对准，并且所述第二掩模的所述第二对准图案与形成在所述光刻胶层中的所述第一对准开口对准；
在所述第一对准开口中形成对准标记；以及
在所述第一布线开口和所述第二布线开口中形成导电布线，
其中，形成在所述重叠部分中的所述第一布线开口的第一宽度大于形成在未由所述第二掩模覆盖的所述第一部分中的所述第一布线开口的第二宽度。
2.根据权利要求1所述的方法，其中，所述第一掩模的所述第一布局图案包括第一光屏蔽图案，所述第一光屏蔽图案具有对应于所述第一布线开口的多个第一光透射区域，并且所述第二掩模的所述第二布局图案包括第二光屏蔽图案，所述第二光屏蔽图案具有对应于所述第二布线开口的多个第二光透射区域。
3.根据权利要求1所述的方法，其中，所述第一掩模包括对应于所述重叠部分的第一重叠区，并且所述第二掩模包括对应于所述重叠部分的第二重叠区。
4.根据权利要求1所述的方法，其中，通过实施所述第二曝光工艺和所述第二显影工艺在所述光刻胶层中进一步形成与所述第一对准开口对准的第二对准开口，并且在所述第一对准开口和所述第二对准开口中形成所述对准标记。
5.根据权利要求1所述的方法，其中，所述导电布线包括形成在所述第一布线开口中的多个第一导电段以及形成在所述第二布线开口中的多个第二导电段。
6.根据权利要求5所述的方法，其中，在所述第一导电段和所述第二导电段之间发生重叠偏移。
7.一种用于制造导电布线的方法，包括：
图案化光刻胶层，包括：
提供包括第一对准图案和第一布局图案的第一掩模；
实施经由所述第一掩模的第一曝光工艺和第一显影工艺，以在所述光刻胶层的第一部分中形成第一对准开口和多个第一布线开口，并且所述光刻胶层的第一部分由所述第一掩模覆盖；
提供包括第二对准图案和第二布局图案的第二掩模；
实施经由所述第二掩模的第二曝光工艺和第二显影工艺，以在所述光刻胶层的第二部分中形成多个第二布线开口，所述光刻胶层的第一部分和第二部分的重叠部分由所述第二掩模覆盖，并且当实施所述第二曝光工艺时，所述第二掩模的所述第二对准图案与形成在所述光刻胶层中的所述第一对准开口对准；
在所述第一对准开口中形成对准标记；以及
在所述第一布线开口和所述第二布线开口中形成导电布线。
8.根据权利要求7所述的方法，其中，通过实施所述第二曝光工艺和所述第二显影工艺在所述光刻胶层中进一步形成与所述第一对准开口对准的第二对准开口，并且在所述第一对准开口和所述第二对准开口中形成所述对准标记。
9.根据权利要求7所述的方法，其中，通过实施所述第二曝光工艺和所述第二显影工艺在所述光刻胶层中进一步形成与所述第一对准开口间隔开的第二对准开口，并且在所述第一对准开口和所述第二对准开口中形成所述对准标记。
10.根据权利要求9所述的方法，其中，所述第一对准标记具有对准凹口，并且所述第二对准标记延伸至所述对准凹口中。
11.根据权利要求9所述的方法，其中，所述第二对准标记具有对准凹口，并且所述第一对准标记延伸至所述对准凹口中。
12.根据权利要求7所述的方法，其中，所述第一掩模的所述第一布局图案包括第一光屏蔽图案，所述第一光屏蔽图案具有对应于所述第一布线开口的多个第一光透射区域，并且所述第二掩模的所述第二布局图案包括第二光屏蔽图案，所述第二光屏蔽图案具有对应于所述第二布线开口的多个第二光透射区域。
13.根据权利要求7所述的方法，其中，所述第一掩模包括对应于所述重叠部分的第一重叠区，所述第二掩模包括对应于所述重叠部分的第二重叠区，所述第一对准图案分布在所述第一掩模的所述第一重叠区中，所述第二对准图案分布在所述第二掩模的所述第二重叠区中，并且所述第二掩模的所述第二重叠区覆盖形成在所述光刻胶层中的所述第一对准开口。
14.一种用于制造芯片封装件的方法，包括：
形成绝缘密封件以横向密封至少一个集成电路组件的侧壁；
在所述至少一个集成电路组件和所述绝缘密封件上形成导电层；
在所述导电层上形成光刻胶层，并且实施多步曝光和显影工艺以图案化所述光刻胶层，其中，实施所述多步曝光和显影工艺以图案化所述光刻胶层包括：
提供包括第一对准图案和第一布局图案的第一掩模；
实施经由所述第一掩模的第一步曝光工艺和第一显影工艺，以在所述光刻胶层的第一部分中形成第一对准开口和多个第一布线开口，并且所述光刻胶层的第一部分由所述第一掩模覆盖；
提供包括第二对准图案和第二布局图案的第二掩模；
实施经由所述第二掩模的第二步曝光工艺和第二显影工艺，以在所述光刻胶层的第二部分中形成多个第二布线开口，所述光刻胶层的第一部分和第二部分的一部分由所述第二掩模覆盖，并且当实施所述第二步曝光工艺时，所述第二掩模的所述第二对准图案与形成在所述光刻胶层中的所述第一对准开口对准；
在所述第一对准开口中形成对准标记；
在所述第一布线开口和所述第二布线开口中形成多个导电布线，其中，所述导电布线电连接至所述至少一个集成电路组件。
15.根据权利要求14所述的方法，其中，通过实施所述第二步曝光工艺和所述第二显影工艺在所述光刻胶层中进一步形成与所述第一对准开口对准的第二对准开口，并且在所述第一对准开口和所述第二对准开口中形成所述对准标记。
16.根据权利要求14所述的方法，其中，通过实施所述第二步曝光工艺和所述第二显影工艺在所述光刻胶层中进一步形成与所述第一对准开口间隔开的第二对准开口，并且在所述第一对准开口和所述第二对准开口中形成所述对准标记。
17.根据权利要求16所述的方法，其中，所述第一对准标记具有对准凹口，并且所述第二对准标记延伸至所述对准凹口中。
18.根据权利要求16所述的方法，其中，所述第二对准标记具有对准凹口，并且所述第一对准标记延伸至所述对准凹口中。
19.根据权利要求14所述的方法，其中，所述第一掩模的所述第一布局图案包括第一光屏蔽图案，所述第一光屏蔽图案具有对应于所述第一布线开口的多个第一光透射区域，并且所述第二掩模的所述第二布局图案包括第二光屏蔽图案，所述第二光屏蔽图案具有对应于所述第二布线开口的多个第二光透射区域。
20.根据权利要求14所述的方法，其中，所述第一掩模包括对应于所述光刻胶层的第一部分和第二部分的重叠部分的第一重叠区，并且所述第二掩模包括对应于所述重叠部分的第二重叠区，所述第一对准图案分布在所述第一掩模的所述第一重叠区中，所述第二对准图案分布在所述第二掩模的所述第二重叠区中，并且所述第二掩模的所述第二重叠区覆盖形成在所述光刻胶层中的所述第一对准开口。
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