CN109412590A - A kind of high speed signal sampling system - Google Patents
A kind of high speed signal sampling system Download PDFInfo
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- CN109412590A CN109412590A CN201811544451.6A CN201811544451A CN109412590A CN 109412590 A CN109412590 A CN 109412590A CN 201811544451 A CN201811544451 A CN 201811544451A CN 109412590 A CN109412590 A CN 109412590A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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Abstract
The invention discloses a kind of high speed signal sampling systems, including clock generation module, frequency unit, multiplier unit, ADC module and FPGA module, the clock signal output terminal of the clock generation module respectively with frequency unit, multiplier unit is connected, the change over clock signal output end of frequency unit, the data clock signal output end of multiplier unit is connected with the input end of analog signal of ADC module, the digital signal output end of ADC module is connected with FPGA module, the FPGA module includes two paths of data channel, every circuit-switched data channel is by sequentially connected data receipt unit, FIFO storage unit and serioparallel exchange unit composition, data clock signal output end is connected with the data receipt unit in every circuit-switched data channel respectively, change over clock signal output end and FIFO storage unit and serioparallel exchange Unit is connected.The present invention is extended to 16 channels by binary channels sample mode, finally reaches the acquisition system of 64 channel 18bit 5MSPS, has the sampling system compared with high sampling rate, high contrast and high sampling precision.
Description
Technical field
The present invention relates to technical field of signal sampling, more particularly to a kind of high speed signal sampling system.
Background technique
With the rapid development of Terahertz Technology, terahertz imaging is had been more and more widely used, and is imaged relative to X,
It is small that terahertz imaging has a transmission power, the advantages of to no damage to human body, simultaneously because Terahertz also has the characteristics of high bandwidth,
The advantages that maintaining high-resolution, the Precise imaging of X imaging, therefore obtained in the field of safety check such as airport, high-speed rail and public security system
To being more and more widely used.
More stringent requirements are proposed to acquisition system for terahertz imaging: because of big bandwidth, it is desirable that acquisition system has higher
Sample rate；Again because of the Larger Dynamic range of imaging requirements, high contrast, therefore it is required that acquisition system has very high sampling precision
(sampling precision 18bit ENOB >=16bit).
Core component of the high speed acquisition system as systems such as communication, radar and imagings, is always to study both at home and abroad
Hot spot and emphasis, before for the acquisition system of communication and radar application, sampling precision concentrates on 14 to 16bit substantially, sampling
80 ~ 200MSPS of rate；The medical imaging systems such as color ultrasound, ADC sampling precision is substantially in 12bit, sampling rate > 10MSPS；Oscillography
The measuring devices such as device need high sampling rate (for bandwidth in the oscillograph of 500M, usual sampling rate is more than 2.5GSPS), but
It is that sampling precision is not high, usually only needs 8bit.
High precision collecting 18 ~ 24bit of system, usually in the fields such as commercial measurement, such as platform scale, flowmeter, since it is desired that
Very big dynamic range, it usually needs the resolving accuracy of 24bit, but since the signal frequency of acquisition is very low, usually kHz with
Under, so the sample rate of ADC is not high (usually in several ksps to tens ksps).
In summary, it can be seen that, for sampling precision 18bit simultaneously sampling rate also higher (5MSPS) acquisition
System, since application field is less, the research of progress is simultaneously few.
It is inputted for 5V analog signal, to reach EN0B > 16bit, then mean that system noise is less than 76uV, adopt at a high speed
Collecting system processing unit subpackage will keep so low noise, to system design, power supply processing etc. containing high-speed figures devices such as FPGA
It is proposed very high request, while when assessing the system, it is desirable to provide the very signal source of high s/n ratio.
With the occasions such as airport, high-speed rail, subway safe examination system to green, Low emissivity, fanout free region, do not contact the features such as
It is required that more more and more urgent, terahertz imaging system is subsequent to widely apply (subway in Shenzhen, which has used, at present changes system),
Public security simultaneously, People's Armed Police department are also very huge to the demand of progress weapon and contraband detecting (every sky) is not contacted.
Summary of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of high speed signal sampling systems, pass through bilateral
Road sample mode is extended to 16 channels, finally reaches the acquisition system of 64 channel 18bit 5MSPS, make the sampling system have compared with
High sampling rate, high contrast and high sampling precision.
The purpose of the present invention is achieved through the following technical solutions: a kind of high speed signal sampling system, including clock
Generation module, frequency unit, multiplier unit, ADC module and FPGA module, the clock signal output of the clock generation module
End is connected with frequency unit, multiplier unit respectively, the data clock of the change over clock signal output end of frequency unit, multiplier unit
Signal output end is connected with the input end of analog signal of ADC module, digital signal output end and the FPGA module phase of ADC module
Even, the FPGA module includes two paths of data channel, and every circuit-switched data channel is stored by sequentially connected data receipt unit, FIFO
Unit and serioparallel exchange unit composition, the data clock signal output end data receipt unit phase with every circuit-switched data channel respectively
Even, change over clock signal output end is connected with FIFO storage unit and serioparallel exchange unit respectively.
The clock generation module is the constant-temperature crystal oscillator of 10MHz.
The change over clock signal is 5MHz, data clock signal 200MHz.
The multiplier unit is phaselocked loop ADF4350 frequency multiplier.
The frequency unit is frequency divider SY89871.
The ADC module is AD7960 analog-digital converter.
The beneficial effects of the present invention are:
1) intend first realizing double channels acquisition system, be then extended to 16 channels again, finally reach 64 channel 18bit 5MSPS's
Acquisition system, sampling system have compared with high sampling rate, high contrast and high sampling precision.
2) this system selection should share a pair of of data clock from clock module and come while sampling two ADC from clock module
The data in channel directly sample output data by CLK clock, and the mode is not because need to use DCO clock, in multichannel ADC
The global clock resource of FPGA can be saved when system, largely convenient for verifying to subsequent 64 channel collection plate.
Detailed description of the invention
Fig. 1 is design scheme schematic diagram of the present invention；
Fig. 2 is double channel data acquisition system block diagram of the present invention；
Fig. 3 is echo mode figure of the present invention；
Fig. 4 is of the invention from clock module figure.
Specific embodiment
Below in conjunction with embodiment, technical solution of the present invention is clearly and completely described, it is clear that described
Embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field
Technical staff's every other embodiment obtained under the premise of not making the creative labor belongs to what the present invention protected
Range.
Refering to fig. 1-4, the present invention provides a kind of technical solution: a kind of high speed signal sampling system, including clock generates mould
Block, frequency unit, multiplier unit, ADC module and FPGA module, the clock signal output terminal difference of the clock generation module
It is connected with frequency unit, multiplier unit, clock generation module is transmitted separately to frequency unit, frequency multiplication list after generating clock signal
Member, the change over clock signal after being divided and the data clock signal after frequency multiplication.
The clock generation module is the constant-temperature crystal oscillator of 10MHz, then clock generation module generates the clock letter of 10MHz
Number, the clock generation module is constant-temperature crystal oscillator, for clock signal requirement needed for meeting subsequent ADC module, the frequency dividing
The change over clock signal that unit is divided as 5MHz, the frequency unit are frequency divider SY89871；The multiplier unit will
Its frequency multiplication is the data clock signal of 200MHz, and the multiplier unit is phaselocked loop ADF4350 frequency multiplier.
The change over clock signal output end of the frequency unit, multiplier unit data clock signal output end and ADC
The input end of analog signal of module is connected, and the digital signal output end of ADC module is connected with FPGA module, and change over clock is simulated
Signal and data clock analog signal, which are transmitted to ADC module and are converted into digital signal, to be exported to FPGA module, the ADC mould
Block is AD7960 analog-digital converter.
The ADC module is based on data clock and carries out data acquisition, and carries out analog-to-digital conversion based on change over clock and adopted
Sample data, specifically, the ADC module is AD7960 analog-digital converter, sample rate 5MSPS, sampling resolution is 18, most
Big power consumption is 64.5mW, and AD7960 is exported using serial ports, and the frequency of required reference clock is 200MHz(CLK), change over clock
Frequency is 5MHz(CNV).
There are two types of modes for AD7960 data-interface: (1) echo mode (see figure 3)；(2) from clock module (see figure 4)；Wherein
Echo mode AD7960 can generate a pair of of DCO clock to FPGA, FPGA can under DCO timeticks to the data of AD7960 into
Row sampling, it is ensured that settling time and retention time, the mode timing sequence process are simple.
This system is selected from clock module, and a pair of of data clock should be shared from clock module and comes while sampling two ADC to lead to
The data in road directly sample output data by CLK clock, and the mode is not because need to use DCO clock, in multichannel ADC system
The global clock resource of FPGA can be saved when system, largely convenient for verifying to subsequent 64 channel collection plate.
The FPGA module includes two paths of data channel, every circuit-switched data channel by sequentially connected data receipt unit,
FIFO storage unit and serioparallel exchange unit composition, the data clock signal output end data receiver with every circuit-switched data channel respectively
Unit is connected, and change over clock signal output end is connected with FIFO storage unit and serioparallel exchange unit respectively.
In the corresponding data receipt unit of FPGA module, sets each frame sampling data and include 20 bits, and highest
Value in two bits of bit is preset value, and the value in the bit of remaining bit is actual sample value；
The data receipt unit receives the sampled data of data clock simultaneously, and judge digital signal from ADC module with
Whether the value in the first two bit of the sampled data of the data clock is preset value, if the value in the first two bit is not default
Value, then receive sampled data after carrying out the delay of predetermined time again, until the value in the first two bit is preset value, can be used
The K7 of XILINX is set as under 200MHz data clock by the delay chain of FPGA module, and by the adjustable delay time
78ps.If preset value then normally receives data, it is every received a frame sampling data after, by sampling data transmitting to FPGA
The corresponding FIFO storage unit of module, FIFO storage unit is based on change over clock signal and stores the sampled data, in FPGA module
Corresponding serioparallel exchange unit carries out serioparallel exchange to the sampled data that FIFO storage unit stores based on change over clock, realizes double
The signal sampling in channel.
The present invention is quasi- first to realize double channels acquisition system, is then extended to 16 channels again, finally reaches 64 channel 18bit
The acquisition system of 5MSPS, sampling system have compared with high sampling rate, high contrast and high sampling precision, specifically, selecting
ADR4550BRZ provides stable 5V analog signal input, then carries out completely the same dual-channel transmission, each channel Jun Bao
Containing two AD8032ARZ, two ADA4899-1YCPZ and AD7960BCRZ, the signal in each channel is by FPGA
Module receive, and so on so realize 64 channels sampling, make sampling system have compared with high sampling rate, high contrast and height
Sampling precision.
The key technical indexes of the invention are as follows:
Algorithm is supported: can be averaged to same channel N point, N is arranged by software；
Simulation input: 2 simulation inputs (Differential Input), 0 ~ 5V of range；
Sample number of significant digit: 16bit effectively acquires position；
Sample frequency: every channel parallel sample frequency 2MHz, highest are supported to 5MHz；
Synchronous to require: internal synchronization, interchannel acquisition delay are less than 10ns；
Earthing mode: it supports on the spot and Polder Model, support software setting, field mode needs independent grounding line；
External TTL triggering: according to external input TTL signal level variation triggering sampling and stopping sampling, (low level 0V stopping is adopted
Sample high level 5V triggering sampling), it is realized by input/output interface；
Software triggering: triggering sampling is called by software interface and stops sampling；
The output of internal TTL signal: software triggering starts/at the end of synchronism output TTL signal (low level 0V stops the high electricity of sampling
Flat triggering sampling 5V), it is realized by input/output interface.
The above is only a preferred embodiment of the present invention, it should be understood that the present invention is not limited to described herein
Form should not be regarded as an exclusion of other examples, and can be used for other combinations, modifications, and environments, and can be at this
In the text contemplated scope, modifications can be made through the above teachings or related fields of technology or knowledge.And those skilled in the art institute into
Capable modifications and changes do not depart from the spirit and scope of the present invention, then all should be in the protection scope of appended claims of the present invention
It is interior.
Claims (6)
1. a kind of high speed signal sampling system, it is characterised in that: including clock generation module, frequency unit, multiplier unit, ADC
The clock signal output terminal of module and FPGA module, the clock generation module is connected with frequency unit, multiplier unit respectively,
The change over clock signal output end of frequency unit, the data clock signal output end of multiplier unit are believed with the simulation of ADC module
Number input terminal is connected, and the digital signal output end of ADC module is connected with FPGA module, and the FPGA module includes that two paths of data is led to
Road, every circuit-switched data channel are made of sequentially connected data receipt unit, FIFO storage unit and serioparallel exchange unit, when data
Clock signal output end is connected with the data receipt unit in every circuit-switched data channel respectively, change over clock signal output end respectively with FIFO
Storage unit is connected with serioparallel exchange unit.
2. a kind of high speed signal sampling system according to claim 1, it is characterised in that: the clock generation module is
The constant-temperature crystal oscillator of 10MHz.
3. a kind of high speed signal sampling system according to claim 1, it is characterised in that: the change over clock signal is
5MHz, data clock signal 200MHz.
4. a kind of high speed signal sampling system according to claim 1, it is characterised in that: the multiplier unit is locking phase
Ring ADF4350 frequency multiplier.
5. a kind of high speed signal sampling system according to claim 1, it is characterised in that: the frequency unit is frequency dividing
Device SY89871.
6. a kind of high speed signal sampling system according to claim 1, it is characterised in that: the ADC module is
AD7960 analog-digital converter.
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| CN201811544451.6A CN109412590A (en) | 2018-12-17 | 2018-12-17 | A kind of high speed signal sampling system |
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| CN201811544451.6A CN109412590A (en) | 2018-12-17 | 2018-12-17 | A kind of high speed signal sampling system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113949466A (en) * | 2021-11-19 | 2022-01-18 | 上海创远仪器技术股份有限公司 | System, method, device, processor and storage medium for realizing automatic ultra-wideband wireless signal acquisition and transmission processing |
| CN115102549A (en) * | 2020-03-23 | 2022-09-23 | 成都华芯天微科技有限公司 | Data channel establishing method for ADC (analog to digital converter) acquisition system |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108919707A (en) * | 2018-06-29 | 2018-11-30 | 王争 | A kind of 64 channel High Precise Data Acquisition Systems |
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- 2018-12-17 CN CN201811544451.6A patent/CN109412590A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108919707A (en) * | 2018-06-29 | 2018-11-30 | 王争 | A kind of 64 channel High Precise Data Acquisition Systems |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115102549A (en) * | 2020-03-23 | 2022-09-23 | 成都华芯天微科技有限公司 | Data channel establishing method for ADC (analog to digital converter) acquisition system |
| CN115102549B (en) * | 2020-03-23 | 2023-03-10 | 成都华芯天微科技有限公司 | Data channel establishing method for ADC (analog to digital converter) acquisition system |
| CN113949466A (en) * | 2021-11-19 | 2022-01-18 | 上海创远仪器技术股份有限公司 | System, method, device, processor and storage medium for realizing automatic ultra-wideband wireless signal acquisition and transmission processing |
| CN113949466B (en) * | 2021-11-19 | 2024-05-17 | 上海创远仪器技术股份有限公司 | System for realizing automatic ultra-wideband wireless signal acquisition, transmission and processing |
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