CN101252398B - Spread-spectrum signal source with Doppler analogue function - Google Patents

Abstract

The invention relates to a spread spectrum signal source provided with the Doppler simulation function, including a Doppler dynamic simulation part, a data framing format arrangement and an IF signal modulated transmission part; the Doppler dynamic simulation part realizes the dynamic simulation of the motion state of a processor, including that the carrier NCO control word is figured out according to the control panel or the control of the host computer and is transmitted to the emission channel subsystem to control the carrier used for generating the Doppler frequency; meanwhile, the simulation process of the code clock Doppler frequency is processed synchronously. The data framing format arrangement part mainly realizes the generation and framing of the data with transmission information in the processor. The IF signal modulated transmission part realizes the code spread spectrum modulation of the information data and the PN code data; meanwhile, the information data and the PN code are transmitted together with the generated digital carrier; on the exterior of the software, the peripheral modulator is used to realize the carrier modulation and transmit the whole IF signal through the RF front-end.

Description

Spread-spectrum signal source with Doppler analogue function

(1) technical field:

A kind of spread-spectrum signal source with Doppler analogue function of the present invention belongs to the space flight measurement and control communication technical field.

(2) background technology:

Core based on the space flight measurement and control communication system of spread spectrum is that digital communication technologies such as pseudo-code spread spectrum, pseudo-random code ranging, code division multiple access are incorporated in the TT&C system; Realization to remote measurement, the remote control of satellite, find range, test the speed, functions such as tracking, angle measurement, number biographies; Accomplish TT&C task, lean on code division multiple access to realize the multiple target telemetry communication.

The radio distance-measuring principle is to measure the propagation delay time of radio wave.At first emitting radio wave is measured inverse signal then with respect to the time delay τ that transmits, thereby calculates target range R.The relation of R and τ is: R=τ c/2, wherein, c is radio propagation speed (light velocity).Therefore, range finding is exactly to survey propagation delay τ.

Pseudo-random code ranging is that reproducible and its auto-correlation function is these characteristics of impulse function according to pseudo-code, measures radio wave propagation time delay τ's.Receiver produces and the range finding pseudo-code that transmits identical at this machine; Constantly change its phase place; Carry out correlation computations with the reception signal that has noise, when sharp-pointed relevant peaks appearred in correlation function, local pseudo-code just can substitute fully and receive signal; Measuring the time delay between the transmitting-receiving range finding pseudo-code this moment, is exactly radio wave propagation time delay τ.

Relevant key technology is following:

Distance measurement mode (method): the clock life period and the difference on the frequency of sending and receiving end, must at first obtain with (or) eliminate this error, just can obtain correct radio wave propagation time delay τ.Through taking to select different time difference/frequency difference processing methods, can obtain different distance measurement modes (method), and demonstrate pluses and minuses separately based on spread spectrum.

The mensuration of the synchronous and radio wave propagation time delay of spread-spectrum signal: receiver need produce and identical local carrier and the local pseudo-code of transmitting at this machine, and further from the phase value of this locality reproduction pseudo-code, extracts time delay information.Can utilize methods such as FLL, section's Stas ring, delay lock loop to realize the synchronous of spread-spectrum signal.Sample constantly in the local epoch code phase values of local reproduction pseudo-code of receiver can obtain this machine and receive signal constantly with respect to the pseudo-time delay value to the square signal x time, obtains real propagation delay after further handling.

Range accuracy error and test thereof: measuring equipment clock correction and variation thereof, measuring equipment variable in distance, intrinsic radio wave propagation and signal processing time delay, antenna phase center error and the factors such as receiver thermal noise and dynamic stress of measuring equipment bring error all can for final range measurement accuracy; In these error components; Preceding 4 belong to systematic error, and back one belongs to random error.Because error component is more, be difficult to analyze one by one, the assessment of the overall error of bringing to range measurement for various error components can utilize corresponding method and calibration equipment to test, with the indexs such as range accuracy of definite this measuring equipment.

Like Fig. 1 and shown in Figure 2; When examining and determine the range accuracy error of a certain system; Traditional method is that measuring equipment A and measuring equipment B are loaded on the actual carrier; Perhaps the two is linked to each other through channel simulator, be used for simulating two situation such as signal to noise ratios variation, initial distance difference and relative motion between measuring equipment; And the analogue value of actual vector or channel simulator and the range finding result of device A linked data recording equipment, the result carries out statistical disposition to each time range finding, so that indexs such as the dynamic property of system and range accuracy are examined and determine.

The shortcoming of the method for this traditional calibrating range accuracy error is:

(1) each equipment is separate, system complex, and integrated level is low.

(2) calibration accuracy of range accuracy error is subject to the simulation precision to the actual vector motion conditions, the perhaps signal time delay simulation precision of channel simulator, and the error calibration accuracy is generally not high.

Based on above characteristics, this patent has proposed to utilize the spread-spectrum signal source with Doppler analogue function to simulate the technological solution that various motion states detect receiver each item performance.

(3) summary of the invention:

The object of the present invention is to provide a kind of spread-spectrum signal source, to solve deficiency of the prior art with Doppler analogue function.

A kind of spread-spectrum signal source of the present invention with Doppler analogue function; Be the radiating portion that is called " intermediate-freuqncy signal processor " in the patent of invention of " bidirectional ranging and time ratio are to processing terminal " as applicant's separate case applicant's name, be responsible for the generation of intermediate-freuqncy signal processor internal data, formatting, Doppler's dynamic characteristic is simulated and the realization of functions such as data-modulated emission.

A kind of spread-spectrum signal source with Doppler analogue function of the present invention mainly can be divided into Doppler's dynamic analog, the layout of data set frame format and three parts of intermediate-freuqncy signal modulate emission.

Wherein, The main dynamic analog of realizing the processor motion state of Doppler's dynamic analog part: through the design of sign indicating number NCO; Accomplishing range finding pseudo-code dynamic characteristic realizes; Make the pseudo-code of generation meet separately sequential and correlation properties, and realize that two kinds of pseudo-code phase are corresponding one by one, so that correctly modulate navigation message; Through the design of carrier wave NCO, just accomplishing, the generation and the dynamic characteristic of (surplus) string digital carrier realize.Data set frame format layout part is main to realize that band sends the generation and the framing of information data in the processor; Have in mainly comprising: frame synchronization; Subframe numbers; The useful information that receiver sections such as this locality information lock in time and this machine data need, the timing Design of counter requires navigation message data phase and pseudo-code chip phase to be mapped according to the base band band spectrum modulation through epoch.The intermediate-freuqncy signal modulate emission is partly accomplished the sign indicating number band spectrum modulation of information data and pseudo-code data, sends simultaneously with the digital carrier that generates simultaneously, and software is outside accomplishes carrier modulation through peripheral modulator, and complete intermediate-freuqncy signal is sent through radio-frequency front-end.

1, Doppler's dynamic analog part

The Doppler simulation part calculates carrier wave NCO control word, and exports the transmission channel subsystem to according to the control of control panel or host computer, and control produces the carrier wave of Doppler frequency; The simulation process of synchronous carrying out yard clock Doppler frequency: calculate spread-spectrum pseudo code NCO control word, produce the bit rate clock that comprises yard Doppler, produce the pseudo-code that is used for the data band spectrum modulation through the mode of looking into code table.

(1) control produces the principle of the carrier wave of Doppler frequency

Adopt DDS technical pattern to generate the dynamic digital carrier wave in the present invention's design, the carrier wave NCO control word that receives is carried out the NCO accumulating operation, after through amplitude quantizing and phase quantization, through phase-magnitude look-up table output digital carrier.Have multidate informations such as speed and acceleration for the digital carrier that makes generation, adopt carrier wave NCO mode to carry out chip count and complete cycle count.The frequency word of carrier wave NCO is set up and is resolved through the carrier doppler simulation model and obtains.Carrier doppler simulation specifically is designed to (even to add (subtracting) fast rectilinear motion be example with terminal A):

If the signal of terminal A emission is:

s ₀(t)＝Acos(2π×140×10 ⁶×t-φ ₀)

In the formula, φ ₀Be initial phase (radian).

If terminal A is v with respect to the radial velocity of terminal B, terminal A is B flight towards the terminal.Both radial distances are R when t=0, and then constantly the electromagnetic wave time that A propagates into terminal B antenna from the terminal is at t:

$\mathrm{\τ}=\frac{R-v\×t}{c}$

In the formula, c is the light velocity.

What at this moment, terminal B received is to have postponed the satellite-signal of τ after second

$s_1\left(t\right)=s_0(t-\mathrm{\τ})$

$=A\cos [2\mathrm{\π}\×140\×{10}^6\×(t-\mathrm{\τ})-{\mathrm{\φ}}_0]$

$=A\cos [2\mathrm{\π}\×140\×{10}^6\×(t-\frac{R-v\×t}{c})-{\mathrm{\φ}}_0]$

$=A\cos [2\mathrm{\π}\×140\×{10}^6\×(t+\frac{v\×t}{c})-2\mathrm{\π}\×140\×{10}^6\×\frac{R}{c}-{\mathrm{\φ}}_0]$

Terminal B is to s ₁(t) carry out down-conversion, obtain the intermediate-freuqncy signal that nominal frequency is 25MHz

$s_2\left(t\right)=s_1\left(t\right)\·\cos (2\mathrm{\π}\×115\×{10}^6\×t)$

$=A\cos [2\mathrm{\π}\×140\×{10}^6\×(t+\frac{v\×t}{c})-2\mathrm{\π}\×140\×{10}^6\×\frac{R}{c}-{\mathrm{\φ}}_0]\·\cos (2\mathrm{\π}\×115\×{10}^6\×t)$

$=A\cos [2\mathrm{\π}\×25\×{10}^6\×t+2\mathrm{\π}\×140\×{10}^6\×\frac{v\×t}{c}-2\mathrm{\π}\×140\×{10}^6\×\frac{R}{c}-{\mathrm{\φ}}_0]$

With the frequency of 62MHz to s ₂(t) sample, the output nominal frequency is the intermediate-freuqncy signal of 25MHz

$s_3\left(t\right)=s_2\left(t\right)\·\cos (2\mathrm{\π}\×62\×{10}^6\×t)$

$=A\cos [-2\mathrm{\π}\×25\×{10}^6\×t+2\mathrm{\π}\×140\×{10}^6\×\frac{v\×t}{c}-2\mathrm{\π}\×140\×{10}^6\×\frac{R}{c}-{\mathrm{\φ}}_0]$

$=A\cos [2\mathrm{\π}\×25\×{10}^6\×t-2\mathrm{\π}\×140\×{10}^6\×\frac{v\×t}{c}+2\mathrm{\π}\×140\×{10}^6\×\frac{R}{c}+{\mathrm{\φ}}_0]$

To s ₃(t) after the discretization, t=n * T _sSample constantly is output as:

$s_3\left(n\right)=A\cos [2\mathrm{\π}\×25\×{10}^6\×n\×T_s-2\mathrm{\π}\×140\×{10}^6\×\frac{v\×n\×T_s}{c}$

$+2\mathrm{\π}\×140\×{10}^6\×\frac{R}{c}+{\mathrm{\φ}}_0]$

At t=(n+1) * T _sConstantly, sample is output as:

$s_3(n+1)=A\cos [2\mathrm{\π}\×25\×{10}^6\×(n+1)\×T_s-2\mathrm{\π}\×140\×{10}^6\×\frac{v\×(n+1)\×T_s}{c}$

$+2\mathrm{\π}\×140\×{10}^6\×\frac{R}{c}+{\mathrm{\φ}}_0]$

Then n+1 with respect to n phase increment constantly is constantly:

$\mathrm{\δ\φ}(n+1)=2\mathrm{\π}\×25\×{10}^6\×T_s-2\mathrm{\π}\×140\×{10}^6\×\frac{v\×T_s}{c}$

Can know by following formula, need only the carrier phase difference that calculates adjacent two sampling instants according to terminal A motion model, can obtain the carrier phase of next sampling instant.

(2) simulation process of carrier doppler frequency

1. carrier wave NCO initialization

Calculate n=0 carrier phase constantly

$\mathrm{\φ}\left(0\right)=2\mathrm{\π}\×140\×{10}^6\×\frac{R}{c}+{\mathrm{\φ}}_0$ (radian)

Carrier wave NCO phase accumulator initial value does

Φ(0)＝[φ(0)-N(0)×2π]×2 ³²

N (0) is a carrier wave complete cycle count value,

Be carved into n+1 carrier wave NCO frequency word setting constantly during 2. from n

After obtaining n phase-accumulated value Φ (n) constantly, n+1 phase-accumulated value Φ (n+1) is constantly obtained by following process.

Calculate n+1 constantly with respect to n carrier phase increment constantly

$\mathrm{\δ\φ}(n+1)=\mathrm{\φ}(n+1)-\mathrm{\φ}\left(n\right)$

$=2\mathrm{\π}\×15\×{10}^6\×T_s-2\mathrm{\π}\×140\×{10}^6\×\frac{v\×T_s}{c}$

Obtaining carrier wave NCO frequency by phase difference, is to transform to frequency (Hz) from angular frequency (rad/s) divided by 2 π

$f_{\mathrm{NCO}}\left(n\right)=\frac{1}{2\mathrm{\π}}\×\frac{\mathrm{\δ\φ}(n+1)}{T_s}$

Carrier wave NCO frequency is converted into the NCO frequency word

$W\left(n\right)=f_{\mathrm{NCO}}\left(n\right)\×\frac{2^{32}}{62\×{10}^6}$

Like this, come temporarily at n+1 clock, after the one-accumulate computing, the phase-accumulated value of carrier wave NCO will be added to the corresponding NCO phase place of n+1 phase (n+1) constantly automatically

Φ(n+1)＝Φ(n)+W(n)

3. the carrier phase accumulator overflows

When the accumulated value of carrier wave NCO phase accumulator has surpassed maximum count 2 ³²The time, generation to be overflowed, its corresponding carrier phase has changed 2 π.This moment, phase-accumulated value and complete cycle count value were respectively

Φ(n)＝Φ(n)-2 ³²

N＝N+1

4. amplitude output signal

After obtaining the phase-accumulated value Φ of carrier wave NCO (n) in arbitrary moment,, calculate the phase place of corresponding cosine look-up table at first to its normalization:

$\mathrm{\θ}\left(n\right)=\frac{\mathrm{\Φ}\left(n\right)}{2^{32}}\×2\mathrm{\π}$ (radian)

Look into cosine table by θ (n) again, the outgoing carrier range value:

s(n)＝Acos[(θ(n)]

(3) generation comprises the principle of yard Doppler's bit rate clock

If the pseudo-code of terminal A emission is:

C ₀(t)＝PN(t-φ ₀)

In the formula, PN () is the GOLD sign indicating number of 5MHz for bit rate, φ ₀Be the pseudo-code initial phase.

If terminal A is v with respect to the radial velocity of terminal B, terminal A is B flight towards the terminal.Both radial distances are R when t=0, and then constantly the electromagnetic wave time that A propagates into terminal B antenna from the terminal is at t:

$\mathrm{\τ}=\frac{R-v\×t}{c}$

In the formula, c is the light velocity.

At this moment, the B pseudo-code that receives in terminal is:

$C_1\left(t\right)=C_0(t-\mathrm{\τ})$

$=\mathrm{PN}[t-\mathrm{\τ}-{\mathrm{\φ}}_0]$

$=\mathrm{PN}[t-\frac{R-v\×t}{c}-{\mathrm{\φ}}_0]$

To C ₁(t) after the discretization, t=n * T _sSample constantly is output as:

$C_1\left(n\right)=\mathrm{PN}[n\×T_s+\frac{v\×n\×T_s}{c}-\frac{R}{c}-{\mathrm{\φ}}_0]$

At t=(n+1) * T _sConstantly, sample is output as:

$C_1(n+1)=\mathrm{PN}[(n+1)\×T_s+\frac{v\×(n+1)\×T_s}{c}-\frac{R}{c}-{\mathrm{\φ}}_0]$

Then n+1 with respect to n phase increment constantly is constantly:

$\mathrm{\δ\φ}(n+1)=T_s+\frac{v\×T_s}{c}$

Can know by following formula,, can obtain the pseudo-code phase of next sampling instant as long as it is poor to calculate the pseudo-code phase of adjacent two sampling instants according to terminal A motion model.

(4) simulation process of sign indicating number clock Doppler frequency

1. set up the receiver motion model

When being located at t=0, the radial distance of terminal A and terminal B is R, and radial velocity between the two is v, establishes terminal A and moves to terminal B.

The code phase error of supposing this moment has been controlled within half chip.

Calculating is in t=0 pseudo-code phase (radian) constantly

$\mathrm{\φ}\left(0\right)=-2\mathrm{\π}\×5\×{10}^6\×\frac{R}{c}-{\mathrm{\φ}}_0$

Sign indicating number NCO phase accumulator initial value does

Ф(0)＝[φ(0)-N(0)×2π]×2 ³²

N (0) is whole chip count value,

2. calculate n+1 constantly with respect to n pseudo-code phase increment constantly

$\mathrm{\δ\φ}\left(n\right)=2\mathrm{\π}\×5\×(T_s+\frac{v\×T_s}{c})$

3. obtaining a yard NCO frequency by phase difference, is to transform to frequency (Hz) from angular frequency (rad/s) divided by 2 π

$f_{\mathrm{NCO}}\left(n\right)=\frac{1}{2\mathrm{\π}}\×\frac{\mathrm{\δ\φ}\left(n\right)}{T_s}$

4. sign indicating number NCO frequency is converted into the NCO frequency word

$W\left(n\right)=f_{\mathrm{NCO}}\left(n\right)\×\frac{2^{32}}{62\×{10}^6}$

5. in the code phase accumulator, the NCO frequency word is added up in each sampling instant

$\mathrm{\Φ}\left(n\right)=\underset{k=1}{\overset{n}{\mathrm{\Σ}}}W\left(k\right)$

As Φ (n)>=2 ³²The time, the code phase accumulator produces and once overflows, and whole chip count device adds 1

Φ(n)＝Φ(n)-2 ³²

Whole chip count value does

N＝N+1

6. according to whole chip count value N, look into code table, and export corresponding range value

C(n)＝PN(N)

The concrete generating run of pseudo-code in FPGA is: with system clock (62MHz) as sample frequency; At each rising edge clock the ROM look-up table is carried out single reading; When this clock trailing edge, the sign indicating number NCO frequency word that receives is carried out one-accumulate simultaneously; The index signal that the code phase accumulator is overflowed is upgraded ROM look-up table address as 5MHz bit rate clock, reads in next chip.

2, data set frame format layout part

The layout of data set frame format partly includes three sub-module and forms, and is respectively the processing sub that transmits, Synchronization Control submodule and interface processing sub.

Wherein, the interface relationship explanation is as shown in table 1 below between each module.

Title	Direction	Explanation	Remarks
				?RESn	IN	The emission modulation module resets	Effectively low
?CLK_in	IN	System clock	61.2MHz
				?A_BUS	IN	The DSP-FPGA address bus	Select least-significant byte for use
?CE	IN	DSP-FPGA gating end
				?AWE	IN	The DSP write signal	Rising edge is effective
?AOE	IN	The DSP read signal	Effectively low
				?D_BUS	IN	The DSP-FPGA data/address bus	32 of bit wides
?fifo_data_in	IN	Data segment Data Receiving position	The 4096bit/s serial data stream
				?fifo_wr_en	IN	Data segment receives read signal
?log_sow	IN	The local second enumeration data of duties section	32 of bit wides
				?log_bac	IN	The local preliminary data of duties section	26 of bit wides
?syn_pd	IN	The synchronous pseudo range data of duties section	32 of bit wides
				?syn_sow	IN	The duties section is second enumeration data synchronously	32 of bit wides
?syn_fra	IN	The synchronous subframe numbers data of duties section	9 of bit wides
				?syn_bac	IN	Duties section synchronized reserve data	6 of bit wides
?enable_transmit_sow	IN	Local second counting of host computer latchs index signal	Simultaneously as the radiating portion enabling signal
				?TIC_adjust	IN	The module initial time is proofreaied and correct	This signal is an enable signal
?TIC_adjust_counter	IN	Module initial time corrected value	25 of bit wides

CLK_out	OUT	System clock output	61.2MHz
				TIC_int	OUT	The dsp interrupt signal	0.2ms, send frequency word
TIC_pulse_Op2s_out	OUT	The duties segment data is upgraded pulse	0.2s
				pn_code	OUT	The Pn_ pseudo noise code	Sign indicating number NCO produces
NAV_data	OUT	Information data behind the framing
				data_to_dac	OUT	Deliver to the digital signal of DAC	14 of bit wides
nav_c_data	OUT	The spreading code data	Radio-frequency front-end requires output
				code_clk	OUT	The spreading code clock	Radio-frequency front-end requires output
clk_dac	OUT	The DAC work clock	61.2MHz
				sec_loc_pulse	OUT	Local pulse per second (PPS)	Pulsewidth 1ms
sec_adj_pulse	OUT	The synchronous correction pulse per second (PPS)	Pulsewidth 1ms transmits correcting value by DSP
				min_pulse	OUT	The pulse of local branch
frame_num_out	OUT	The Frame counting

Table 1

3, intermediate-freuqncy signal modulate emission part

Intermediate-freuqncy signal modulate emission part main modular comprises: frequency mixer, BPSK modulator, band pass filter, the amplifier of band automatic gain control, power combiner, emitter follower, attenuator etc.Frequency mixer carries out mixing with the single-carrier signal of centre frequency 25MHz with the 115MHz local oscillation signal, produces the 140MHz carrier signal.The 140MHz carrier signal gets into the amplifier of band pass filter and the control of band automatic gain, one tunnel direct output frequency 140MHz, level 3dBm carrier signal, and one the tunnel gets into the BPSK modulator, and base-band spread-spectrum signal is directly modulated.The BPSK modulation signal gets into the amplifier of band pass filter and the control of band automatic gain, the modulation signal that output amplitude is constant.This signal ingoing power synthesizer synthesizes with noise signal, exports the modulation signal of certain signal to noise ratio.Be divided into two-way through power divider then, after attenuator carries out amplitude fading, output BPSK modulation signal, centre frequency 140MHz, level-20dBm.

A kind of spread-spectrum signal source with Doppler analogue function of the present invention further comprises: 25MHz sinusoidal signal D/A change-over circuit; 5Mz sign indicating number clock generation circuit; Watchdog circuit etc.; In order to simulate Doppler; At the remote operation terminal; Initial data reaches the intermediate-freuqncy signal processor under LAN interface, according to the Doppler simulation control at remote operation terminal, the intermediate-freuqncy signal processor adopts carrier wave NCO+D/A and the mode of sign indicating number NCO+D/A to control carrier wave and the simulation of sign indicating number Doppler frequency simultaneously; The 25MHz sinusoidal signal that wherein will comprise Doppler exports radio-frequency front-end to; Through up-conversion output 140MHz radiofrequency signal, the 5MHz sinusoidal signal that will comprise Doppler is through filtering, relatively wait and handle the 5MHz sign indicating number clock that back output comprises Doppler, is used for producing launching pseudo-code.

Wherein, (1) 25MHz sinusoidal signal D/A change-over circuit

FPGA output center frequency is the 25MHz sinusoidal signal, behind D/A converter, is transformed into analog signal, and D/A converter adopts the 14-bit transducer DAC5675A of TI company:

When design D/A change-over circuit, noted following problem:

1. differential clocks design

In order to guarantee 14 conversion accuracy, the clock signal of DAC5675A must be provided by clock source high stability, utmost point low phase noise.In order to reach optimum performance, clock should adopt the differential mode input.In order to satisfy the differential clocks requirement, adopt the PECL chip for driving MC100ELT24D of ON SEMICONDUCTOR company to realize.

2. input signal differential design

The same with the D/A converter of most of high speeds, great dynamic range, the digital input end of DAC5675 adopts the LVDS differential mode, and differential digital output realizes through the FPGA output port being configured to the LVDS level.

3. current-differencing coupling

When adopting DAC5675,, therefore need accomplish the conversion that electric current outputs to voltage output through the current-differencing amplifying circuit owing to be the current-differencing output form.

For the input with radio-frequency front-end is complementary, realize difference current to voltage output conversion at the output of AD9744 through the current-differencing amplifying circuit, the stream differential amplifier circuit adopts the AD8056 of AD company to realize.

4. bandpass filtering

Other useless harmonic component for the output of filtering D/A converter adds band pass filter at the D/A output, and the filter leading indicator is following:

● centre frequency (fc): 25MHz

● 3dB relative bandwidth (%of fc): 5

● impedance: 50 Ω

● maximum standing-wave ratio VSWR:1.5: 1

● maximum Mean Input Power: 1W

● temperature range :-20 ℃ to+71 ℃

(2) 5Mz sign indicating number clock generation circuit

5MHz sign indicating number clock generation circuit is intended and is adopted two kinds of forms, and a kind of is digital mode, and another kind is a NCO+D/A+ shaping mode.

NCO+D/A+ shaping mode adopts the AD9744 analog to digital converter to combine zero-crossing comparator to realize.

D/A converter is selected the AD9744 of AD company for use, and AD9744 is 14-bit, the 210MSPS high accuracy D/A converter of AD company.

2 points below when design D/A change-over circuit, having noted: current-differencing coupling and bandpass filtering.

1. current-differencing coupling

When adopting AD9744,,, realize that through the current-differencing amplifying circuit difference current is to voltage output conversion at the output of AD9744 therefore for the input with radio-frequency front-end is complementary owing to be the current-differencing output form.The current-differencing amplifying circuit adopts the AD8056 of AD company to realize that AD8056 is the common voltage feedback operational amplifier of AD company.

2. bandpass filtering

Because the output of D/A converter has a large amount of harmonic waves, therefore also need to carry out filtering through wave filter again.

3. comparator circuit

Comparator circuit adopts zero-crossing comparator to realize.This circuit can be imported bipolarity (here for sinusoidal wave) and convert unipolar square wave output into, realizes the zero balancing of crossing to input signal through all add identical dc offset voltage at in-phase input end and reverse input end.

Comparator selects that the 4ns of Analog Device company is supper-fast, single supply comparator AD8611 for use.

(3) watchdog circuit

In order effectively to monitor power supply power supply situation and DSP operating state, watchdog circuit is set in circuit, watchdog circuit adopts the MAX705 of MAXIM company to realize.

The following function of main completion:

● when voltage is lower than a certain threshold value, produce low reset signal

● when monitoring DSP when exporting acomia changing within a certain period of time, produce low reset signal.

The objective of the invention is to a kind of spread-spectrum signal source with Doppler analogue function, its advantage and effect are:

1. possesses dynamic and time delay function, in order to detection by quantitative receiving terminal performance in the transmission channel simulation;

2. spread spectrum transmitter and channel simulation function are integrated, equipment and degree are high;

3. the simulation precision to the actual vector motion conditions is high, and is higher than the analog signal time delay precision with channel simulator simultaneously, can reach simulation error and be no more than 0.1ns;

4. can increase motion model flexibly, each item index performance of test receiver under different motion states.

(4) description of drawings:

The range accuracy error calibration method 1 that Fig. 1 is traditional.

The range accuracy error calibration method 2 that Fig. 2 is traditional.

Shown in Figure 3 is the partly relation between each submodule of data set frame format layout.

Shown in Figure 4 is the electric current output DC coupling circuit figure of AD9744.

(5) embodiment:

A kind of spread-spectrum signal source of the present invention with Doppler analogue function; Be the radiating portion that is called " intermediate-freuqncy signal processor " in the patent of invention of " bidirectional ranging and time ratio are to processing terminal " as applicant's separate case applicant's name, be responsible for the generation of intermediate-freuqncy signal processor internal data, formatting, Doppler's dynamic characteristic is simulated and the realization of functions such as data-modulated emission.

A kind of spread-spectrum signal source with Doppler analogue function of the present invention mainly can be divided into Doppler's dynamic analog, the layout of data set frame format and three parts of intermediate-freuqncy signal modulate emission.

Wherein, The main dynamic analog of realizing the processor motion state of Doppler's dynamic analog part: through the design of sign indicating number NCO; Accomplishing range finding pseudo-code dynamic characteristic realizes; Make the pseudo-code of generation meet separately sequential and correlation properties, and realize that two kinds of pseudo-code phase are corresponding one by one, so that correctly modulate navigation message; Through the design of carrier wave NCO, just accomplishing, the generation and the dynamic characteristic of (surplus) string digital carrier realize.Data set frame format layout part is main to realize that band sends the generation and the framing of information data in the processor; Have in mainly comprising: frame synchronization; Subframe numbers; The useful information that receiver sections such as this locality information lock in time and this machine data need, the timing Design of counter requires navigation message data phase and pseudo-code chip phase to be mapped according to the base band band spectrum modulation through epoch.The intermediate-freuqncy signal modulate emission is partly accomplished the sign indicating number band spectrum modulation of information data and pseudo-code data, sends simultaneously with the digital carrier that generates simultaneously, and software is outside accomplishes carrier modulation through peripheral modulator, and complete intermediate-freuqncy signal is sent through radio-frequency front-end.

1, Doppler's dynamic analog part

The Doppler simulation part calculates carrier wave NCO control word, and exports the transmission channel subsystem to according to the control of control panel or host computer, and control produces the carrier wave of Doppler frequency; The simulation process of synchronous carrying out yard clock Doppler frequency: calculate spread-spectrum pseudo code NCO control word, produce the bit rate clock that comprises yard Doppler, produce the pseudo-code that is used for the data band spectrum modulation through the mode of looking into code table.

(1) control produces the principle of the carrier wave of Doppler frequency

Adopt DDS technical pattern to generate the dynamic digital carrier wave in the present invention's design, the carrier wave NCO control word that receives is carried out the NCO accumulating operation, after through amplitude quantizing and phase quantization, through phase-magnitude look-up table output digital carrier.Have multidate informations such as speed and acceleration for the digital carrier that makes generation, adopt carrier wave NCO mode to carry out chip count and complete cycle count.The frequency word of carrier wave NCO is set up and is resolved through the carrier doppler simulation model and obtains.Carrier doppler simulation specifically is designed to (even to add (subtracting) fast rectilinear motion be example with terminal A):

If the signal of terminal A emission is:

s ₀(t)＝Acos(2π×140×10 ⁶×t-φ ₀)

In the formula, φ ₀Be initial phase (radian).

If terminal A is v with respect to the radial velocity of terminal B, terminal A is B flight towards the terminal.Both radial distances are R when t=0, and then constantly the electromagnetic wave time that A propagates into terminal B antenna from the terminal is at t:

$\mathrm{\τ}=\frac{R-v\×t}{c}$

In the formula, c is the light velocity.

What at this moment, terminal B received is to have postponed the satellite-signal of τ after second

$s_1\left(t\right)=s_0(t-\mathrm{\τ})$

$=A\cos [2\mathrm{\π}\×140\×{10}^6\×(t-\mathrm{\τ})-{\mathrm{\φ}}_0]$

$=A\cos [2\mathrm{\π}\×140\×{10}^6\×(t-\frac{R-v\×t}{c})-{\mathrm{\φ}}_0]$

$=A\cos [2\mathrm{\π}\×140\×{10}^6\×(t+\frac{v\×t}{c})-2\mathrm{\π}\×140\×{10}^6\×\frac{R}{c}-{\mathrm{\φ}}_0]$

Terminal B is to s ₁(t) carry out down-conversion, obtain the intermediate-freuqncy signal that nominal frequency is 25MHz

$s_2\left(t\right)=s_1\left(t\right)\·\cos (2\mathrm{\π}\×115\×{10}^6\×t)$

$=A\cos [2\mathrm{\π}\×140\×{10}^6\×(t+\frac{v\×t}{c})-2\mathrm{\π}\×140\×{10}^6\×\frac{R}{c}-{\mathrm{\φ}}_0]\·\cos (2\mathrm{\π}\×115\×{10}^6\×t)$

$=A\cos [2\mathrm{\π}\×25\×{10}^6\×t+2\mathrm{\π}\×140\×{10}^6\×\frac{v\×t}{c}-2\mathrm{\π}\×140\×{10}^6\×\frac{R}{c}-{\mathrm{\φ}}_0]$

With the frequency of 62MHz to s ₂(t) sample, the output nominal frequency is the intermediate-freuqncy signal of 25MHz

$s_3\left(t\right)=s_2\left(t\right)\·\cos (2\mathrm{\π}\×62\×{10}^6\×t)$

$=A\cos [-2\mathrm{\π}\×25\×{10}^6\×t+2\mathrm{\π}\×140\×{10}^6\×\frac{v\×t}{c}-2\mathrm{\π}\×140\×{10}^6\×\frac{R}{c}-{\mathrm{\φ}}_0]$

$=A\cos [2\mathrm{\π}\×25\×{10}^6\×t-2\mathrm{\π}\×140\×{10}^6\×\frac{v\×t}{c}+2\mathrm{\π}\×140\×{10}^6\×\frac{R}{c}+{\mathrm{\φ}}_0]$

To s ₃(t) after the discretization, t=n * T _sSample constantly is output as:

$s_3\left(n\right)=A\cos [2\mathrm{\π}\×25\×{10}^6\×n\×T_s-2\mathrm{\π}\×140\×{10}^6\×\frac{v\×n\×T_s}{c}$

$+2\mathrm{\π}\×140\×{10}^6\×\frac{R}{c}+{\mathrm{\φ}}_0]$

At t=(n+1) * T _sConstantly, sample is output as:

$s_3(n+1)=A\cos [2\mathrm{\π}\×25\×{10}^6\×(n+1)\×T_s-2\mathrm{\π}\×140\×{10}^6\×\frac{v\×(n+1)\×T_s}{c}$

$+2\mathrm{\π}\×140\×{10}^6\×\frac{R}{c}+{\mathrm{\φ}}_0]$

Then n+1 with respect to n phase increment constantly is constantly:

$\mathrm{\δ\φ}(n+1)=2\mathrm{\π}\×25\×{10}^6\×T_s-2\mathrm{\π}\×140\×{10}^6\×\frac{v\×T_s}{c}$

Can know by following formula, need only the carrier phase difference that calculates adjacent two sampling instants according to terminal A motion model, can obtain the carrier phase of next sampling instant.

(2) simulation process of carrier doppler frequency

1. carrier wave NCO initialization

Calculate n=0 carrier phase constantly

$\mathrm{\φ}\left(0\right)=2\mathrm{\π}\×140\×{10}^6\×\frac{R}{c}+{\mathrm{\φ}}_0$ (radian)

Carrier wave NCO phase accumulator initial value does

Φ(0)＝[φ(0)-N(0)×2π]×2 ³²

N (0) is a carrier wave complete cycle count value,

Be carved into n+1 carrier wave NCO frequency word setting constantly during 2. from n

After obtaining n phase-accumulated value Φ (n) constantly, n+1 phase-accumulated value Φ (n+1) is constantly obtained by following process.

Calculate n+1 constantly with respect to n carrier phase increment constantly

$\mathrm{\δ\φ}(n+1)=\mathrm{\φ}(n+1)-\mathrm{\φ}\left(n\right)$

$=2\mathrm{\π}\×15\×{10}^6\×T_s-2\mathrm{\π}\×140\×{10}^6\×\frac{v\×T_s}{c}$

Obtaining carrier wave NCO frequency by phase difference, is to transform to frequency (Hz) from angular frequency (rad/s) divided by 2 π

$f_{\mathrm{NCO}}\left(n\right)=\frac{1}{2\mathrm{\π}}\×\frac{\mathrm{\δ\φ}(n+1)}{T_s}$

Carrier wave NCO frequency is converted into the NCO frequency word

$W\left(n\right)=f_{\mathrm{NCO}}\left(n\right)\×\frac{2^{32}}{62\×{10}^6}$

Like this, come temporarily at n+1 clock, after the one-accumulate computing, the phase-accumulated value of carrier wave NCO will be added to the corresponding NCO phase place of n+1 phase (n+1) constantly automatically

Φ(n+1)＝Φ(n)+W(n)

3. the carrier phase accumulator overflows

When the accumulated value of carrier wave NCO phase accumulator has surpassed maximum count 2 ³²The time, generation to be overflowed, its corresponding carrier phase has changed 2 π.This moment, phase-accumulated value and complete cycle count value were respectively

Φ(n)＝Φ(n)-2 ³²

N＝N+1

4. amplitude output signal

After obtaining the phase-accumulated value Φ of carrier wave NCO (n) in arbitrary moment,, calculate the phase place of corresponding cosine look-up table at first to its normalization:

$\mathrm{\θ}\left(n\right)=\frac{\mathrm{\Φ}\left(n\right)}{2^{32}}\×2\mathrm{\π}$ (radian)

Look into cosine table by θ (n) again, the outgoing carrier range value:

s(n)＝Acos[(θ(n)]

(3) generation comprises the principle of yard Doppler's bit rate clock

If the pseudo-code of terminal A emission is:

C ₀(t)＝PN(t-φ ₀)

In the formula, PN () is the GOLD sign indicating number of 5MHz for bit rate, φ ₀Be the pseudo-code initial phase.

If terminal A is v with respect to the radial velocity of terminal B, terminal A is B flight towards the terminal.Both radial distances are R when t=0, and then constantly the electromagnetic wave time that A propagates into terminal B antenna from the terminal is at t:

$\mathrm{\τ}=\frac{R-v\×t}{c}$

In the formula, c is the light velocity.

At this moment, the B pseudo-code that receives in terminal is:

$C_1\left(t\right)=C_0(t-\mathrm{\τ})$

$=\mathrm{PN}[t-\mathrm{\τ}-{\mathrm{\φ}}_0]$

$=\mathrm{PN}[t-\frac{R-v\×t}{c}-{\mathrm{\φ}}_0]$

To C ₁(t) after the discretization, t=n * T _sSample constantly is output as:

$C_1\left(n\right)=\mathrm{PN}[n\×T_s+\frac{v\×n\×T_s}{c}-\frac{R}{c}-{\mathrm{\φ}}_0]$

At t=(n+1) * T _sConstantly, sample is output as:

$C_1(n+1)=\mathrm{PN}[(n+1)\×T_s+\frac{v\×(n+1)\×T_s}{c}-\frac{R}{c}-{\mathrm{\φ}}_0]$

Then n+1 with respect to n phase increment constantly is constantly:

$\mathrm{\δ\φ}(n+1)=T_s+\frac{v\×T_s}{c}$

Can know by following formula,, can obtain the pseudo-code phase of next sampling instant as long as it is poor to calculate the pseudo-code phase of adjacent two sampling instants according to terminal A motion model.

(4) simulation process of sign indicating number clock Doppler frequency

1. set up the receiver motion model

When being located at t=0, the radial distance of terminal A and terminal B is R, and radial velocity between the two is v, establishes terminal A and moves to terminal B.

The code phase error of supposing this moment has been controlled within half chip.

Calculating is in t=0 pseudo-code phase (radian) constantly

$\mathrm{\φ}\left(0\right)=-2\mathrm{\π}\×5\×{10}^6\×\frac{R}{c}-{\mathrm{\φ}}_0$

Sign indicating number NCO phase accumulator initial value does

Ф(0)＝[φ(0)-N(0)×2π]×2 ³²

N (0) is whole chip count value,

2. calculate n+1 constantly with respect to n pseudo-code phase increment constantly

$\mathrm{\δ\φ}\left(n\right)=2\mathrm{\π}\×5\×(T_s+\frac{v\×T_s}{c})$

3. obtaining a yard NCO frequency by phase difference, is to transform to frequency (Hz) from angular frequency (rad/s) divided by 2 π

$f_{\mathrm{NCO}}\left(n\right)=\frac{1}{2\mathrm{\π}}\×\frac{\mathrm{\δ\φ}\left(n\right)}{T_s}$

4. sign indicating number NCO frequency is converted into the NCO frequency word

$W\left(n\right)=f_{\mathrm{NCO}}\left(n\right)\×\frac{2^{32}}{62\×{10}^6}$

5. in the code phase accumulator, the NCO frequency word is added up in each sampling instant

$\mathrm{\Φ}\left(n\right)=\underset{k=1}{\overset{n}{\mathrm{\Σ}}}W\left(k\right)$

As Φ (n)>=2 ³²The time, the code phase accumulator produces and once overflows, and whole chip count device adds 1

Ф(n)＝Φ(n)-2 ³²

Whole chip count value does

N＝N+1

6. according to whole chip count value N, look into code table, and export corresponding range value

C(n)＝PN(N)

The concrete generating run of pseudo-code in FPGA is: with system clock (62MHz) as sample frequency; At each rising edge clock the ROM look-up table is carried out single reading; When this clock trailing edge, the sign indicating number NCO frequency word that receives is carried out one-accumulate simultaneously; The index signal that the code phase accumulator is overflowed is upgraded ROM look-up table address as 5MHz bit rate clock, reads in next chip.

What need further specify is, for Doppler's dynamic analog part,

embodiment of the invention is the uniformly accelrated rectilinear motion model, and the Doppler frequency variation pattern is linear increasing; When acceleration was made as zero, this model became the fixing motion model of Doppler frequency.

frequency word quantified precision is made as 32 bits at present; Can improve quantified precision according to the Doppler simulation performance requirement, can rise to 48 bits and quantize.

The simulation of

sinusoidal variations: Doppler frequency changes according to sinuso sine protractor.

Can consider among the design to adopt the mode of tabling look-up to generate the Doppler frequency control word.Promptly calculate and quantize the Doppler frequency word (20000 times/second, resolution 0.1mHz) of each updated time, then frequency word is existed in the inner memory of FPGA as look-up table, get final product according to upgrading the renewal frequency word of tabling look-up at interval according to the motion simulation of root kind.

2, data set frame format layout part

The layout of data set frame format partly includes three sub-module and forms, and is respectively the processing sub that transmits, Synchronization Control submodule and interface processing sub.Relation between each submodule is as shown in Figure 3.

Wherein, the interface relationship explanation is as shown in table 2 below between each module.

Title	Direction	Explanation	Remarks
				RESn	IN	The emission modulation module resets	Effectively low
CLK_in	IN	System clock	61.2MHz
				A_BUS	IN	The DSP-FPGA address bus	Select least-significant byte for use
CE	IN	DSP-FPGA gating end
				AWE	IN	The DSP write signal	Rising edge is effective
AOE	IN	The DSP read signal	Effectively low
				D_BUS	IN	The DSP-FPGA data/address bus	32 of bit wides
fifo_data_in	IN	Data segment Data Receiving position	The 4096bit/s serial data stream
				fifo_wr_en	IN	Data segment receives read signal
log_sow	IN	The local second enumeration data of duties section	32 of bit wides
				log_bac	IN	The local preliminary data of duties section	26 of bit wides
syn_pd	IN	The synchronous pseudo range data of duties section	32 of bit wides
				syn_sow	IN	The duties section is second enumeration data synchronously	32 of bit wides
syn_fra	IN	The synchronous subframe numbers data of duties section	9 of bit wides
				syn_bac	IN	Duties section synchronized reserve data	6 of bit wides
enable_transmit_sow	IN	Local second counting of host computer latchs index signal	Simultaneously as the radiating portion enabling signal
				TIC_adjust	IN	The module initial time is proofreaied and correct	This signal is an enable signal
TIC_adjust_counter	IN	Module initial time corrected value	25 of bit wides
				CLK_out	OUT	System clock output	61.2MHz
TIC_int	OUT	The dsp interrupt signal	0.2ms, send frequency word
				TIC_pulse_Op2s_out	OUT	The duties segment data is upgraded pulse	0.2s
pn_code	OUT	The Pn_ pseudo noise code	Sign indicating number NCO produces
				NAV_data	OUT	Information data behind the framing
data_to_dac	OUT	Deliver to the digital signal of DAC	14 of bit wides
				nav_c_data	OUT	The spreading code data	Radio-frequency front-end requires output

code_clk	OUT	The spreading code clock	Radio-frequency front-end requires output
				clk_dac	OUT	The DAC work clock	?61.2MHz
sec_loc_pulse	OUT	Local pulse per second (PPS)	Pulsewidth 1ms
				sec_adj_pulse	OUT	The synchronous correction pulse per second (PPS)	Pulsewidth 1ms transmits correcting value by DSP
min_pulse	OUT	The pulse of local branch
				frame_num_out	OUT	The Frame counting

Table 2

3, intermediate-freuqncy signal modulate emission part

Intermediate-freuqncy signal modulate emission part main modular comprises: frequency mixer, BPSK modulator, band pass filter, the amplifier of band automatic gain control, power combiner, emitter follower, attenuator etc.Frequency mixer carries out mixing with the single-carrier signal of centre frequency 25MHz with the 115MHz local oscillation signal, produces the 140MHz carrier signal.The 140MHz carrier signal gets into the amplifier of band pass filter and the control of band automatic gain, one tunnel direct output frequency 140MHz, level 3dBm carrier signal, and one the tunnel gets into the BPSK modulator, and base-band spread-spectrum signal is directly modulated.The BPSK modulation signal gets into the amplifier of band pass filter and the control of band automatic gain, the modulation signal that output amplitude is constant.This signal ingoing power synthesizer synthesizes with noise signal, exports the modulation signal of certain signal to noise ratio.Be divided into two-way through power divider then, after attenuator carries out amplitude fading, output BPSK modulation signal, centre frequency 140MHz, level-20dBm.

A kind of spread-spectrum signal source with Doppler analogue function of the present invention further comprises: 25MHz sinusoidal signal D/A change-over circuit; 5Mz sign indicating number clock generation circuit; Watchdog circuit etc.; In order to simulate Doppler; At the remote operation terminal; Initial data reaches the intermediate-freuqncy signal processor under LAN interface, according to the Doppler simulation control at remote operation terminal, the intermediate-freuqncy signal processor adopts carrier wave NCO+D/A and the mode of sign indicating number NCO+D/A to control carrier wave and the simulation of sign indicating number Doppler frequency simultaneously; The 25MHz sinusoidal signal that wherein will comprise Doppler exports radio-frequency front-end to; Through up-conversion output 140MHz radiofrequency signal, the 5MHz sinusoidal signal that will comprise Doppler is through filtering, relatively wait and handle the 5MHz sign indicating number clock that back output comprises Doppler, is used for producing launching pseudo-code.

Wherein, (1) 25MHz sinusoidal signal D/A change-over circuit

FPGA output center frequency is the 25MHz sinusoidal signal, behind D/A converter, is transformed into analog signal, and D/A converter adopts the 14-bit transducer DAC5675A of TI company,

● the 400MSPS sample rate

● compatible LVDS input interface

● good inerrancy dynamic range (SFDR), SFDR is with respect to Nyquist rate:

-69dBc70MHz intermediate frequency, 400MSPS

● 1.2V reference voltage on the sheet

● single 3.3V power supply

● power consumption: 660mW, 20MHz output, 400MSPS

When design D/A change-over circuit, noted following problem:

1. differential clocks design

In order to guarantee 14 conversion accuracy, the clock signal of DAC5675A must be provided by clock source high stability, utmost point low phase noise.In order to reach optimum performance, clock should adopt the differential mode input.In order to satisfy the differential clocks requirement, adopt the PECL chip for driving MC100ELT24D of ON SEMICONDUCTOR company to realize.

2. input signal differential design

The same with the D/A converter of most of high speeds, great dynamic range, the digital input end of DAC5675 adopts the LVDS differential mode, and differential digital output realizes through the FPGA output port being configured to the LVDS level.

3. current-differencing coupling

When adopting DAC5675,, therefore need accomplish the conversion that electric current outputs to voltage output through the current-differencing amplifying circuit owing to be the current-differencing output form.

For the input with radio-frequency front-end is complementary, realize difference current to voltage output conversion at the output of AD9744 through the current-differencing amplifying circuit, the stream differential amplifier circuit adopts the AD8056 of AD company to realize.

4. bandpass filtering

Other useless harmonic component for the output of filtering D/A converter adds band pass filter at the D/A output, and the filter leading indicator is following:

● centre frequency (fc): 25MHz

● 3dB relative bandwidth (%of fc): 5

● impedance: 50 Ω

● maximum standing-wave ratio VSWR:1.5: 1

● maximum Mean Input Power: 1W

● temperature range :-20 ℃ to+71 ℃

(2) 5Mz sign indicating number clock generation circuit

5MHz sign indicating number clock generation circuit is intended and is adopted two kinds of forms, and a kind of is digital mode, and another kind is a NCO+D/A+ shaping mode.

Digital mode is inner through digital NCO realization at FPGA fully, and this mode realizes simply, but when the work clock of NCO aligns with a sign indicating number rising edge clock, possibly have jitter problem.

The mode of NCO+D/A+ shaping can solve above-mentioned deficiency preferably, but realizes going up trouble relatively.NCO+D/A+ shaping mode adopts the AD9744 analog to digital converter to combine zero-crossing comparator to realize.

D/A converter is selected the AD9744 of AD company for use, and AD9744 is 14-bit, the 210MSPS high accuracy D/A converter of AD company, and its main performance is following:

● 14-bit resolution

● high-performance TxDAC series pin compatibility

The compatible 8-bit of-TxDAC series, 10-bit, 12-bit, 14-bit DAC chip pin

● good inerrancy dynamic range (SFDR), SFDR is with respect to Nyquist rate:

-83dB5MHz output

-80dB10MHz output

-73dB20MHz output

● SNR5MHz output, 125MHzMSPS:77dB

● the complement of two's two's complement or straight binary data format

● difference current output: 2mA-20mA

● power consumption: 135mA3.3V

● shutdown mode: 15mA3.3V

● 1.2V reference voltage in the sheet

● the cmos digital interface compatibility

● the edge triggers and latchs

● at a high speed, the switching rate of 165MHz is supported in single-ended cmos clock input

● operating voltage:

-AVDD：3.3V

-DVDD：3.3V

-CLKVDD：3.3V

● full scale output current: 2mA-20mA

● output resistance: 100K Ω

● output capacitance: 5pF

● temperature range :-40 ℃ to+85 ℃

2 points below when design D/A change-over circuit, having noted: current-differencing coupling and bandpass filtering.

1. current-differencing coupling

When adopting AD9744,,, realize that through the current-differencing amplifying circuit difference current is to voltage output conversion at the output of AD9744 therefore for the input with radio-frequency front-end is complementary owing to be the current-differencing output form.The current-differencing amplifying circuit adopts the AD8056 of AD company to realize that AD8056 is the common voltage feedback operational amplifier of AD company, and main performance is following:

● bandwidth:

-250MHz small-signal, G=1

-130MHz large-signal (VP-P=2V), G=1

● exemplary currents: 5.8mA

● low distortion, low noise

--66dBc5MHz

--54dBc20MHz

-52nV/√Hz

● capacitive load driving force: 5pF

● at a high speed:

-ramp rate: 750V/us

● ± 3V arrives ± the 6V voltage range

● temperature range :-40 ℃ to+85 ℃

Adopt the electric current output DC coupling circuit of AD8047, as shown in Figure 4.

2. bandpass filtering

Because the output of D/A converter has a large amount of harmonic waves, therefore also need to carry out filtering through wave filter again, the band pass filter leading indicator is following:

● centre frequency (Fcenter) 5MHz

● 1dB bandwidth (BWpass) 30kHz

● band internal loss (IL)≤10dB

● bandwidth of rejection (BWstop) 100kHz

● stopband attenuation (Astop) >=20dB

● bear power >=10dBm

● input and output impedance 50 Ω

● maximum standing-wave ratio 1.5: 1

3. comparator circuit

Comparator circuit adopts zero-crossing comparator to realize.This circuit can be imported bipolarity (here for sinusoidal wave) and convert unipolar square wave output into, realizes the zero balancing of crossing to input signal through all add identical dc offset voltage at in-phase input end and reverse input end.

Comparator selects that the 4ns of Analog Device company is supper-fast, single supply comparator AD8611 for use.

The key property of AD8611:

transmission delay: 5ns5V

3V-5V single power supply

100MHz input

latch function

temperature range :-40 ℃ to+85 ℃

(3) FPGA type selecting

In order to accelerate Development Schedule, according to existing development Experience, FPGA adopts the new VIRTEX-4 series of X C4VSX55 that releases of XILINX company to realize.Compare with XILINX company other series, XC4VSX55 is more suitable for carrying out high-speed digital signal and handles, and it has following characteristics:

● to very-high performance Digital Signal Processing Application Design;

● nearly 55,296 logical blocks (Logic Cells) realize complicated signal processing and control logic,

● have 500MHz DCM digital dock manager,

● PMCD phase matched Clock dividers;

● differential clocks network on the sheet;

● adopt the 500MHz SmartRAM technology and the integrated 1 Gbps I/O of ChipSync source simultaneous techniques of integrated fifo control logic.

● chip also provides nearly 512 XtremeDSPs; Each XtremeDSPs can the performance work of 256GigaMAC/seconds (18 * 18) altogether of 500MHz throughput; Consumed power is merely 23mW/MHz; More than 40 kind of difference in functionality of the configurable establishment of XtremeDSPs, the full speed cascade of these XtremeDSPs can be used to realize multiple high performance digital signal processing algorithm.

● Virtex-4FPGA has fabulous low speed paper tape reader static power disspation and low dynamic power consumption performance,

(4) DSP type selecting

According to real work demand and application experience in the past, DSP adopts the high performance float-point DSP TMS320C6701 of TI company, and its key property is following:

● the Floating-point DSP that performance is the highest

-8.3-, 6.7-, 6-ns instruction cycle time

-120-, 150-, 167-MHz clock rate

-8 32-bit instruction/circulations

-1?GFLOPS

● the senior very CLIW of VelociTITM (VLIW) ' C67 * CPU core

-8 height independent functional units

4 ALUs (floating-point and fixed point)

2 ALUs (fixed point)

2 multipliers (floating-point and fixed point)

-have a load store structure of 32 32-bit general registers

-instruction packing reduces code length

-the instruction of having ready conditions entirely

● the instruction set characteristic

The instruction of-hardware supports IEEE single precision

The instruction of-hardware supports IEEE double precision

But-byte addressing (8-, 16,32-bit data)

-location is extracted, is provided with, is removed

Add up in-position

● the 1M-Bit on-chip SRAM

-512K-bit internal processes/high-speed cache (16K 32-bit instruction)

The two access internal datas (64K-byte) of-512K-bit

● 32-bit external memory interface (EMIF)

-with synchronous memories seamless interfacing: SDRAM and SBSRAM

-with asynchronous memory seamless interfacing: SRAM and EPROM

-52M-byte addressing external memory storage space

● the four-way bootstrapping that has an accessory channel loads immediate data access (DMA) controller

● 16-Bit host side interface (HPI)

-can the travel all over memory mapped

● 2 multichannel buffer serial ports (McBSPs)

● 2 32-Bit general purpose timers

● phase-locked loop (PLL) clock generator flexibly

● IEEE-1149.1 (JTAG) boundary scan is compatible

● 352 pin BGA encapsulation

● 0.18um/5 layer smithcraft

-CMOS technology

● 3.3V I/Os, and the 1.8V core operational voltage (120-, 150-MHz)

● 3.3V I/Os, 1.9V core operational voltage (167-MHz)

● Work Packages temperature range :-0 ℃ to+90 ℃ (default value)

-40 ℃ to+105 ℃ (A version)

The recommended work condition is as shown in table 3 below:

Table 3

Electrical property under recommended work voltage and package temperature, as shown in table 4 below:

Table 4

(5) watchdog circuit

In order effectively to monitor power supply power supply situation and DSP operating state, watchdog circuit is set in circuit, watchdog circuit adopts the MAX705 of MAXIM company to realize.

The following function of main completion:

● when voltage is lower than a certain threshold value, produce low reset signal

● when monitoring DSP when exporting acomia changing within a certain period of time, produce low reset signal.

Claims (7)

1. spread frequency signal generator with Doppler analogue function, it is characterized in that: this spread frequency signal generator is divided into Doppler's dynamic analog, the layout of data set frame format and three parts of intermediate-freuqncy signal modulate emission;

(1) Doppler's dynamic analog part

The main dynamic analog of realizing the processor motion state of described Doppler's dynamic analog part: according to the control of control panel or host computer, calculate carrier wave NCO control word, and export the transmission channel subsystem to, control produces the carrier wave of Doppler frequency; The simulation process of synchronous carrying out yard clock Doppler frequency: calculate spread-spectrum pseudo code NCO control word, produce the bit rate clock that comprises yard Doppler, produce the pseudo-code that is used for the data band spectrum modulation through the mode of looking into code table;

Wherein, control produces the carrier wave of Doppler frequency, and promptly the simulation process of carrier doppler frequency is following:

1. carrier wave NCO initialization

Calculate n=0 carrier phase constantly

$\mathrm{\φ}\left(0\right)=2\mathrm{\π}\×140\×{10}^6\×\frac{R}{c}+{\mathrm{\φ}}_0$ Wherein, φ ₀Be initial phase;

Carrier wave NCO phase accumulator initial value does

Φ(0)＝[φ(0)-N(0)×2π]×2 ³²

N (0) is a carrier wave complete cycle count value,

Be carved into n+1 carrier wave NCO frequency word setting constantly during 2. from n

After obtaining n phase-accumulated value Φ (n) constantly, n+1 phase-accumulated value Φ (n+1) is constantly obtained by following process;

Calculate n+1 constantly with respect to n carrier phase increment constantly

$\mathrm{\δ\φ}(n+1)=\mathrm{\φ}(n+1)-\mathrm{\φ}\left(n\right)$

$=2\mathrm{\π}\×15\×{10}^6\×T_s-2\mathrm{\π}\×140\×{10}^6\×\frac{v\×T_s}{c}$

Obtaining carrier wave NCO frequency by phase difference, is to transform to frequency (Hz) from angular frequency (rad/s) divided by 2 π

$f_{\mathrm{NCO}}\left(n\right)=\frac{1}{2\mathrm{\π}}\×\frac{\mathrm{\δ\φ}(n+1)}{T_s}$

Carrier wave NCO frequency is converted into the NCO frequency word

$W\left(n\right)=f_{\mathrm{NCO}}\left(n\right)\×\frac{2^{32}}{62\×{10}^6}$

Like this, come temporarily at n+1 clock, after the one-accumulate computing, the phase-accumulated value of carrier wave NCO will be added to the corresponding NCO phase place of n+1 phase (n+1) constantly automatically

Φ(n+1)＝Φ(n)+W(n)

3. the carrier phase accumulator overflows

When the accumulated value of carrier wave NCO phase accumulator has surpassed maximum count 2 ³²The time, generation to be overflowed, its corresponding carrier phase has changed 2 π; This moment, phase-accumulated value and complete cycle count value were respectively

Φ(n)＝Φ(n)-2 ³²

N＝N+1

4. amplitude output signal

After obtaining the phase-accumulated value Φ of carrier wave NCO (n) in arbitrary moment,, calculate the phase place of corresponding cosine look-up table at first to its normalization:

$\mathrm{\θ}\left(n\right)=\frac{\mathrm{\Φ}\left(n\right)}{2^{32}}\×2\mathrm{\π}$

Look into cosine table by θ (n) again, the outgoing carrier range value:

s(n)＝Acos[(θ(n)]

Wherein, the simulation process of sign indicating number clock Doppler frequency is following:

1. set up the receiver motion model

When being located at t=0, the radial distance of terminal A and terminal B is R, and radial velocity between the two is v, establishes terminal A and moves to terminal B;

The code phase error of supposing this moment has been controlled within half chip;

Calculating is in t=0 pseudo-code phase constantly

$\mathrm{\φ}\left(0\right)=-2\mathrm{\π}\×5\×{10}^6\×\frac{R}{c}-{\mathrm{\φ}}_0$

Sign indicating number NCO phase accumulator initial value does

Φ(0)＝[φ(0)-N(0)×2π]×2 ³²

N (0) is whole chip count value,

2. calculate n+1 constantly with respect to n pseudo-code phase increment constantly

$\mathrm{\δ\φ}\left(n\right)=2\mathrm{\π}\×5\×(T_s+\frac{v\×T_s}{c})$

3. obtaining a yard NCO frequency by phase difference, is to transform to frequency (Hz) from angular frequency (rad/s) divided by 2 π

$f_{\mathrm{NCO}}\left(n\right)=\frac{1}{2\mathrm{\π}}\×\frac{\mathrm{\δ\φ}\left(n\right)}{T_s}$

4. sign indicating number NCO frequency is converted into the NCO frequency word

$W\left(n\right)=f_{\mathrm{NCO}}\left(n\right)\×\frac{2^{32}}{62\×{10}^6}$

5. in the code phase accumulator, the NCO frequency word is added up in each sampling instant

$\mathrm{\Φ}\left(n\right)=\underset{k=1}{\overset{n}{\mathrm{\Σ}}}W\left(k\right)$

As Φ (n)>=2 ³²The time, the code phase accumulator produces and once overflows, and whole chip count device adds 1

Φ(n)＝Φ(n)-2 ³²

Whole chip count value does

N＝N+1

6. according to whole chip count value N, look into code table, and export corresponding range value

C(n)＝PN(N)

(2) data set frame format layout part

Data set frame format layout part is main to realize that band sends the generation and the framing of information data in the processor; Information data mainly comprise in have: frame synchronization, subframe numbers, local lock in time information and this machine data receiver section needs useful information, the timing Design of counter is mapped navigation message data phase and pseudo-code chip phase according to the requirement of base band band spectrum modulation through epoch; The layout of data set frame format partly includes three sub-module and forms, and is respectively the processing sub that transmits, Synchronization Control submodule and interface processing sub;

(3) intermediate-freuqncy signal modulate emission part

The intermediate-freuqncy signal modulate emission is partly accomplished the sign indicating number band spectrum modulation of information data and pseudo-code data, sends simultaneously with the digital carrier that generates simultaneously, and software is outside accomplishes carrier modulation through peripheral modulator, and complete intermediate-freuqncy signal is sent through radio-frequency front-end; Intermediate-freuqncy signal modulate emission part main modular comprises: frequency mixer, BPSK modulator, band pass filter, amplifier, power combiner, emitter follower, the attenuator of the control of band automatic gain; Frequency mixer carries out mixing with the single-carrier signal of centre frequency 25MHz with the 115MHz local oscillation signal, produces the 140MHz carrier signal; The 140MHz carrier signal gets into the amplifier of band pass filter and the control of band automatic gain, one tunnel direct output frequency 140MHz, level 3dBm carrier signal, and one the tunnel gets into the BPSK modulator, and base-band spread-spectrum signal is directly modulated; The BPSK modulation signal gets into the amplifier of band pass filter and the control of band automatic gain, the modulation signal that output amplitude is constant; This signal ingoing power synthesizer synthesizes with noise signal, exports the modulation signal of certain signal to noise ratio; Be divided into two-way through power divider then, after attenuator carries out amplitude fading, output BPSK modulation signal, centre frequency 140MHz, level-20dBm.

2. the spread frequency signal generator with Doppler analogue function according to claim 1; It is characterized in that: described this spread frequency signal generator further comprises: 25MHz sinusoidal signal D/A change-over circuit, 5MHz sign indicating number clock generation circuit and watchdog circuit; In order to simulate Doppler; At the remote operation terminal; Initial data reaches the intermediate-freuqncy signal processor under LAN interface, according to the Doppler simulation control at remote operation terminal, the intermediate-freuqncy signal processor adopts carrier wave NCO+D/A and the mode of sign indicating number NCO+D/A to control carrier wave and the simulation of sign indicating number Doppler frequency simultaneously; The 25MHz sinusoidal signal that wherein will comprise Doppler exports radio-frequency front-end to; Through up-conversion output 140MHz radiofrequency signal, the 5MHz sinusoidal signal that will comprise Doppler is exported the 5MHz sign indicating number clock that comprises Doppler after filtering, comparison process, be used for producing the emission pseudo-code.

3. the spread frequency signal generator with Doppler analogue function according to claim 2; It is characterized in that: described 25MHz sinusoidal signal D/A change-over circuit; Specifically be for FPGA output center frequency be the 25MHz sinusoidal signal; Behind D/A converter, be transformed into analog signal, D/A converter adopts the 14-bit transducer DAC5675A of TI company.

4. the spread frequency signal generator with Doppler analogue function according to claim 3 is characterized in that: described D/A change-over circuit designs as follows:

1. differential clocks design

In order to guarantee 14 conversion accuracy, the clock signal of DAC5675A must be provided by clock source high stability, utmost point low phase noise; In order to reach optimum performance, clock should adopt the differential mode input; In order to satisfy the differential clocks requirement, adopt the PECL chip for driving MC100ELT24D of ON SEMICONDUCTOR company to realize;

2. input signal differential design

The same with the D/A converter of most of high speeds, great dynamic range, the digital input end of DAC5675A adopts the LVDS differential mode, and differential digital output realizes through the FPGA output port being configured to the LVDS level;

3. current-differencing coupling

When adopting DAC5675,, therefore need accomplish the conversion that electric current outputs to voltage output through the current-differencing amplifying circuit owing to be the current-differencing output form;

For the input with radio-frequency front-end is complementary, at the A/D chip, promptly the output of AD9744 is realized difference current to voltage output conversion through the current-differencing amplifying circuit, and the stream differential amplifier circuit adopts the AD8056 of AD company to realize;

4. bandpass filtering

Other useless harmonic component for the output of filtering D/A converter adds band pass filter at the D/A output, and the filter leading indicator is following:

● centre frequency (fc): 25MHz

● 3dB relative bandwidth (%of fc): 5

● impedance: 50 Ω

● maximum standing-wave ratio VSWR:1.5: 1

● maximum Mean Input Power: 1W

● temperature range :-20 ℃～+ 71 ℃.

5. the spread frequency signal generator with Doppler analogue function according to claim 2 is characterized in that: described 5MHz sign indicating number clock generation circuit adopts two kinds of forms, and a kind of is digital mode, and another kind is a NCO+D/A+ shaping mode;

NCO+D/A+ shaping mode adopts the AD9744 analog to digital converter to combine zero-crossing comparator to realize;

D/A converter is selected the AD9744 of AD company for use, and AD9744 is 14-bit, the 210MSPS high accuracy D/A converter of AD company.

6. the spread frequency signal generator with Doppler analogue function according to claim 5 is characterized in that: in the described NCO+D/A+ shaping mode, the D/A change-over circuit designs as follows:

1. current-differencing coupling

When adopting AD9744,,, realize that through the current-differencing amplifying circuit difference current is to voltage output conversion at the output of AD9744 therefore for the input with radio-frequency front-end is complementary owing to be the current-differencing output form; The current-differencing amplifying circuit adopts the AD8056 of AD company to realize that AD8056 is the common voltage feedback operational amplifier of AD company;

2. bandpass filtering

Because the output of D/A converter has a large amount of harmonic waves, therefore also need to carry out filtering through wave filter again;

3. comparator circuit

Comparator circuit adopts zero-crossing comparator to realize; This circuit converts the bipolarity input into unipolar square wave output, realizes the zero balancing of crossing to input signal through all add identical dc offset voltage at in-phase input end and reverse input end;

Comparator selects that the 4ns of Analog Device company is supper-fast, single supply comparator AD8611 for use.

7. the spread frequency signal generator with Doppler analogue function according to claim 2 is characterized in that: described watchdog circuit, be used to monitor power supply power supply situation and DSP operating state, and watchdog circuit adopts the MAX705 of MAXIM company to realize:

● when voltage is lower than a certain threshold value, produce low reset signal

● when monitoring DSP when exporting acomia changing within a certain period of time, produce low reset signal.

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