CN109410861B - Driver and display device - Google Patents
Driver and display device Download PDFInfo
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- CN109410861B CN109410861B CN201811415546.8A CN201811415546A CN109410861B CN 109410861 B CN109410861 B CN 109410861B CN 201811415546 A CN201811415546 A CN 201811415546A CN 109410861 B CN109410861 B CN 109410861B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a driver and a display device, wherein the driver comprises a first amplifier and a control circuit, and before a time schedule controller finishes initial configuration, the control circuit controls a scanning closing signal of a scanning signal to pass through the first amplifier; after the timing controller completes the initial configuration, the control circuit controls a scan-on signal and a scan-off signal of the scan signal to pass through the first amplifier. According to the technical scheme, the control circuit is arranged, so that only the scanning closing signal passes through the first amplifier before the time schedule controller completes initial configuration, and the display panel of the display device is not lightened; after the time schedule controller finishes the initial configuration, the scanning starting signal and the scanning closing signal can both pass through the first amplifier, and the display panel of the display device is controlled by normal driving, so that the problem of starting flicker of the display device is solved.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a driver and a display device.
Background
Liquid Crystal Displays (LCDs) have been widely used due to their light weight, thin thickness and low power consumption, for example: display screens of liquid crystal televisions, display screens of mobile phones, display screens of digital cameras, computer screens or notebook computer screens, etc., are dominant in the field of flat panel displays.
There are many types of lcds, and a Thin Film Transistor (Thin Film Transistor) lcd is mainly used, and controls the input of a scan signal through a tft switch, thereby controlling the display of a picture. The display screen driving system of the thin film transistor liquid crystal display mainly comprises: the display panel is called a Gate Driver Integrated Circuit (G-IC), a Source Driver Integrated Circuit (S-IC), and a Timing Controller (TCON), the Timing Controller receives an external signal, processes the signal and transmits the processed signal to the Gate Driver chip and the Source Driver chip, and the Gate Driver chip and the Source Driver chip drive the display panel of the tft-lcd to operate.
At present, when a thin film transistor liquid crystal display is just started, because a time sequence controller needs a certain time to read an external signal and complete the initialization configuration setting of a register in the time sequence controller, the signal output of the time sequence controller is in an unstable state in the time period, and the problem of starting flicker of the thin film transistor liquid crystal display is easy to occur.
Disclosure of Invention
The invention provides a driver, which aims to solve the problem that a thin film transistor liquid crystal display is easy to generate start-up flicker.
To achieve the above object, the present invention provides a driver for a display device, the driver comprising:
the display device comprises a first amplifier, a second amplifier and a control circuit, wherein the first amplifier is used for receiving scanning signals from a time sequence controller of the display device and amplifying the scanning signals, and the scanning signals comprise scanning starting signals and scanning stopping signals;
the control circuit is used for monitoring the initial configuration completion state of the time schedule controller, and before the time schedule controller completes the initial configuration, the control circuit controls the scanning closing signal of the scanning signal to pass through the first amplifier; after the timing controller completes initial configuration, the control circuit controls a scan-on signal and a scan-off signal of the scan signal to pass through the first amplifier.
Optionally, the control circuit has a first signal input terminal, a second signal input terminal, a third signal input terminal, a fourth signal input terminal, a first signal output terminal and a second signal output terminal, and the timing controller further outputs a configuration state signal;
the first signal input end and the second signal input end are used for inputting the scanning signals; the third signal input terminal and the fourth signal input terminal are used for inputting the configuration state signal; the first signal output end and the second signal output end are connected with the first amplifier;
the control circuit controls the signal output of the first signal output end according to the signal input by the first signal input end and the signal input by the third signal input end, and controls the signal output of the second signal output end according to the signal input by the second signal input end and the signal input by the fourth signal input end.
Optionally, the control circuit includes an and gate circuit and an or gate circuit, the and gate circuit has a first and gate input end, a second and gate input end and an and gate output end, and the or gate circuit has a first or gate input end, a second or gate input end and an or gate output end;
the first and gate input end forms the first signal input end, the first or gate input end forms the second signal input end, the second and gate input end forms the third signal input end, the second or gate input end forms the fourth signal input end, the and gate output end forms the first signal output end, and the or gate output end forms the second signal output end.
Optionally, the control circuit further includes an inverting circuit, the configuration state signal includes a configuration state forward signal and a configuration state inverting signal, the timing controller outputs the configuration state forward signal, and the configuration state forward signal passes through the inverting circuit to form the configuration state inverting signal.
Optionally, the first amplifier includes a first P-type field effect transistor, a second P-type field effect transistor, a third P-type field effect transistor, a fourth P-type field effect transistor, a first N-type field effect transistor, a second N-type field effect transistor, a third N-type field effect transistor, and a fourth N-type field effect transistor;
the input ends of the first P-type field effect transistor and the second P-type field effect transistor are electrically connected and form a first power supply input end;
the input ends of the third P-type field effect transistor and the fourth P-type field effect transistor are electrically connected and form a second power supply input end;
the input ends of the first N-type field effect transistor, the second N-type field effect transistor, the third N-type field effect transistor and the fourth N-type field effect transistor are electrically connected and form a third power supply input end;
the output end of the first P-type field effect transistor is electrically connected with the controlled ends of the second N-type field effect transistor and the fourth N-type field effect transistor, and the output end of the second P-type field effect transistor is electrically connected with the controlled ends of the first N-type field effect transistor and the third N-type field effect transistor;
the output end of the third P-type field effect transistor is electrically connected with the controlled end of the fourth P-type field effect transistor and the output end of the third N-type field effect transistor; the output end of the fourth P-type field effect transistor is electrically connected with the controlled end of the third P-type field effect transistor and the output end of the fourth N-type field effect transistor to form a scanning signal output end;
the first signal output end is electrically connected with the controlled end of the first P-type field effect transistor, and the second signal output end is electrically connected with the controlled end of the second P-type field effect transistor.
Optionally, the driver further includes a register, and the scan signal passes through the register before being transmitted to the control circuit.
The present invention also proposes a driver for a display device, the driver comprising:
the display device comprises a first amplifier, a second amplifier and a control circuit, wherein the first amplifier is used for receiving scanning signals from a time sequence controller of the display device and amplifying the scanning signals, and the scanning signals comprise scanning starting signals and scanning stopping signals;
the second amplifier is used for receiving the scanning signal from the first amplifier, amplifying the scanning signal and outputting the scanning signal;
the control circuit is used for monitoring the initial configuration completion state of the time schedule controller, and before the time schedule controller completes the initial configuration, the control circuit controls the scanning closing signal of the scanning signal to pass through the first amplifier; after the time schedule controller finishes the initial configuration, the control circuit controls the scanning starting signal and the scanning closing signal of the scanning signal to pass through the first amplifier;
and the register receives a scanning signal from a time sequence controller of the display device, is used for adjusting the output direction of the scanning signal and then transmits the scanning signal to the control circuit.
The invention also provides a display device, which comprises
A first driver;
a second driver;
the time schedule controller is electrically connected with the first driver and the second driver;
the scanning lines of the display panel are electrically connected with the first driver, and the data lines of the display panel are electrically connected with the second driver;
wherein the first driver includes:
the display device comprises a first amplifier, a second amplifier and a control circuit, wherein the first amplifier is used for receiving scanning signals from a time sequence controller of the display device and amplifying the scanning signals, and the scanning signals comprise scanning starting signals and scanning stopping signals;
the control circuit is used for monitoring the initial configuration completion state of the time schedule controller, and before the time schedule controller completes the initial configuration, the control circuit controls the scanning closing signal of the scanning signal to pass through the first amplifier; after the timing controller completes initial configuration, the control circuit controls a scan-on signal and a scan-off signal of the scan signal to pass through the first amplifier.
Optionally, the timing controller further outputs a configuration state forward signal, and before the initial configuration is completed, the configuration state forward signal is a low level signal; after the time sequence controller completes the initial configuration, the configuration state forward signal is a high level signal.
Optionally, the timing controller includes a signal reading module, a signal processing module and a signal output module, the signal reading module receives and reads signals from the outside and transmits the signals to the signal processing module, and the signals are converted and processed by the signal processing module and then output by the signal output module.
The technical scheme of the invention is that the control circuit is arranged and used for monitoring the initial configuration completion state of the time schedule controller, and before the time schedule controller completes the initial configuration, the control circuit controls the scanning closing signal of the scanning signal to pass through the first amplifier; after the timing controller completes the initial configuration, the control circuit controls a scan-on signal and a scan-off signal of the scan signal to pass through the first amplifier. Since only the scan-off signal passes through the first amplifier before the timing controller completes the initial configuration, the display panel of the display device is not lighted at this time; after the time schedule controller completes the initial configuration, the scanning start signal and the scanning stop signal can both pass through the first amplifier, and the display panel of the display device is controlled by the normal drive of the time schedule controller and the first driver, thereby solving the problem of the display device flickering when the display device is started.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a block diagram of a circuit configuration of a display device according to an embodiment of the present invention;
FIG. 2 is a block diagram of a first driver circuit shown in FIG. 1;
fig. 3 is a schematic diagram showing a specific circuit connection between the control circuit and the first amplifier in fig. 1.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The invention provides a driver and a display device, wherein the display device can be an electronic device with a display panel, such as a liquid crystal display, a liquid crystal television or a mobile phone.
In an embodiment of the present invention, as shown in fig. 1, the display device includes a timing controller 300, a display panel 400, a second driver 200, a first driver 100, and the like. The timing controller 300 is electrically connected to the second driver 200 and the first driver 100, the second driver 200 is electrically connected to the data line of the display panel 400, and the first driver 100 is electrically connected to the scan line of the display panel. The timing controller 300 includes a signal reading module, a signal processing module, and a signal output module, the signal reading module receives and reads data signals, control signals, and clock signals from the outside, and transmits the data signals, the control signals, and the clock signals to the signal processing module, and the signals are converted into data signals, control signals, and clock signals suitable for the second driver 200 and the first driver 100 by the signal processing module, and then output by the signal output module.
Specifically, as shown in fig. 2 and 3, the first driver 100 includes a register 10, a control circuit 20, a first amplifier 30, a second amplifier 40, and the like. The register 10 is used for adjusting the output direction of the scan signal, and the second amplifier 40 is used for improving the driving capability of the scan signal. The first amplifier 30 is configured to receive a scan signal from the timing controller 300 of the display device and amplify the scan signal. The scan signals include a scan on signal A and a scan off signal
The scan start signal A is a high level signal, and the scan stop signal
Is a low level signal, the scan-on signal A and the scan-off signal
Are opposite signals. The scan start signal a controls the communication of a source electrode and a drain electrode of a Thin Film Transistor (TFT), and the scan stop signal a controls the communication of a drain electrode and a source electrode of a TFT
And controlling the source electrode and the drain electrode of the thin film transistor to be disconnected.
The control circuit 20 is configured to monitor an initial configuration completion state of the timing controller 300, and before the timing controller 300 completes the initial configuration, the control circuit 20 controls a scan off signal of the scan signal
Through the first amplifier 30; after the timing controller 300 completes the initial configuration, the control circuit 20 controls the scan-on signal a and the scan-off signal a of the scan signals
Through the first amplifier 30.
Specifically, the first driver 100 receives a scan signal from the timing controller 300, and the scan signal is first transferred to the register 10, and then transferred to the control circuit 20 and the first amplifier 30. The control circuit 20 controls a scan off signal of the scan signal before the timing controller 300 completes an initial configuration
Through the first amplifier 30; after the timing controller 300 completes the initial configuration, the control circuit 20 controls the scan-on signal a and the scan-off signal a of the scan signals
Through the first amplifier 30. The scan signal amplified by the first amplifier 30 is transmitted to the second amplifier 40, and the second amplifier 40 processes the scan signal to improve the driving capability of the scan signal.
Since only the scan off signal is required before the timing controller 30 completes the initial configuration
By the first amplifier 30, that is, at this time, the display panel 400 of the display device is not lighted, even if the signal output of the timing controller 300 is in an unstable state, the problem that the display panel 400 of the display device flickers does not occur. After the timing controller 300 completes the initial configuration, a scan-on signal a and a scan-off signal
The display panel 400 of the display device is subjected to normal driving control of the timing controller 300 and the first driver 100 through the first amplifier 30.
According to the technical scheme of the invention, the control circuit 20 is arranged, the control circuit 20 is used for monitoring the initial configuration completion state of the time schedule controller 300, and before the time schedule controller 300 completes the initial configuration, the control circuit 20 controls the scanning closing signal of the scanning signal
Through a first amplifier 30; after the timing controller 300 completes the initial configuration, the control circuit 20 controls the scan-on signal a and the scan-off signal a of the scan signal
Through a first amplifier 30. Since only the scan-off signal is required before the timing controller 300 completes the initial configuration
By the first amplifier 30, the display panel 400 of the display device is not turned on at this time; after the timing controller 300 completes the initial configuration, a scan-on signal a and a scan-off signal
The display panel 400 of the display device is subjected to the normal driving control of the timing controller 300 and the first driver 100 through the first amplifier 30, thereby solving the problem of the display device flickering at the time of power-on.
Specifically, as shown in fig. 2, the control circuit 20 has a first signal input terminal 21, a second signal input terminal 22, a third signal input terminal 23, a fourth signal input terminal 24, a first signal output terminal 25 and a second signal output terminal 26. In order to realize that the control circuit 20 monitors the initial configuration completion state of the timing controller 300, the timing controller 300 further outputsConfiguration state signals including configuration state forward signal Ready and configuration state reverse signal
The configuration state forward signal Ready and the configuration state reverse signal
Are opposite signals.
It should be noted that the configuration state reversal signal
May be generated in the timing controller 300 or may be generated in the first driver 100. In this embodiment, as shown in fig. 2 and 3, the control circuit 20 further includes an inverting circuit F, and the timing controller 300 outputs the configuration state forward signal Ready, which forms the configuration state inverted signal through the inverting circuit F
The configuration state forward signal Ready and the configuration state reverse signal
And transmits the initial configuration information to the control circuit 20, so that the control circuit 20 monitors the initial configuration completion state of the timing controller 300.
It is to be understood that one or more of the inverting circuits F may be provided, as long as the configuration state inversion signal can be finally formed
In the present embodiment, only one inverting circuit F is provided, which can simplify the circuit.
The first signal input terminal 21 and the second signal input terminal 22 are used for inputting the scan signal, the third signal input terminal 23 and the fourth signal input terminal 24 are used for inputting the configuration status signal, and the first signal output terminal 25 and the second signal output terminal 26 are connected to the amplifier.
It should be noted that, when the scan-on signal a is input to the first signal input terminal 21, the scan-off signal is input to the second signal input terminal 22
When the first signal input terminal 21 inputs the scan-off signal
Then, the scan start signal a is input to the second signal input terminal 22. Similarly, when the configuration state forward signal Ready is input to the third signal input terminal 23, the configuration state reverse signal is input to the fourth signal input terminal 24
When the third signal input terminal 23 inputs the configuration status inversion signal
Then, the configuration state positive signal Ready is input to the fourth signal input terminal 24.
The control circuit 20 controls the signal output of the first signal output terminal 25 according to the signal input from the first signal input terminal 21 and the signal input from the third signal input terminal 23, and controls the signal output of the second signal output terminal 26 according to the signal input from the second signal input terminal 22 and the signal input from the fourth signal input terminal 24.
More specifically, as shown in fig. 3, the control circuit 20 includes an and circuit Y having a first and input terminal, a second and input terminal, and an and output terminal, and an or circuit H having a first or input terminal, a second or input terminal, and an or output terminal;
the first and gate input end forms the first signal input end, the first or gate input end forms the second signal input end, the second and gate input end forms the third signal input end, the second or gate input end forms the fourth signal input end, the and gate output end forms the first signal output end, and the or gate output end forms the second signal output end.
It should be noted that, in this embodiment, before the initial configuration is completed by the timing controller 30, the output configuration state forward signal Ready is a low level signal, after the initial configuration is completed by the timing controller 300, the output configuration state forward signal Ready is a high level signal, the configuration state forward signal Ready is input to the second and gate input terminal, and the configuration state reverse signal is input to the second or gate input terminal
It is understood that, in other embodiments, the configuration state forward signal Ready output by the timing controller 300 before the initial configuration is completed may be a high level signal, the configuration state forward signal Ready output by the timing controller 300 after the initial configuration is completed is a low level signal, and the configuration state reverse signal is input to the second and gate input terminal
The second OR gate input end inputs the configuration state positive signal Ready.
The AND gate Y and the OR gate H are both basic logic gates in an integrated circuit, and the process for manufacturing the AND gate Y and the OR gate H on a semiconductor is mature, simple and easy to implement.
It is understood that one or more of the and circuit Y and the or circuit H may be provided, as long as the functions of the control circuit 20 in the present invention can be realized. In this embodiment, the and circuit Y and the or circuit H are respectively provided one for simplifying the circuit.
Further, in the present embodiment, as shown in fig. 3, the first amplifier 30 specifically includes a first P-type field effect transistor M1, a second P-type field effect transistor M2, a third P-type field effect transistor M5, a fourth P-type field effect transistor M6, a first N-type field effect transistor M3, a second N-type field effect transistor M4, a third N-type field effect transistor M7, and a fourth N-type field effect transistor M8; the input ends of the first P-type field effect transistor M1 and the second P-type field effect transistor M2 are electrically connected to form a first power input end 32; the input ends of the third P-type field effect transistor M5 and the fourth P-type field effect transistor M6 are electrically connected to form a second power input end 33; the input terminals of the first N-type field effect transistor M3, the second N-type field effect transistor M4, the third N-type field effect transistor M7 and the fourth N-type field effect transistor M8 are electrically connected and form a third power input terminal 31; the output end of the first P-type field effect transistor M1 is electrically connected with the controlled ends of the second N-type field effect transistor M4 and the fourth N-type field effect transistor M8, and the output end of the second P-type field effect transistor M2 is electrically connected with the controlled ends of the first N-type field effect transistor M3 and the third N-type field effect transistor M7; the output end of the third P-type field effect transistor M5 is electrically connected with the controlled end of the fourth P-type field effect transistor M6 and the output end of the third N-type field effect transistor M7; an output terminal of the fourth P-type field effect transistor M6 is electrically connected to the controlled terminal of the third P-type field effect transistor M5 and the output terminal of the fourth N-type field effect transistor M8 to form a scan signal output terminal OUT; the first signal output end is electrically connected with the controlled end of the first P-type field effect transistor M1, and the second signal output end is electrically connected with the controlled end of the second P-type field effect transistor M2.
The first Power input end 32, the second Power input end 33, and the third Power input end 31 are electrically connected to a Power Management Integrated Circuit (PMIC), the first Power input end 32 is used for inputting a VDD level, the second Power input end 33 is used for inputting a VGH level, and the third Power input end 31 is used for inputting a VGL level. Wherein the VGH level is higher than a level of the scan-on signal A, and the VGL level is lower than a level of the scan-off signal A.
In this embodiment, before the timing controller 300 completes the initial configuration, since the second and gate input terminal always inputs a low level signal, the and gate output terminal always outputs a low level signal no matter the first and gate input terminal inputs the scan on signal a or the scan off signal a, and since the second or gate input terminal always inputs a high level signal, the or gate output terminal always outputs a high level signal no matter the first or gate input terminal inputs the scan on signal or the scan off signal. After the low level signal output by the and gate output terminal and the high level signal output by the or gate output terminal are input to the first amplifier 30, the level output by the scanning signal output terminal OUT of the first amplifier 30 is the scanning signal of VGL level, and at this time, the source and the drain of the thin film transistor are disconnected, and the display panel 400 of the display device is not lighted. After the timing controller 300 completes the initial configuration, since the second and gate input terminal always inputs a high level signal, the level of the signal output by the and gate output terminal depends on the signal input by the first and gate input terminal, since the second or gate input terminal always inputs a high level signal, the level of the signal output by the or gate output terminal depends on the signal input by the first or gate input terminal, and after the scan start signal a passes through the control circuit 20 and the first amplifier 30, the level thereof becomes VGH level; after the scan off signal a passes through the control circuit 20 and the first amplifier 30, its level becomes VGL level. The display panel 400 of the display device is subjected to normal driving control by the timing controller 300 and the first driver 100.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (8)
1. A driver for a display device, the driver comprising:
the display device comprises a first amplifier, a second amplifier and a control circuit, wherein the first amplifier is used for receiving scanning signals from a time sequence controller of the display device and amplifying the scanning signals, and the scanning signals comprise scanning starting signals and scanning stopping signals;
the control circuit is used for monitoring the initial configuration completion state of the time schedule controller, and before the time schedule controller completes the initial configuration, the control circuit controls the scanning closing signal of the scanning signal to pass through the first amplifier; after the time schedule controller finishes the initial configuration, the control circuit controls the scanning starting signal and the scanning closing signal of the scanning signal to pass through the first amplifier;
the control circuit is provided with a first signal input end, a second signal input end, a third signal input end, a fourth signal input end, a first signal output end and a second signal output end, and the time schedule controller also outputs a configuration state signal; the first signal input end and the second signal input end are used for inputting the scanning signals; the third signal input terminal and the fourth signal input terminal are used for inputting the configuration state signal; the first signal output end and the second signal output end are connected with the first amplifier; the control circuit controls the signal output of the first signal output end according to the signal input by the first signal input end and the signal input by the third signal input end, and controls the signal output of the second signal output end according to the signal input by the second signal input end and the signal input by the fourth signal input end;
the first amplifier comprises a first P-type field effect transistor, a second P-type field effect transistor, a third P-type field effect transistor, a fourth P-type field effect transistor, a first N-type field effect transistor, a second N-type field effect transistor, a third N-type field effect transistor and a fourth N-type field effect transistor; the input ends of the first P-type field effect transistor and the second P-type field effect transistor are electrically connected and form a first power supply input end; the input ends of the third P-type field effect transistor and the fourth P-type field effect transistor are electrically connected and form a second power supply input end; the input ends of the first N-type field effect transistor, the second N-type field effect transistor, the third N-type field effect transistor and the fourth N-type field effect transistor are electrically connected and form a third power supply input end; the output end of the first P-type field effect transistor is electrically connected with the controlled ends of the second N-type field effect transistor and the fourth N-type field effect transistor, and the output end of the second P-type field effect transistor is electrically connected with the controlled ends of the first N-type field effect transistor and the third N-type field effect transistor; the output end of the third P-type field effect transistor is electrically connected with the controlled end of the fourth P-type field effect transistor and the output end of the third N-type field effect transistor; the output end of the fourth P-type field effect transistor is electrically connected with the controlled end of the third P-type field effect transistor and the output end of the fourth N-type field effect transistor to form a scanning signal output end; the first signal output end is electrically connected with the controlled end of the first P-type field effect transistor, and the second signal output end is electrically connected with the controlled end of the second P-type field effect transistor.
2. The driver of claim 1, wherein the control circuit comprises an AND gate circuit having a first AND gate input, a second AND gate input, and an AND gate output, and an OR gate circuit having a first OR gate input, a second OR gate input, and an OR gate output;
the first and gate input end forms the first signal input end, the first or gate input end forms the second signal input end, the second and gate input end forms the third signal input end, the second or gate input end forms the fourth signal input end, the and gate output end forms the first signal output end, and the or gate output end forms the second signal output end.
3. The driver of claim 2, wherein the control circuit further comprises an inversion circuit, the configuration state signals comprise configuration state forward signals and configuration state inversion signals, and the timing controller outputs the configuration state forward signals, the configuration state forward signals passing through the inversion circuit to form the configuration state inversion signals.
4. The driver of claim 1, further comprising a register, wherein the scan signal passes through the register before being passed to the control circuit.
5. A driver for a display device, the driver comprising:
the display device comprises a first amplifier, a second amplifier and a control circuit, wherein the first amplifier is used for receiving scanning signals from a time sequence controller of the display device and amplifying the scanning signals, and the scanning signals comprise scanning starting signals and scanning stopping signals;
the second amplifier is used for receiving the scanning signal from the first amplifier, amplifying the scanning signal and outputting the scanning signal;
the control circuit is used for monitoring the initial configuration completion state of the time schedule controller, and before the time schedule controller completes the initial configuration, the control circuit controls the scanning closing signal of the scanning signal to pass through the first amplifier; after the time schedule controller finishes the initial configuration, the control circuit controls the scanning starting signal and the scanning closing signal of the scanning signal to pass through the first amplifier;
the register receives a scanning signal from a time sequence controller of the display device, is used for adjusting the output direction of the scanning signal and then transmits the scanning signal to the control circuit;
the control circuit is provided with a first signal input end, a second signal input end, a third signal input end, a fourth signal input end, a first signal output end and a second signal output end, and the time schedule controller also outputs a configuration state signal; the first signal input end and the second signal input end are used for inputting the scanning signals; the third signal input terminal and the fourth signal input terminal are used for inputting the configuration state signal; the first signal output end and the second signal output end are connected with the first amplifier; the control circuit controls the signal output of the first signal output end according to the signal input by the first signal input end and the signal input by the third signal input end, and controls the signal output of the second signal output end according to the signal input by the second signal input end and the signal input by the fourth signal input end;
the first amplifier comprises a first P-type field effect transistor, a second P-type field effect transistor, a third P-type field effect transistor, a fourth P-type field effect transistor, a first N-type field effect transistor, a second N-type field effect transistor, a third N-type field effect transistor and a fourth N-type field effect transistor; the input ends of the first P-type field effect transistor and the second P-type field effect transistor are electrically connected and form a first power supply input end; the input ends of the third P-type field effect transistor and the fourth P-type field effect transistor are electrically connected and form a second power supply input end; the input ends of the first N-type field effect transistor, the second N-type field effect transistor, the third N-type field effect transistor and the fourth N-type field effect transistor are electrically connected and form a third power supply input end; the output end of the first P-type field effect transistor is electrically connected with the controlled ends of the second N-type field effect transistor and the fourth N-type field effect transistor, and the output end of the second P-type field effect transistor is electrically connected with the controlled ends of the first N-type field effect transistor and the third N-type field effect transistor; the output end of the third P-type field effect transistor is electrically connected with the controlled end of the fourth P-type field effect transistor and the output end of the third N-type field effect transistor; the output end of the fourth P-type field effect transistor is electrically connected with the controlled end of the third P-type field effect transistor and the output end of the fourth N-type field effect transistor to form a scanning signal output end; the first signal output end is electrically connected with the controlled end of the first P-type field effect transistor, and the second signal output end is electrically connected with the controlled end of the second P-type field effect transistor.
6. A display device is characterized by comprising
A first driver being a driver as claimed in any one of claims 1 to 5;
a second driver;
the time schedule controller is electrically connected with the first driver and the second driver;
and the scanning line of the display panel is electrically connected with the first driver, and the data line of the display panel is electrically connected with the second driver.
7. The display device according to claim 6, wherein the timing controller further outputs a configuration state forward signal, which is a low level signal before the initial configuration is completed; after the time sequence controller completes the initial configuration, the configuration state forward signal is a high level signal.
8. The display device according to claim 6, wherein the timing controller comprises a signal reading module, a signal processing module and a signal output module, the signal reading module receives and reads signals from the outside and transmits the signals to the signal processing module, and the signals are converted by the signal processing module and then output by the signal output module.
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| CN110264971B (en) * | 2019-06-26 | 2022-01-04 | 京东方科技集团股份有限公司 | Anti-flash screen circuit and method, driving circuit and display device |
| CN114038434B (en) * | 2021-11-09 | 2023-03-07 | 深圳创维－Rgb电子有限公司 | Power sequence control circuit and method for liquid crystal panel, liquid crystal panel and display device |
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