CN109408260A - Error bit number estimation method, device, computer equipment and storage medium - Google Patents
Error bit number estimation method, device, computer equipment and storage medium Download PDFInfo
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- CN109408260A CN109408260A CN201811119377.3A CN201811119377A CN109408260A CN 109408260 A CN109408260 A CN 109408260A CN 201811119377 A CN201811119377 A CN 201811119377A CN 109408260 A CN109408260 A CN 109408260A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/079—Root cause analysis, i.e. error or fault diagnosis
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
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Abstract
The present invention relates to error bit number estimation method, device, computer equipment and storage medium, this method include count set interval in test errors number of bits and it is corresponding test be unsatisfactory for syndrome number；Initial model is established according to statistical result；Initial model is fitted, object module is formed；Syndrome number is actually unsatisfactory for the code word calculating of input decoder when in use；It using object module and is actually unsatisfactory for syndrome number and estimates factual error number of bits.The present invention by set interval test errors number of bits and corresponding test be unsatisfactory for syndrome number and count, obtain the object module in different sections, in actual use, factual error number of bits is estimated according to the object module for being actually unsatisfactory for the fallen into section of syndrome number, it effectively carries out the selection of decoding mode or directly carries out reading to retry next time, whole decoding efficiency can be improved in the number for reducing unnecessary decoding iteration and retrying.
Description
Technical field
The present invention relates to solid state hard disks, more specifically refer to error bit number estimation method, device, computer equipment
And storage medium.
Background technique
Solid state hard disk is easy to produce the disadvantage of reading and writing data mistake due to it, the corrupt data after erasable number is more
Probability significantly increases, therefore is highly desirable to error correction algorithm guarantee, for example, solid state hard disk goes verification to change using ECC algorithm needs
Error in data, and judge whether bad block, error bit number is accurately estimated, for estimating that the quality of channel circumstance has weight
The meaning wanted, but the error correcting capability of error correction algorithm is substantially fixed, and there is presently no more appropriate algorithms can be quasi-
Really estimate the error bit number of the code word before entering ldpc decoder, and then number of retries can not be reduced, so that decoding
Inefficiency,
Therefore, it is necessary to design a kind of method, the number for reducing and retrying is realized, improve decoding efficiency.
Summary of the invention
It is an object of the invention to overcome the deficiencies of existing technologies, error bit number estimation method, device, calculating are provided
Machine equipment and storage medium.
To achieve the above object, the invention adopts the following technical scheme: error bit number estimation method, comprising:
Test errors number of bits and corresponding test in statistics set interval are unsatisfactory for syndrome number；
Initial model is established according to statistical result；
Initial model is fitted, object module is formed；
Syndrome number is actually unsatisfactory for the code word calculating of input decoder when in use；
It using object module and is actually unsatisfactory for syndrome number and estimates factual error number of bits.
Its further technical solution are as follows: test errors number of bits and corresponding test in the statistics set interval
It is unsatisfactory for syndrome number, comprising:
Obtain initial data；
Initial data is encoded, test codeword is obtained；
Set section, step-length and the maximum statistics number of the test errors number of bits injected at random；
Corresponding test errors number of bits is generated using random number；
Test codeword is added in test errors number of bits；
Test, which is calculated, according to test codeword is unsatisfactory for syndrome number；
The corresponding test of record test errors number of bits is unsatisfactory for syndrome number；
Judge to record whether number reaches maximum statistics number；
If it is not, then returning to the utilization random number generates corresponding test errors bit step；
If so, resetting the test errors number of bits of injection according to step-length；
Judge whether the test errors number of bits of injection reaches the maximum value in section；
If so, into it is described according to test errors number of bits and it is corresponding test be unsatisfactory for syndrome number establish
Initial model step；
If it is not, then returning to the utilization random number generates corresponding test errors bit step.
Its further technical solution are as follows: described that initial model is established according to statistical result, comprising:
The corresponding test syndrome number of same test errors number of bits is averaged, to form object identifier
Number；
According to the section of test errors number of bits and the sub- number of corresponding object identifier, relation curve is obtained, to obtain
Initial model.
Its further technical solution are as follows: it is described that initial model is fitted, form object module, comprising:
Threshold interval division is carried out to the sub- number of object identifier according to relation curve；
Piecewise fitting is carried out using minimum variance according to division result and fitting formula, determines impact factor and offset
Value；
Object module is determined according to impact factor and deviant.
Its further technical solution are as follows: the fitting formula includes: sμ(x)=ax+b；Wherein, a > 0, b > 0；A is
Ratio impact factor, b are deviant.
Its further technical solution are as follows: described to utilize object module and be actually unsatisfactory for syndrome number estimation factual error
Number of bits, comprising:
Obtain the practical section being actually unsatisfactory for where syndrome number；
Using the object module in practical section, factual error number of bits is estimated according to syndrome number is actually unsatisfactory for.
The present invention also provides error bit number estimation devices, comprising:
Statistic unit is unsatisfactory for verifying for counting test errors number of bits in set interval and corresponding test
Sub- number；
Initial model establishes unit, for establishing initial model according to statistical result；
Fitting unit forms object module for being fitted to initial model；
Actual number computing unit is actually unsatisfactory for syndrome for the code word calculating when in use to input decoder
Number；
Number of bits evaluation unit estimates factual error ratio for using object module and being actually unsatisfactory for syndrome number
Special number.
Its further technical solution are as follows: the statistic unit includes:
Data acquisition module, for obtaining initial data；
Coding module obtains test codeword for encoding to initial data；
Setting module, for setting section, step-length and the maximum statistics time of the test errors number of bits injected at random
Number；
Random generating module, for generating corresponding test errors number of bits using random number；
Module is added, for test codeword to be added in test errors number of bits；
Computing module is unsatisfactory for syndrome number for calculating test according to test codeword；
Logging modle, for recording the corresponding test syndrome number of test errors number of bits；
Number judgment module records whether number reaches maximum statistics number for judging；
Step size settings module, for if so, resetting the test errors number of bits of injection according to step-length；
Interval judgement module, for judging whether the test errors number of bits of injection reaches the maximum value in section.
The present invention also provides a kind of computer equipment, the computer equipment includes memory and processor, described to deposit
Computer program is stored on reservoir, the processor realizes above-mentioned method when executing the computer program.
The present invention also provides a kind of storage medium, the storage medium is stored with computer program, the computer journey
Sequence can realize above-mentioned method when being executed by processor.
Compared with the prior art, the invention has the advantages that: the present invention passes through to the test errors bit in set interval
Number and corresponding test are unsatisfactory for syndrome number and are counted, and establish initial model according to statistical result, to initial
Model is fitted, and to obtain the object module in different sections, in actual use, is first carried out to the code word before decoding
It is actually unsatisfactory for the calculating of syndrome number, is estimated according to the object module for being actually unsatisfactory for the fallen into section of syndrome number real
Border error bit number effectively carries out the selection of decoding mode or directly carries out reading to retry next time, reduces unnecessary translate
Code iteration and the number retried, can be improved whole decoding efficiency.
The invention will be further described in the following with reference to the drawings and specific embodiments.
Detailed description of the invention
Technical solution in order to illustrate the embodiments of the present invention more clearly, below will be to needed in embodiment description
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the flow diagram of error bit number estimation method provided in an embodiment of the present invention；
Fig. 2 is the sub-process schematic diagram of error bit number estimation method provided in an embodiment of the present invention；
Fig. 3 is the sub-process schematic diagram of error bit number estimation method provided in an embodiment of the present invention；
Fig. 4 is the sub-process schematic diagram of error bit number estimation method provided in an embodiment of the present invention；
Fig. 5 is the sub-process schematic diagram of error bit number estimation method provided in an embodiment of the present invention；
Fig. 6 is the result schematic diagram that all 4 bit-errors provided in an embodiment of the present invention fall into 8 rings；
Fig. 7 is the result schematic diagram that all 4 bit-errors provided in an embodiment of the present invention fall into 10 rings；
Fig. 8 is the result schematic diagram that all 4 bit-errors provided in an embodiment of the present invention fall into 12 rings and 14 rings；
Fig. 9 is all 4 bit-errors provided in an embodiment of the present invention mutually without the result schematic diagram of sideline connection；
Figure 10 is the fitting pass of codeword error number of bits provided in an embodiment of the present invention and ungratified syndrome number
It is schematic diagram；
Figure 11 is the schematic block diagram of error bit number estimation device provided in an embodiment of the present invention；
Figure 12 is the schematic block diagram of computer equipment provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are some of the embodiments of the present invention, instead of all the embodiments.Based on this hair
Embodiment in bright, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, shall fall within the protection scope of the present invention.
It should be appreciated that ought use in this specification and in the appended claims, term " includes " and "comprising" instruction
Described feature, entirety, step, operation, the presence of element and/or component, but one or more of the other feature, whole is not precluded
Body, step, operation, the presence or addition of element, component and/or its set.
It is also understood that mesh of the term used in this description of the invention merely for the sake of description specific embodiment
And be not intended to limit the present invention.As description of the invention and it is used in the attached claims, unless on
Other situations are hereafter clearly indicated, otherwise " one " of singular, "one" and "the" are intended to include plural form.
It will be further appreciated that the term "and/or" used in description of the invention and the appended claims is
Refer to any combination and all possible combinations of one or more of associated item listed, and including these combinations.
Referring to Fig. 1, Fig. 1 is the flow diagram of error bit number estimation method provided in an embodiment of the present invention.It should
Error bit number estimation method can operate in the solid state hard disk of the ECC algorithm comprising LDPC, with the decoding to solid state hard disk
Correcting data error is carried out before device work, realizes the number for reducing and retrying, improves decoding efficiency.
As shown in Figure 1, this approach includes the following steps S110 to S150.
S110, the test errors number of bits in statistics set interval and corresponding test are unsatisfactory for syndrome number.
In the present embodiment, test errors number of bits is referred in test to establish the test number used in model process
According to the test errors amount of bits of generation；Test is unsatisfactory for syndrome number and refers to produced by testing to establish in model process
Be unsatisfactory for syndrome number.
Since test errors number of bits and corresponding test are unsatisfactory for syndrome number there are certain linear relationship, because
This is modeled further according to statistical result by counting to the two numerical value, helps to estimate into ldpc decoder
The error bit number of code word before can effectively carry out the selection of decoding mode or directly carry out reading to retry behaviour next time
Make, unnecessary decoding iteration can be greatly reduced in this way, whole decoding efficiency can be improved.Error bit number is also one
A important parameter in the biggish situation that malfunctions, can carry out optimal in advance by taking solid state hard disk memory read data as an example
The adjustment of offset voltage is read, more accurately reads data to obtain.
In one embodiment, as shown in Fig. 2, above-mentioned step S110 may include step S110a~S110j.
S110a, initial data is obtained；
In the present embodiment, initial data refers to the test data of write-in solid state hard disk.
S110b, initial data is encoded, obtains test codeword.
Test codeword refers to before solid state hard disk is written, and is encoded formed after error correction to initial data
Code word.In the present embodiment, specifically initial data is encoded using LDPC encoder, LDPC (low-density checksum
Code, Low Density Parity Check Code) linear block codes with sparse check matrix, not only approach
The superperformance of Shannon limit, and decoding complexity is lower, flexible structure, and has excellent error-correcting performance.
Section, step-length and the maximum statistics number for the test errors number of bits that S110c, setting are injected at random.
When acquisition test is unsatisfactory for syndrome number, and in the section of different test errors number of bits, test
Error bit number, which is unsatisfactory for the Relation Parameters of syndrome number with test, to change, it is necessary to set several with
It the section of the test errors number of bits of machine injection will be for the institute in section when acquisition test is unsatisfactory for syndrome number
There is test errors number of bits to carry out acquisition test and be unsatisfactory for syndrome number, most preferably, to be repeated as many times and obtain, to improve
Accuracy rate, it is necessary to set maximum statistics number.
When acquisition test is unsatisfactory for syndrome number, it is also necessary to increase of test errors bit according to the step-length of setting
Number obtains the process that test is unsatisfactory for syndrome number to complete the test errors number of bits in entire section.
S110d, corresponding test errors number of bits is generated using random number.
The test errors number of bits generated by the way of random number could improve acquisition accuracy rate.
S110e, test codeword is added in test errors number of bits.
S110f, syndrome number is unsatisfactory for according to test codeword calculating test.
In the present embodiment, S=Hm is utilizedTCarry out syndrome computation, wherein m represents test codeword, and H represents LDPC
The check matrix that error correcting code uses, is a kind of linear block codes matrix, for calculating syndrome.
The corresponding test of S110g, record test errors number of bits is unsatisfactory for syndrome number；
Test is unsatisfactory for syndrome number record, in order to subsequent processing.
S110h, judge to record whether number reaches maximum statistics number.
Same test errors number of bits is carried out repeatedly obtaining to test to be unsatisfactory for syndrome number, to improve accuracy rate,
Reduce error
If it is not, then return step S110d；
If so, S110i, the test errors number of bits injected according to step-length reset.
After carrying out maximum statistics number acquisition test to same test errors number of bits and being unsatisfactory for syndrome number, need
Above-mentioned process is carried out for next test errors number of bits, therefore, it is necessary to increase test errors according to the step-length of setting
Number of bits is counted with same process, until the test errors number of bits currently injected reaches the maximum value in section.
S110j, judge whether the test errors number of bits of injection reaches the maximum value in section；
It is unsatisfactory for syndrome number to obtain the corresponding test of several test errors number of bits in set interval, it will be upper
The content of record is stated as statistical result.
If so, entering step S120；
If it is not, then return step S110d.
S120, initial model is established according to statistical result.
In the present embodiment, statistical result refers to test errors number of bits in the set interval of statistics and corresponding
Test is unsatisfactory for syndrome number；Initial model has referred to that several test errors number of bits and corresponding test are discontented
The curve graph that sufficient syndrome number is formed.
In one embodiment, as shown in figure 3, above-mentioned step S120 may include step S121~S122.
S121, the corresponding test syndrome number of same test errors number of bits is averaged, to form target school
Test sub- number；
One, which is obtained, from multiple test syndrome numbers in a manner of being averaged represents the test errors number of bits pair
The test syndrome number answered can make the accuracy rate for improving initial model.
S122, the section according to test errors number of bits and the sub- number of corresponding object identifier obtain relation curve, with
Obtain initial model.
In the present embodiment, can be drawn using the tools such as matlab test errors number of bits section and corresponding mesh
Mark the relation curve of syndrome number.
S130, initial model is fitted, forms object module.
In the present embodiment, object module, which refers to, carries out curve fitting for initial model with the curve of formation.
In one embodiment, as shown in figure 4, above-mentioned step S130 may include step S131~S133.
S131, threshold interval division is carried out to the sub- number of object identifier according to relation curve.
Since in different sections, the relationship between error bit number and the sub- number of object identifier can be different, therefore, need
Threshold interval division is carried out to the sub- number of object identifier, to obtain error bit number and object identifier in each section
Relationship between number, to improve the accuracy rate of error bit number estimation.
S132, piecewise fitting is carried out using minimum variance according to division result and fitting formula, determine impact factor and
Deviant.
In the present embodiment, the fitting formula includes: sμ(x)=ax+b, wherein a > 0, b > 0；A is ratio shadow
The factor is rung, b is deviant.
Different fragmentation thresholds is set to ungratified syndrome according to curve, and the point in each section is calculated using minimum variance
Method is fitted, and determines the impact factor and deviant of each piecewise interval.
S133, object module is determined according to impact factor and deviant.
When the impact factor and deviant for determining each piecewise interval, then s can be usedμ(x)=ax+b formula is true
The relationship of error bit number and ungratified syndrome is determined, so that it is determined that object module.
S140, syndrome number is actually unsatisfactory for the code word calculating of input decoder when in use.
Syndrome number is first actually unsatisfactory for the code word of input decoder to calculate, and specifically uses S=HmTMeter
It calculates.
S150, using object module and actually it is unsatisfactory for syndrome number estimation factual error number of bits.
In one embodiment, above-mentioned step S150 may include step S151~S152.
S151, acquisition are actually unsatisfactory for the practical section where syndrome number；
S152, using the object module in practical section, according to being actually unsatisfactory for syndrome number estimation factual error bit
Number.
Determine that being actually unsatisfactory for syndrome number determines which section it falls into, it is true according to syndrome number is actually unsatisfactory for
Surely the corresponding object module s in the section fallen intoμ(x)=ax+b, input are actually unsatisfactory for syndrome number sμ(x), to practical mistake
Errored bit number is estimated, can effectively avoid can not entangling in the case where there are many error bit number into decoder
The waste of bandwidth caused by and, to improve decoding efficiency, which is applied equally to the code word error of irregular QC-LDPC
Erroneous estimation.
Give one example: by taking the regular QC-LDPC of PEG algorithm construction verifies battle array as an example, such verification battle array is having the same
Column weight, since LDPC code can be usually indicated with bipartite graph than sparse grouping liner code, as G=(V=L ∪ R,
E), L indicates the set of all variable nodes, and R indicates the set of all check-nodes, E indicate variable node and check-node it
Between line.Assuming that the column weight of LDPC verification battle array is l=4 to verify in battle array one of error pattern, i.e. divide for 8 rings
Analysis, as shown in fig. 6, black box indicates that verification battle array verification calculates ungratified check-node, white box indicates the school met
Node is tested, black circles indicate that the variable node of mistake occurs, each variable node connects 4 check-nodes, intermediate 4 schools
The variable node of node connection even number mistake is tested, therefore syndrome meets, so ungratified syndrome number is 8, this is
A kind of special case, in the case where only 4 bit-errors, the probability for just entirely falling in 8 rings in LDPC verification battle array is extremely low,
Because it is longer and sparse to verify horizontal and vertical parity check code.
Certainly, LDPC verifies more than a kind of error pattern of 8 ring in battle array, as shown in Figure 7, it is assumed that all 4 bit-errors are fallen into
The error pattern of 10 rings can then have more two syndromes and be unsatisfactory for.It is same as shown in figure 8, respectively falling in 12 rings and 14 rings
Error pattern has more two and four ungratified syndromes respectively.In the case where LDPC code word only has 4 bit errors, very
4 error bits of maximum probability malfunction at random does not have any sideline connection, and result is as shown in Figure 9.Therefore deduce that for
There is random wrong situation in LDPC code word, falls into different error patterns, and the syndrome being calculated is different, but
Within certain interval range, theoretically count the number of all rings, calculate fall into the probability of ring can be according to verification
The number of son estimation error bit, the relationship of syndrome and error bit number is simulated by the method for statistics.Due to from primary
N errors present of injection at random, to determine that the relationship for being unsatisfactory for syndrome number and error bit number does not have generality,
It is different under different error patterns, it is therefore desirable to the characteristics of analyzing from the statistical significance, battle array verified according to LDPC, from system
Every mistake for increasing by 1 bit, that is, increase a step-length for meter analysis is upper, and ungratified check-node should also will increase.It is false
If the error bit number injected at random is indicated with x, and ungratified syndrome number can use sμ(x) it indicates, it can be to sμ
(x) it is fitted, it may be assumed that sμ(x)=ax+b；Wherein, a > 0, b > 0；A is ratio impact factor, and b is deviant.
When error bit number is less, due to the sparsity of code word itself, as shown in Figure 10, therefore a≤l, work as a=l
When, b=0；As error bit number increases, the same check-node is likely to occur the mistake of more bits, thus influence because
Sub- a can become smaller.By the way that threshold value is arranged to the ungratified syndrome number in different sections, so that piecewise fitting is carried out, to obtain more
High accuracy.Its rough Function Fitting situation is as shown in figure 11, verifies battle array for specific LDPC, each section in curve
Impact factor a and deviant b can be obtained by statistics.Pass through the ungratified number difference of the syndrome actually calculated
With three threshold value Tu1, Tu2, Tu3It being compared, which section determination falls into, so that it is determined that a and b, then estimate code word error
Error bit number: x=(sμ(x)-b)/a。
The case where verifying battle array by the QC-LDPC that PEG construction column are fixed again, this estimation method can equally be well applied to not advise
LDPC then verifies the case where battle array, as long as the distribution of column weight is generally uniform, can use the mode of statistics equally to obtain correspondence
Impact factor and deviant, and result is not in too big fluctuation.It, can also be with if column weight distribution is absolutely not regular
The precision of fitting is improved by dividing some sections, so as to estimate more accurate error bit number more.To realize
The number of codeword error bit is estimated by section that ungratified syndrome number is fallen into.
Occur the number of bits of mistake before entering decoder based on LDPC linear block codes estimation code word, passes through code word
The verification sub-information calculated with check matrix the characteristics of verifying battle array according to LDPC, is led to using ungratified syndrome number
It crosses and different threshold values is arranged to ungratified syndrome number to estimate the error bit number of code word, for estimating channel circumstance
Quality have great importance, be also provided to one important reference factor of ldpc decoder, it is more suitable so as to select
Decoded mode, improve decoding efficiency.The characteristics of by verifying battle array to LDPC, carries out corresponding modeling analysis, in different error feelings
Influence of the error bit number to syndrome under condition, to determine the impact factor in different wrong sections, to estimate code word
The number of error can obtain under different error patterns, the number of ungratified syndrome and actual error bit
There are a reasonable proportionate relationships for number, and different threshold values, which is arranged, to ungratified syndrome number can obtain different sections
Impact factor and deviant, so as to estimate the number of codeword error bit, and so on, other different verification battle arrays
It can estimate the error bit number of code word error.
The error correcting capability of error correction algorithm is substantially fixed, therefore can be estimated by certain method before decoding error correction
The number of bits substantially to malfunction is counted out, so that suitable mode be selected to be decoded, the number retried can be greatly reduced in this way,
Improve decoding efficiency.
Above-mentioned error bit number estimation method, by the test errors number of bits and correspondence in set interval
Test be unsatisfactory for syndrome number and counted, and initial model is established according to statistical result, initial model is fitted,
It is in actual use, first practical to the code word before decoding to be unsatisfactory for school to obtain the object module in different sections
The calculating for testing sub- number estimates factual error bit according to the object module for being actually unsatisfactory for the fallen into section of syndrome number
Number effectively carries out the selection of decoding mode or directly carries out reading to retry next time, reduces unnecessary decoding iteration and retry
Number, whole decoding efficiency can be improved.
Figure 11 is a kind of schematic block diagram of error bit number estimation device 300 provided in an embodiment of the present invention.Such as figure
Shown in 11, correspond to the above error bit number estimation method, the present invention also provides a kind of error bit number estimation devices
300.The error bit number estimation device 300 includes the unit for executing above-mentioned error bit number estimation method, the dress
Setting can be configured in the solid state hard disk of the ECC algorithm comprising LDPC.
Specifically, Figure 11 is please referred to, which includes:
Statistic unit 301 is unsatisfactory for for counting test errors number of bits in set interval and corresponding test
Syndrome number；
Initial model establishes unit 302, for establishing initial model according to statistical result；
Fitting unit 303 forms object module for being fitted to initial model；
Actual number computing unit 304 is actually unsatisfactory for verifying for the code word calculating when in use to input decoder
Sub- number；
Number of bits evaluation unit 305 estimates practical mistake for using object module and being actually unsatisfactory for syndrome number
Errored bit number.
In one embodiment, the statistic unit 301 includes:
Data acquisition module, for obtaining initial data；
Coding module obtains test codeword for encoding to initial data；
Setting module, for setting section, step-length and the maximum statistics time of the test errors number of bits injected at random
Number；
Random generating module, for generating corresponding test errors number of bits using random number；
Module is added, for test codeword to be added in test errors number of bits；
Computing module is unsatisfactory for syndrome number for calculating test according to test codeword；
Logging modle, for recording the corresponding test syndrome number of test errors number of bits；
Number judgment module records whether number reaches maximum statistics number for judging；
Step size settings module, for if so, resetting the test errors number of bits of injection according to step-length；
Interval judgement module, for judging whether the test errors number of bits of injection reaches the maximum value in section.
In one embodiment, the initial model establishes unit 302 and includes:
Average value obtains module, for being averaged to the corresponding test syndrome number of same test errors number of bits
Value, to form the sub- number of object identifier；
Relation curve module, for according to test errors number of bits section and the sub- number of corresponding object identifier, obtain
Relation curve is taken, to obtain initial model.
In one embodiment, the fitting unit 303 includes:
Division module, for carrying out threshold interval division to the sub- number of object identifier according to relation curve；
Parameter determination module, for carrying out piecewise fitting using minimum variance according to division result and fitting formula, really
Determine impact factor and deviant；
Object module determining module, for determining object module according to impact factor and deviant.
In one embodiment, the number of bits evaluation unit 305 includes:
Practical section obtains module, for obtaining the practical section where being actually unsatisfactory for syndrome number；
Number estimation module is estimated for the object module using practical section according to syndrome number is actually unsatisfactory for
Factual error number of bits.
It should be noted that it is apparent to those skilled in the art that, above-mentioned error bit number estimation
The specific implementation process of device 300 and each unit, can be with reference to the corresponding description in preceding method embodiment, for the side of description
Just and succinctly, details are not described herein.
Above-mentioned error bit number estimation device 300 can be implemented as a kind of form of computer program, the computer journey
Sequence can be run in computer equipment as shown in figure 12.
Figure 12 is please referred to, Figure 12 is a kind of schematic block diagram of computer equipment provided by the embodiments of the present application.The calculating
Machine equipment 500 is the server in the solid state hard disk with the ECC algorithm comprising LDPC.
Refering to fig. 12, which includes processor 502, memory and the net connected by system bus 501
Network interface 505, wherein memory may include non-volatile memory medium 503 and built-in storage 504.
The non-volatile memory medium 503 can storage program area 5031 and computer program 5032.The computer program
5032 include program instruction, which is performed, and processor 502 may make to execute a kind of error bit number estimation side
Method.
The processor 502 is for providing calculating and control ability, to support the operation of entire computer equipment 500.
The built-in storage 504 provides environment for the operation of the computer program 5032 in non-volatile memory medium 503, should
When computer program 5032 is executed by processor 502, processor 502 may make to execute a kind of error bit number estimation method.
The network interface 505 is used to carry out network communication with other equipment.It will be understood by those skilled in the art that in Figure 12
The structure shown, only the block diagram of part-structure relevant to application scheme, does not constitute and is applied to application scheme
The restriction of computer equipment 500 thereon, specific computer equipment 500 may include more more or fewer than as shown in the figure
Component perhaps combines certain components or with different component layouts.
Wherein, the processor 502 is for running computer program 5032 stored in memory, to realize following step
It is rapid:
Test errors number of bits and corresponding test in statistics set interval are unsatisfactory for syndrome number；
Initial model is established according to statistical result；
Initial model is fitted, object module is formed；
Syndrome number is actually unsatisfactory for the code word calculating of input decoder when in use；
It using object module and is actually unsatisfactory for syndrome number and estimates factual error number of bits.
In one embodiment, processor 502 realize it is described statistics set interval in test errors number of bits and
When corresponding test is unsatisfactory for syndrome number step, it is implemented as follows step:
Obtain initial data；
Initial data is encoded, test codeword is obtained；
Set section, step-length and the maximum statistics number of the test errors number of bits injected at random；
Corresponding test errors number of bits is generated using random number；
Test codeword is added in test errors number of bits；
Test, which is calculated, according to test codeword is unsatisfactory for syndrome number；
The corresponding test of record test errors number of bits is unsatisfactory for syndrome number；
Judge to record whether number reaches maximum statistics number；
If it is not, then returning to the utilization random number generates corresponding test errors bit step；
If so, resetting the test errors number of bits of injection according to step-length；
Judge whether the test errors number of bits of injection reaches the maximum value in section；
If so, into it is described according to test errors number of bits and it is corresponding test be unsatisfactory for syndrome number establish
Initial model step；
If it is not, then returning to the utilization random number generates corresponding test errors bit step.
In one embodiment, processor 502 realize it is described initial model step is established according to statistical result when, it is specific real
Existing following steps:
The corresponding test syndrome number of same test errors number of bits is averaged, to form object identifier
Number；
According to the section of test errors number of bits and the sub- number of corresponding object identifier, relation curve is obtained, to obtain
Initial model.
In one embodiment, processor 502 realize it is described initial model is fitted, formed object module step
When, it is implemented as follows step:
Threshold interval division is carried out to the sub- number of object identifier according to relation curve；
Piecewise fitting is carried out using minimum variance according to division result and fitting formula, determines impact factor and offset
Value；
Object module is determined according to impact factor and deviant.
Wherein, fitting formula includes: sμ(x)=ax+b；Wherein, a > 0, b > 0；A is ratio impact factor, and b is inclined
Shifting value.
In one embodiment, processor 502 described using object module and be actually unsatisfactory for syndrome number and estimate realizing
When calculating factual error number of bits step, it is implemented as follows step:
Obtain the practical section being actually unsatisfactory for where syndrome number；
Using the object module in practical section, factual error number of bits is estimated according to syndrome number is actually unsatisfactory for.
It should be appreciated that in the embodiment of the present application, processor 502 can be central processing unit (Central
Processing Unit, CPU), which can also be other general processors, digital signal processor (Digital
Signal Processor, DSP), specific integrated circuit (Application Specific Integrated Circuit,
ASIC), ready-made programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic
Device, discrete gate or transistor logic, discrete hardware components etc..Wherein, general processor can be microprocessor or
Person's processor is also possible to any conventional processor etc..
Those of ordinary skill in the art will appreciate that be realize above-described embodiment method in all or part of the process,
It is that relevant hardware can be instructed to complete by computer program.The computer program includes program instruction, computer journey
Sequence can be stored in a storage medium, which is computer readable storage medium.The program instruction is by the department of computer science
At least one processor in system executes, to realize the process step of the embodiment of the above method.
Therefore, the present invention also provides a kind of storage mediums.The storage medium can be computer readable storage medium.This is deposited
Storage media is stored with computer program, and processor is made to execute following steps when wherein the computer program is executed by processor:
Test errors number of bits and corresponding test in statistics set interval are unsatisfactory for syndrome number；
Initial model is established according to statistical result；
Initial model is fitted, object module is formed；
Syndrome number is actually unsatisfactory for the code word calculating of input decoder when in use；
It using object module and is actually unsatisfactory for syndrome number and estimates factual error number of bits.
In one embodiment, the processor is realized in the statistics set interval in the execution computer program
When test errors number of bits and corresponding test are unsatisfactory for syndrome number step, it is implemented as follows step:
Obtain initial data；
Initial data is encoded, test codeword is obtained；
Set section, step-length and the maximum statistics number of the test errors number of bits injected at random；
Corresponding test errors number of bits is generated using random number；
Test codeword is added in test errors number of bits；
Test, which is calculated, according to test codeword is unsatisfactory for syndrome number；
The corresponding test of record test errors number of bits is unsatisfactory for syndrome number；
Judge to record whether number reaches maximum statistics number；
If it is not, then returning to the utilization random number generates corresponding test errors bit step；
If so, resetting the test errors number of bits of injection according to step-length；
Judge whether the test errors number of bits of injection reaches the maximum value in section；
If so, into it is described according to test errors number of bits and it is corresponding test be unsatisfactory for syndrome number establish
Initial model step；
If it is not, then returning to the utilization random number generates corresponding test errors bit step.
In one embodiment, the processor is realized and described is established according to statistical result executing the computer program
When initial model step, it is implemented as follows step:
The corresponding test syndrome number of same test errors number of bits is averaged, to form object identifier
Number；
According to the section of test errors number of bits and the sub- number of corresponding object identifier, relation curve is obtained, to obtain
Initial model.
In one embodiment, the processor is realized and described is intended initial model executing the computer program
It closes, when forming object module step, is implemented as follows step:
Threshold interval division is carried out to the sub- number of object identifier according to relation curve；
Piecewise fitting is carried out using minimum variance according to division result and fitting formula, determines impact factor and offset
Value；
Object module is determined according to impact factor and deviant
Wherein, the fitting formula includes: sμ(x)=ax+b；Wherein, a > 0, b > 0；A is ratio impact factor, b
For deviant
In one embodiment, the processor realizes utilization object module and the reality executing the computer program
When border is unsatisfactory for syndrome number estimation factual error number of bits step, it is implemented as follows step:
Obtain the practical section being actually unsatisfactory for where syndrome number；
Using the object module in practical section, factual error number of bits is estimated according to syndrome number is actually unsatisfactory for.
The storage medium can be USB flash disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), magnetic disk
Or the various computer readable storage mediums that can store program code such as CD.
Those of ordinary skill in the art may be aware that list described in conjunction with the examples disclosed in the embodiments of the present disclosure
Member and algorithm steps, can be realized with electronic hardware, computer software, or a combination of the two, in order to clearly demonstrate hardware
With the interchangeability of software, each exemplary composition and step are generally described according to function in the above description.This
A little functions are implemented in hardware or software actually, the specific application and design constraint depending on technical solution.Specially
Industry technical staff can use different methods to achieve the described function each specific application, but this realization is not
It is considered as beyond the scope of this invention.
In several embodiments provided by the present invention, it should be understood that disclosed device and method can pass through it
Its mode is realized.For example, the apparatus embodiments described above are merely exemplary.For example, the division of each unit, only
Only a kind of logical function partition, there may be another division manner in actual implementation.Such as multiple units or components can be tied
Another system is closed or is desirably integrated into, or some features can be ignored or not executed.
The steps in the embodiment of the present invention can be sequentially adjusted, merged and deleted according to actual needs.This hair
Unit in bright embodiment device can be combined, divided and deleted according to actual needs.In addition, in each implementation of the present invention
Each functional unit in example can integrate in one processing unit, is also possible to each unit and physically exists alone, can also be with
It is that two or more units are integrated in one unit.
If the integrated unit is realized in the form of SFU software functional unit and when sold or used as an independent product,
It can store in one storage medium.Based on this understanding, technical solution of the present invention is substantially in other words to existing skill
The all or part of part or the technical solution that art contributes can be embodied in the form of software products, the meter
Calculation machine software product is stored in a storage medium, including some instructions are used so that a computer equipment (can be a
People's computer, terminal or network equipment etc.) it performs all or part of the steps of the method described in the various embodiments of the present invention.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in various equivalent modifications or replace
It changes, these modifications or substitutions should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with right
It is required that protection scope subject to.
Claims (10)
1. error bit number estimation method characterized by comprising
Test errors number of bits and corresponding test in statistics set interval are unsatisfactory for syndrome number；
Initial model is established according to statistical result；
Initial model is fitted, object module is formed；
Syndrome number is actually unsatisfactory for the code word calculating of input decoder when in use；
It using object module and is actually unsatisfactory for syndrome number and estimates factual error number of bits.
2. error bit number estimation method according to claim 1, which is characterized in that in the statistics set interval
Test errors number of bits and corresponding test are unsatisfactory for syndrome number, comprising:
Obtain initial data；
Initial data is encoded, test codeword is obtained；
Set section, step-length and the maximum statistics number of the test errors number of bits injected at random；
Corresponding test errors number of bits is generated using random number；
Test codeword is added in test errors number of bits；
Test, which is calculated, according to test codeword is unsatisfactory for syndrome number；
The corresponding test of record test errors number of bits is unsatisfactory for syndrome number；
Judge to record whether number reaches maximum statistics number；
If it is not, then returning to the utilization random number generates corresponding test errors bit step；
If so, resetting the test errors number of bits of injection according to step-length；
Judge whether the test errors number of bits of injection reaches the maximum value in section；
If so, into it is described according to test errors number of bits and corresponding test be unsatisfactory for syndrome number establish it is initial
Model step；
If it is not, then returning to the utilization random number generates corresponding test errors bit step.
3. error bit number estimation method according to claim 1 or 2, which is characterized in that described according to statistical result
Establish initial model, comprising:
The corresponding test syndrome number of same test errors number of bits is averaged, to form the sub- number of object identifier；
According to the section of test errors number of bits and the sub- number of corresponding object identifier, relation curve is obtained, it is initial to obtain
Model.
4. error bit number estimation method according to claim 3, which is characterized in that described to intend initial model
It closes, forms object module, comprising:
Threshold interval division is carried out to the sub- number of object identifier according to relation curve；
Piecewise fitting is carried out using minimum variance according to division result and fitting formula, determines impact factor and deviant；
Object module is determined according to impact factor and deviant.
5. error bit number estimation method according to claim 4, which is characterized in that the fitting formula includes: sμ
(x)=ax+b；Wherein, a > 0, b > 0；A is ratio impact factor, and b is deviant.
6. error bit number estimation method according to claim 4, which is characterized in that described to utilize object module and reality
Border is unsatisfactory for syndrome number estimation factual error number of bits, comprising:
Obtain the practical section being actually unsatisfactory for where syndrome number；
Using the object module in practical section, factual error number of bits is estimated according to syndrome number is actually unsatisfactory for.
7. error bit number estimation device characterized by comprising
Statistic unit is unsatisfactory for syndrome for counting test errors number of bits in set interval and corresponding test
Number；
Initial model establishes unit, for establishing initial model according to statistical result；
Fitting unit forms object module for being fitted to initial model；
Actual number computing unit is actually unsatisfactory for syndrome number for the code word calculating when in use to input decoder；
Number of bits evaluation unit estimates factual error bit for using object module and being actually unsatisfactory for syndrome number
Number.
8. error bit number estimation device according to claim 7, which is characterized in that the statistic unit includes:
Data acquisition module, for obtaining initial data；
Coding module obtains test codeword for encoding to initial data；
Setting module, for setting section, step-length and the maximum statistics number of the test errors number of bits injected at random；
Random generating module, for generating corresponding test errors number of bits using random number；
Module is added, for test codeword to be added in test errors number of bits；
Computing module is unsatisfactory for syndrome number for calculating test according to test codeword；
Logging modle, for recording the corresponding test syndrome number of test errors number of bits；
Number judgment module records whether number reaches maximum statistics number for judging；
Step size settings module, for if so, resetting the test errors number of bits of injection according to step-length；
Interval judgement module, for judging whether the test errors number of bits of injection reaches the maximum value in section.
9. a kind of computer equipment, which is characterized in that the computer equipment includes memory and processor, on the memory
It is stored with computer program, the processor is realized as described in any one of claims 1 to 6 when executing the computer program
Method.
10. a kind of storage medium, which is characterized in that the storage medium is stored with computer program, the computer program quilt
Processor can be realized when executing such as method described in any one of claims 1 to 6.
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