CN109361467B - Optical module - Google Patents
Optical module Download PDFInfo
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- CN109361467B CN109361467B CN201811474977.1A CN201811474977A CN109361467B CN 109361467 B CN109361467 B CN 109361467B CN 201811474977 A CN201811474977 A CN 201811474977A CN 109361467 B CN109361467 B CN 109361467B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/40—Transceivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/80—Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups H04B10/03 - H04B10/70, e.g. optical power feeding or optical transmission through water
- H04B10/806—Arrangements for feeding power
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- Computer Networks & Wireless Communication (AREA)
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- Optical Communication System (AREA)
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Abstract
The application discloses an optical module and an optical network system, and belongs to the technical field of optical fiber communication. The embodiment of the application discloses an optical module, which comprises a microprocessor, a first field effect transistor, a second field effect transistor, a capacitor and a golden finger, wherein the microprocessor is provided with a first communication pin and a second communication pin, and the golden finger is provided with a data line pin and a clock line pin; the capacitor, the data line pin and the clock line pin are respectively connected with a power supply of the optical module; one end of the first field effect transistor is connected with the first communication pin, the other end of the first field effect transistor is connected with the data line pin, and the grid electrode of the first field effect transistor is connected with the capacitor; one end of the second field effect transistor is connected with the second communication pin, the other end of the second field effect transistor is connected with the clock line pin, and the grid electrode of the second field effect transistor is connected with the capacitor.
Description
Technical Field
The application relates to the technical field of optical communication, in particular to an optical module.
Background
The optical fiber communication mode is a communication mode that light waves are used as information carriers and optical fibers are used as transmission media, the optical module is an optical signal interface device which is very important in optical fiber communication, one end of the optical module is used as an optical interface and connected with the optical fibers, the other end of the optical module is used as an electrical interface and connected with external communication equipment, and the optical module can convert optical signals and electrical signals.
With the increasing demand for bandwidth, the demand of optical modules in optical networks is increasing, and ten or twenty optical modules often appear on an upper computer, and most of the optical modules are hot-pluggable optical modules. In the prior art, the optical modules are communicated by the upper computer through addresses a2 and a0, and when a plurality of optical modules exist on the upper computer, the upper computer is connected with the plurality of optical modules through an IIC bus for realizing communication transmission between the upper computer and the plurality of optical modules. As shown in fig. 1, a golden finger is arranged at one end of the hot-pluggable optical module, the optical module is inserted into the upper computer through the golden finger, the upper computer supplies power to the MCU of the optical module through a power supply pin of the golden finger, and a slow start circuit is arranged on a circuit board between the MCU and the golden finger, and is used for supplying power to the MCU slowly to ensure normal operation of inserting the optical module.
However, when the upper computer supplies power to the optical module through the power supply pin, since the IIC bus is directly connected to the MCU of the optical module, the slow start circuit supplies power slowly, and thus the power supply pin directly supplies power to the MCU of the optical module through the IIC bus without passing through the slow start circuit, and the MCU-IIC line can be regarded as an RC circuit, and when the power supply pin supplies power to the MCU through the IIC bus, the RC circuit is charged, which may cause a reduction in the level on the IIC bus, affect the communication between the IIC bus and the optical module already operating on the upper computer, and easily cause a communication failure.
Disclosure of Invention
The application provides an optical module to solve the technical problem that when the existing optical module is inserted into an upper computer, the level of an IIC bus is influenced, and communication failure is easily caused.
In order to solve the technical problem, the embodiment of the application discloses the following technical scheme:
the embodiment of the application discloses an optical module, which comprises a microprocessor, a first field effect transistor, a second field effect transistor, a capacitor and a golden finger, wherein the microprocessor is provided with a first communication pin and a second communication pin, and the golden finger is provided with a data line pin and a clock line pin; the capacitor, the data line pin and the clock line pin are respectively connected with a power supply of the optical module; one end of the first field effect transistor is connected with the first communication pin, the other end of the first field effect transistor is connected with the data line pin, and the grid electrode of the first field effect transistor is connected with the capacitor; one end of the second field effect transistor is connected with the second communication pin, the other end of the second field effect transistor is connected with the clock line pin, and the grid electrode of the second field effect transistor is connected with the capacitor.
Compared with the prior art, the beneficial effect of this application is:
when the module power VCC is 0V at the moment of hot plugging of the optical module, the power pulls down the voltage of the data line pin and the clock line pin, the voltage of the first field effect transistor and the second field effect transistor is 0V, VGS is smaller than the turn-on voltage of the MOS transistor at the moment, the MOS transistor is in a cut-off state at the moment, namely the data line pin and the clock line pin inside the module are isolated from the external IIC bus, and although the IIC bus inside the module is pulled down by VCC at the moment, the IIC bus of external equipment cannot be influenced, so that the purpose of eliminating interference is achieved; as VCC in the module gradually rises, VCC charges the capacitor, and the voltage of the capacitor (namely the G-voltage of the field effect transistor) gradually rises and is larger than the conduction voltage of the MOS transistor, the MOS transistor is conducted; because the G pole voltage of the MOS tube is charged through the VCC, the G pole voltage is always later than the VCC, and the MOS tube is switched on after the VCC is stable through the capacitance value, so that the influence of the instability of the VCC on the IIC bus in the module plugging process is avoided. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
In order to more clearly explain the technical solution of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious to those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a general optical module;
FIG. 2 is a diagram of a power-on equivalent circuit in a general optical module (IIC in MCU is equivalent to RC circuit);
FIG. 3 is a schematic diagram of an IIC bus timing sequence of an upper computer at the power-on instant of a general optical module;
fig. 4 is a schematic structure of an optical module provided in an embodiment of the present application;
fig. 5 is a schematic diagram of an IIC bus timing sequence of an upper computer in an optical module at the moment of power-on according to an embodiment of the present application.
Detailed Description
In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In modern optical networks, with the requirement for bandwidth becoming higher and higher, the demand for optical modules becomes larger and larger, and ten or twenty optical modules appear on an upper computer in the field, and most of the optical modules are hot-pluggable optical modules. According to the design requirements of the optical modules, the upper computer communicates with each optical module by using addresses A2 and A0, so that the upper computer and each optical module can be connected through a common IIC bus. As shown in fig. 1, in the case that there are a plurality of optical modules on the upper computer 2, the optical modules are inserted into the upper computer through a golden finger, the upper computer is connected with the plurality of optical modules through an IIC bus, the IIC bus is composed of a serial data line SDA and a serial clock line SCL, and the upper computer transmits data on the SDA and simultaneously transmits a clock through the SCL, so that data transmission between the upper computer and the optical modules is realized. And the plurality of optical modules are connected to the IIC bus and used for realizing communication between the upper computer and the plurality of optical modules.
When the hot-pluggable optical module is plugged on an upper computer through the golden finger, the power supply pin of the golden finger supplies power to the MCU of the optical module, a slow starting circuit 13 is arranged between the MCU and the power supply pin for preventing the voltage of the MCU from suddenly changing at the moment of power-on, and the power supply pin supplies power to the MCU slowly through the slow starting circuit. However, as shown in fig. 2, since the IIC bus (the data line and the clock line) is directly connected to the MCU of the optical module, the slow start circuit supplies power slowly, when the power supply pin supplies power to the MCU, the IIC bus with smaller power supply current selection resistance supplies power to the MCU, and the IIC circuit in the MCU may be equivalent to an RC circuit, and when the power supply pin supplies power to the MCU through the IIC bus, the RC circuit is charged, which may cause a level on the IIC bus to decrease. As shown in fig. 3, when a new optical module is inserted into the upper computer, the new optical module causes a sudden drop in the time sequence of the bus of the upper computer at the moment of power-on, which affects the communication between the IIC bus and the optical module already operating on the upper computer, and causes a communication failure.
In order to solve the above problems, an embodiment of the present application provides an optical module, including a microprocessor, a first field effect transistor, a second field effect transistor, a capacitor, and a gold finger, where the microprocessor is provided with a first communication pin and a second communication pin, and the gold finger is provided with a data line pin and a clock line pin; the capacitor, the data line pin and the clock line pin are respectively connected with a power supply of the optical module; one end of the first field effect transistor is connected with the first communication pin, the other end of the first field effect transistor is connected with the data line pin, and the grid electrode of the first field effect transistor is connected with the capacitor; one end of the second field effect transistor is connected with the second communication pin, the other end of the second field effect transistor is connected with the clock line pin, and the grid electrode of the second field effect transistor is connected with the capacitor.
When the module power VCC is 0V at the moment of hot plugging of the optical module, the power pulls down the voltage of the data line pin and the clock line pin, the voltage of the first field effect transistor and the second field effect transistor is 0V, VGS is smaller than the turn-on voltage of the MOS transistor at the moment, the MOS transistor is in a cut-off state at the moment, namely the data line pin and the clock line pin inside the module are isolated from the external IIC bus, and although the IIC bus inside the module is pulled down by VCC at the moment, the IIC bus of external equipment cannot be influenced, so that the purpose of eliminating interference is achieved; as VCC in the module gradually rises, VCC charges the capacitor, and the voltage of the capacitor (namely the G-voltage of the field effect transistor) gradually rises and is larger than the conduction voltage of the MOS transistor, the MOS transistor is conducted; because the G pole voltage of the MOS tube is charged through the VCC, the G pole voltage is always later than the VCC, and the MOS tube is switched on after the VCC is stable through the capacitance value, so that the influence of the instability of the VCC on the IIC bus in the module plugging process is avoided.
Referring to fig. 4, a schematic structural diagram of an optical module provided in the embodiment of the present application is shown, where an MCU in the optical module has a data line pin SDA and a clock line pin SCL. This is a common I2C communication pin, and information can be transmitted between two devices through a data line pin and a clock line pin according to the I2C communication protocol. According to the embodiment of the application, communication between the optical module and the external upper computer of the optical module is achieved.
Generally, a data line pin and a clock line pin of the MCU are directly connected to corresponding pins on a golden finger of the optical module, and the golden finger is inserted into the upper computer to realize communication with the upper computer. In this application, the first communication pin and the second communication pin on the magic photo golden finger are pins corresponding to the MCU pin. The data line pin is finally connected with the first communication pin, and the clock line pin is finally connected with the second communication pin. In the present application, for the purpose of the invention, a first fet Q6 is connected in series between the data line pin and the first communication pin, and a second fet Q7 is connected in series between the clock line pin and the second communication pin.
The field effect transistor is provided with a source electrode, a grid electrode and a drain electrode, and the conduction and the closing control are realized through the voltage relation between the source electrode and the grid electrode. Specifically, the NMOS transistor is characterized in that when the VGS voltage is greater than the turn-on voltage, the MOS transistor is turned on, and when the VGS voltage is less than the turn-on voltage, the MOS transistor is turned off, which is equivalent to the isolation between the IIC bus inside the module and the IIC bus of the device.
Specifically, the power supply of the optical module may be a power supply pin on a finger of the optical module, and the upper computer supplies power to all devices in the optical module through the power supply pin. The power supply of the optical module can also be provided with a power supply management chip, the power supply pin introduces electricity into the power supply management chip, and the power supply management chip supplies power to the inside of the optical module.
The power source vcc is connected with the first communication pin through the first resistor R32, connected with the second communication pin through the second resistor R33, and connected with the capacitor C2 through the third resistor R34, the capacitor C2 starts to be charged after being electrified, and the voltage of the capacitor gradually increases.
When the optical module is inserted into an upper computer and powered on, because VCC is 0, the voltages of two MOS (metal oxide semiconductor) tubes Q6 and Q7 are 0V, VGS is smaller than the conduction voltage of the MOS tubes, the MOS tubes are in a cut-off state, namely SDA and SCL (two circuits of IIC) inside the module are isolated from an external IIC bus, although the IIC bus inside the module is pulled down by VCC, the IIC bus of external equipment cannot be influenced, and therefore the purpose of eliminating interference is achieved; with the gradual rise of VCC in the module, VCC charges the C2 capacitor through R34, and the voltage of the C2 capacitor (namely the G-voltage of the MOS transistor) gradually rises and is greater than the conduction voltage of the MOS transistor, so that the MOS transistor is conducted; because the G pole voltage of the MOS tube is charged through VCC, the G pole voltage is always later than VCC, and the MOS tube is switched on again after the VCC is stable by adjusting the resistance and the capacitance of R34 and C2, thereby avoiding the influence of the VCC instability on the IIC bus in the module plugging process.
As shown in fig. 5, after the field effect transistor is additionally arranged on the data line and the clock line (IIC bus) connecting the MCU11 and the gold finger 12, the MCU11 has little time sequence change of the IIC bus of the upper computer at the moment of power-on, so as to ensure the stability of the level in the IIC bus and ensure the normal communication between each optical module and the upper computer.
In the embodiment of the application, the pin of the field effect transistor is inserted on the circuit board of the optical module 1, the optical module comprises an optical device, a shell and the circuit board, and the optical device of the optical module is inserted on the circuit board for fixing, so that the pin of the field effect transistor is inserted on the circuit board, and the connection stability of the field effect transistor is ensured.
The field effect transistor can be an electronic field effect transistor or a mechanical field effect transistor, the electronic field effect transistor is a unit which uses the electronic technology to drive a certain element to realize the on-off of a circuit through current or voltage, namely the field effect transistor is closed after the electronic field effect transistor receives a high-voltage signal of the MCU 11; when the electronic field effect tube receives the low voltage signal of the MCU11, the field effect tube is disconnected. The fet is a component for opening, closing, and switching a circuit by mechanical operation, that is, after receiving a control signal from the MCU11, the fet is controlled to open or close by some mechanical operation (e.g., a pull ring or a button). Because the mechanical field effect transistor occupies a large space, an electronic field effect transistor is generally adopted in the optical module.
The working process of the optical module provided by the embodiment of the application is as follows: when a new optical module (adopting the optical module of the scheme of the application) is inserted into an upper computer, the first field effect tube and the second field effect tube are in an off state, and a power supply pin of the optical module supplies power to the MCU through the slow starting circuit; when the detection voltage of the MCU reaches a preset threshold value, the first field effect transistor and the second field effect transistor are in a conducting state; and the MCU and the golden finger are communicated, and IIC communication requirements of the upper computer are responded normally.
Based on the optical module provided by the embodiment, the embodiment of the application further provides an optical network system, which comprises the optical module provided by the embodiment, and the field effect transistor is arranged on the data line and the clock line (IIC bus) connecting the MCU and the golden finger in the optical module, so that the level of the IIC bus is not affected by the newly inserted optical module, thereby ensuring the communication between the IIC bus and the optical module already in operation, and avoiding the occurrence of communication failure.
Through the above description of the embodiments, those skilled in the art will clearly understand that the present invention may be implemented by software plus necessary general hardware, and certainly may also be implemented by hardware, but in many cases, the former is a better embodiment.
It should be noted that, in the present specification, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a circuit structure, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such circuit structure, article, or apparatus. Without further limitation, the presence of an element identified by the phrase "comprising an … …" does not exclude the presence of other like elements in a circuit structure, article or device comprising the element.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
The above-described embodiments of the present application do not limit the scope of the present application.
Claims (4)
1. An optical module, which is characterized by comprising a microprocessor, a first field effect transistor, a second field effect transistor, a capacitor and a golden finger,
the microprocessor is provided with a first communication pin and a second communication pin, and the golden finger is provided with a data line pin and a clock line pin;
the capacitor, the data line pin and the clock line pin are respectively connected with a power supply of the optical module;
one end of the first field effect transistor is connected with the first communication pin, the other end of the first field effect transistor is connected with the data line pin, and the grid electrode of the first field effect transistor is connected with the capacitor;
one end of the second field effect transistor is connected with the second communication pin, the other end of the second field effect transistor is connected with the clock line pin, and the grid electrode of the second field effect transistor is connected with the capacitor.
2. The optical module of claim 1, wherein a first resistor is connected in series between the power supply and the data line pin, and a second resistor is connected in series between the power supply and the clock line pin.
3. The optical module of claim 1, wherein the power supply is a power pin on the gold finger.
4. The optical module of claim 1, wherein the power supply is a power management chip of the optical module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811474977.1A CN109361467B (en) | 2018-12-04 | 2018-12-04 | Optical module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811474977.1A CN109361467B (en) | 2018-12-04 | 2018-12-04 | Optical module |
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| CN109361467A CN109361467A (en) | 2019-02-19 |
| CN109361467B true CN109361467B (en) | 2021-07-06 |
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| CN201811474977.1A Active CN109361467B (en) | 2018-12-04 | 2018-12-04 | Optical module |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110460381A (en) * | 2019-08-12 | 2019-11-15 | 青岛海信宽带多媒体技术有限公司 | A kind of optical module |
| CN114285477A (en) * | 2021-12-17 | 2022-04-05 | 青岛海信宽带多媒体技术有限公司 | Optical module |
Citations (4)
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| CN1567278A (en) * | 2003-07-06 | 2005-01-19 | 华为技术有限公司 | Assess controlling system for bus of internal integrated circuit |
| CN206259950U (en) * | 2016-10-25 | 2017-06-16 | 深圳欧陆通电子有限公司 | A kind of communication bus isolation circuit |
| CN106936496A (en) * | 2017-04-20 | 2017-07-07 | 江苏奥雷光电有限公司 | Multiple IIC communication equipments hot plug devices |
| CN108365888A (en) * | 2018-02-01 | 2018-08-03 | 四川泰瑞创通讯技术股份有限公司 | The device of test light module performance |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN207819925U (en) * | 2018-02-08 | 2018-09-04 | 衡阳泰豪通信车辆有限公司 | A kind of modular communication networking platform based on fiber buss |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1567278A (en) * | 2003-07-06 | 2005-01-19 | 华为技术有限公司 | Assess controlling system for bus of internal integrated circuit |
| CN206259950U (en) * | 2016-10-25 | 2017-06-16 | 深圳欧陆通电子有限公司 | A kind of communication bus isolation circuit |
| CN106936496A (en) * | 2017-04-20 | 2017-07-07 | 江苏奥雷光电有限公司 | Multiple IIC communication equipments hot plug devices |
| CN108365888A (en) * | 2018-02-01 | 2018-08-03 | 四川泰瑞创通讯技术股份有限公司 | The device of test light module performance |
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