CN109360826B

CN109360826B - Three-dimensional memory

Info

Publication number: CN109360826B
Application number: CN201811202855.7A
Authority: CN
Inventors: 华子群; 夏志良; 刘峻
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2018-10-16
Filing date: 2018-10-16
Publication date: 2020-07-07
Anticipated expiration: 2038-10-16
Also published as: CN109360826A

Abstract

The invention provides a three-dimensional memory, comprising: one or more array common sources extending in a first direction on a substrate; and a first conductive pattern on the one or more array common sources comprising: one or more connection lines extending in a second direction electrically connecting at least one of the array common sources; dummy connection lines extending in the second direction and located at both sides of the one or more connection lines; and a plurality of bit lines extending in the second direction and located at both sides of the dummy connection line. The pseudo connecting lines are uniformly arranged on two sides of the connecting line in the three-dimensional memory, so that the short circuit risk of the connecting line and the bit line is reduced. In addition, since the dummy connection lines are disposed at both sides of the connection lines, process window protection is provided when the first conductive pattern is formed using a self-aligned double patterning process or the like. In addition, the connecting line can have a larger width, reducing the resistance thereof.

Description

Three-dimensional memory

Technical Field

The invention mainly relates to the field of semiconductors, in particular to a three-dimensional memory.

Background

With the continuous improvement of the storage density requirement of the market, the key size reduction of the two-dimensional memory reaches the limit of the mass production technology, and in order to further improve the storage capacity and reduce the cost, the memory with the three-dimensional structure is provided.

Bit lines electrically connected with the channel layer in the channel structure and connecting lines electrically connected with the array common source are included in the three-dimensional memory. The connecting lines are used for introducing current into the array common source. Generally, the bit lines and the connection lines are located at the same layer and are formed at the same time. To further increase the memory density, more channel structures may be arranged per unit area of the three-dimensional memory core region. Accordingly, the density of bit lines and connecting lines in the core region may be further increased and the line-to-line spacing may be decreased. This increases the risk of a short circuit between the bit line and the connection line.

Disclosure of Invention

The invention provides a three-dimensional memory, which reduces the risk of short circuit between a bit line and a connecting line and improves the process window for forming the bit line and the connecting line.

To solve the above technical problem, the present invention provides a three-dimensional memory, including: one or more array common sources extending in a first direction on a substrate; and a first conductive pattern on the one or more array common sources comprising: one or more connection lines extending in a second direction electrically connecting at least one of the array common sources; dummy connection lines extending in the second direction and located at both sides of the one or more connection lines; and a plurality of bit lines extending in the second direction and located at both sides of the dummy connection line.

In an embodiment of the present invention, the dummy connection line is adjacent to the bit line.

In an embodiment of the invention, at least one side of the one or more connection lines is provided with a plurality of the dummy connection lines.

In an embodiment of the invention, the one or more connection lines are electrically connected to at least two of the plurality of array common sources at the same time.

In an embodiment of the invention, at least two of the plurality of connection lines are connected to each other.

In an embodiment of the invention, the three-dimensional memory further includes a second conductive pattern between the one or more array common sources and the first conductive pattern, and at least one of the connection lines is electrically connected to at least one of the array common sources through the second conductive pattern.

In an embodiment of the invention, the second conductive pattern includes one or more first conductive lines extending along the second direction, and the one or more first conductive lines are electrically connected to the connection lines.

In an embodiment of the invention, at least two of the plurality of first conductive lines are connected to each other.

In an embodiment of the invention, at least one of the first conductive lines is electrically connected to a plurality of the connection lines.

In an embodiment of the invention, at least one of the first conductive lines electrically connects two adjacent connection lines.

In an embodiment of the invention, the second conductive pattern includes one or more second conductive lines extending along the second direction, and electrically connects the bit lines.

In an embodiment of the present invention, at least one of the second wires further electrically connects the channel layers in two channel holes adjacent in the second direction.

In an embodiment of the invention, the second conductive pattern includes one or more third conductive lines extending along the second direction, and electrically connects the dummy connection lines.

In an embodiment of the invention, at least one of the dummy connection lines is connected to a plurality of the third conductive lines.

In an embodiment of the invention, the three-dimensional memory further includes a plurality of conductive plugs respectively connected to the first conductive patterns and the second conductive patterns.

In an embodiment of the invention, the three-dimensional memory further includes a plurality of conductive contact blocks respectively connected to the first conductive line and the array common source.

In an embodiment of the invention, the first conductive pattern includes one of the connection lines, and a width of the connection line is greater than a width of the dummy connection line and/or the bit line.

In an embodiment of the invention, the first direction and the second direction are perpendicular to each other.

Compared with the prior art, the invention has the following advantages:

the pseudo connecting lines are uniformly arranged on two sides of the connecting line in the three-dimensional memory, so that the short circuit risk of the connecting line and the bit line is reduced. In addition, since dummy connection lines are disposed at both sides of the connection lines, process window protection is provided when the first conductive patterns are formed using Self-aligned Double Patterning (SADP) or the like. In addition, the connecting line can have a larger width, reducing the resistance thereof.

Drawings

FIG. 1 is a partial top view of a three-dimensional memory.

FIG. 2 is a partial cross-sectional view of the three-dimensional memory shown in FIG. 1 taken along line A-A.

FIG. 3 is a partial cross-sectional view of the three-dimensional memory shown in FIG. 1 taken along line B-B.

FIG. 4 is a partial cross-sectional view of the three-dimensional memory shown in FIG. 1 taken along line C-C.

FIG. 5 is a partial cross-sectional view of the three-dimensional memory shown in FIG. 1 taken along line D-D.

FIG. 6 is a partial top view of a three-dimensional memory of some embodiments of the inventions.

Fig. 7 is a partial cross-sectional view of the three-dimensional memory shown in fig. 6 taken along line a-a.

FIG. 8 is a partial cross-sectional view of the three-dimensional memory shown in FIG. 6 taken along line B-B.

FIG. 9 is a partial cross-sectional view of the three-dimensional memory shown in FIG. 6 taken along line C-C.

Fig. 10 is a partial cross-sectional view of the three-dimensional memory shown in fig. 6 taken along line D-D.

FIG. 11 is a partial top view of a three-dimensional memory of some embodiments of the inventions.

Fig. 12 is a partial cross-sectional view of the three-dimensional memory shown in fig. 11 taken along line a-a.

FIG. 13 is a partial cross-sectional view of the three-dimensional memory of FIG. 11 taken along line B-B.

FIG. 14 is a partial cross-sectional view of the three-dimensional memory of FIG. 11 taken along line C-C.

FIG. 15 is a partial cross-sectional view of the three-dimensional memory of FIG. 11 taken along line D-D.

FIG. 16 is a partial top view of a three-dimensional memory of some embodiments of the inventions.

Fig. 17 is a partial cross-sectional view of the three-dimensional memory shown in fig. 16 taken along line a-a.

FIG. 18 is a partial cross-sectional view of the three-dimensional memory of FIG. 16 taken along line B-B.

FIG. 19 is a partial cross-sectional view of the three-dimensional memory of FIG. 16 taken along line C-C.

Fig. 20 is a partial cross-sectional view of the three-dimensional memory of fig. 16 taken along line D-D.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

Fig. 1 is a partial top view of a three-dimensional memory 100. Fig. 2 is a partial cross-sectional view of the three-dimensional memory 100 shown in fig. 1 taken along line a-a. Fig. 3 is a partial cross-sectional view of the three-dimensional memory 100 shown in fig. 1 taken along line B-B. Fig. 4 is a partial cross-sectional view of the three-dimensional memory 100 shown in fig. 1 taken along line C-C. Fig. 5 is a partial cross-sectional view of the three-dimensional memory 100 shown in fig. 1 taken along line D-D. As shown with combined reference to fig. 1-5, three-dimensional memory 100 may include a substrate 100a and a stack of layers 100b in a core region. The stack layer 100b may include gate layers and spacer layers alternately stacked in a direction perpendicular to the substrate 100 a. The stacked layer 100b has a first array common-source 111 and a second array common-source 112 perpendicular to the substrate 100a and extending in the first direction D1. The stacked layer 100b also has a channel hole 170 perpendicular to the substrate 100a, in which a memory layer and a channel layer are sequentially disposed along the channel hole 170 from the outside to the inside. Here, the memory layer may include a charge blocking layer, a charge trapping layer, and a tunneling layer. The upper portion of stacked layer 100b also has a top select gate 160 extending along first direction D1. The top select gate 160 is located between the first array common-source 111 and the second array common-source 112.

The three-dimensional memory 100 may further include a first conductive pattern 120 and a second conductive pattern 130 over the stacked layer 100 b. The second conductive pattern 130 is positioned between the first conductive pattern 120 and the stacked layer 100 b.

The first conductive pattern 120 may be divided into an array common source node connection region 120a and a bit line region 120b according to their functions. The array common-source connection region 120a is located between two bit line regions 120 b. The array common-source connection region 120a includes a plurality of connection lines 121 electrically connected to the first array common-source electrode 111 and/or the second array common-source electrode 112, and a dummy connection line 122 not electrically connected to the first array common-source electrode 111 and the second array common-source electrode 112. The bit line region 120b includes a plurality of bit lines 123. The connection line 121, the dummy connection line 122, and the bit line 123 all extend in the second direction D2.

The second conductive pattern 130 includes a first conductive line 131 electrically connected to the connection line 121, a second conductive line 132 electrically connected to the bit line 123, and a third conductive line 133 electrically connected to the dummy connection line.

The connection line 121, the dummy connection line 122, and the bit line 123 are connected to the first conductive line 131, the third conductive line 133, and the second conductive line 132, respectively, through the conductive plugs 140. The first wire 131 is connected to the first array common-source 111 and the second array common-source 112, respectively, through a conductive contact block 150.

As shown in fig. 1-4, the array common-source connection region 120a of the three-dimensional memory 100 has dummy connection lines 122 only on one side, and the connection lines 121 on the other side are directly adjacent to the bit lines 123. As the density of the bit lines 123 and the connection lines 121 is further increased, the interval between the bit lines 123 and the connection lines 121 becomes smaller, and the risk of short-circuiting the bit lines 123 and the connection lines 123 increases. In addition, as the density of the bit lines 123 and the connection lines 121 increases, a process margin is reduced when the first conductive patterns 120 are formed using a Self-aligned double patterning (SADP) process or the like.

The embodiment of the invention describes a three-dimensional memory capable of reducing the risk of short circuit between a bit line and a connecting line, and improves a process window.

Figure 6 is a partial top view of a three-dimensional memory 200 of some embodiments of the inventions. Fig. 7 is a partial cross-sectional view of the three-dimensional memory 200 shown in fig. 6 taken along line a-a. Fig. 8 is a partial cross-sectional view of the three-dimensional memory 200 shown in fig. 6 taken along line B-B. Fig. 9 is a partial cross-sectional view of the three-dimensional memory 200 shown in fig. 6 along the line C-C. Fig. 10 is a partial cross-sectional view of the three-dimensional memory 200 shown in fig. 6 taken along line D-D. As shown in conjunction with fig. 6-10, three-dimensional memory 200 may include substrate 200a and stacked layers 200b in a core region. The stack layer 200b may include gate layers and spacer layers alternately stacked in a direction perpendicular to the substrate 200 a. The stacked layer 200b has a first array common-source 211 and a second array common-source 212 perpendicular to the substrate 200a and extending in the first direction D1. The first array common source 211 and the second array common source 212 are located on the substrate 200a and penetrate through the stack layer 200 b. The upper surfaces of the first and second array

common sources

211 and 212 may be substantially coplanar with the upper surface of the stack layer 200 b. The stacked layer 200b also has a channel hole 270 perpendicular to the substrate 200a, in which the memory layer and the channel layer are sequentially disposed in a direction from outside to inside along the channel hole 270. Here, the memory layer may include a charge blocking layer, a charge trapping layer, and a tunneling layer. The upper portion of the stacked layer 200b also has a top select gate 260 extending along the first direction D1. The top select gate 260 is located between the first array common source 211 and the second array common source 212.

The three-dimensional memory 200 may further include a first conductive pattern 220 on the first array common source 211 and the second array common source 212. That is, the first conductive pattern 220 is located above the stacked layer 200 b.

The first conductive pattern 220 may be divided into an array common source node connection region 220a and a bit line region 220b according to their functions. The array common-source connection region 220a is located between two bit line regions 220 b. The array common-source connection region 220a includes a plurality of connection lines 221 electrically connected with the first array common-source 211 and/or the second array common-source 212, and a plurality of dummy connection lines 222 not electrically connected with the first array common-source 211 and the second array common-source 212. The bit line region 220b includes a plurality of bit lines 223. The connection line 221, the dummy connection line 222, and the bit line 223 all extend in the second direction D2. In some embodiments, the first direction D1 and the second direction D2 are perpendicular to each other.

Referring to fig. 6-9, a plurality of dummy connection lines 222 are disposed on both sides of the plurality of connection lines 221, and a plurality of bit lines 223 are disposed on both sides of the plurality of dummy connection lines 222. That is, the dummy connection line 222 is located between the connection line 221 and the bit line 223, and the dummy connection line 222 is disposed adjacent to the bit line 223.

Although one dummy connection line 222 is disposed on both sides of the plurality of connection lines 221 in the three-dimensional memory 200 shown in fig. 6 to 9, it is understood that at least one of both sides of the plurality of connection lines 221 may be provided with a plurality of dummy connection lines 222. For example, two dummy connection lines 222 are provided on one side of the plurality of connection lines 221, and one dummy connection line 222 is provided on the other side. The number of dummy connection lines 222 provided on both sides of the plurality of connection lines 221 may be the same or different.

In some embodiments, some of the connection lines 221 of the plurality of connection lines 221 simultaneously electrically connect the first array common-source 211 and the second array common-source 212 to simultaneously provide current to the first array common-source 211 and the second array common-source 212.

In some embodiments, the connection line 221 may be electrically connected to the first array common-source 211 and/or the second array common-source 212 through the conductive contact block 250. In some embodiments, the connection line 221 may be electrically connected to the first array common-source 211 and/or the second array common-source 212 through the conductive plug 240. It is to be understood that the connection line 221 may also be electrically connected to the first array common-source 211 and/or the second array common-source 212 by other means, which is not limited by the present invention.

In some embodiments, at least two connection lines 221 of the plurality of connection lines 221 are electrically connected to each other. As shown in fig. 6, the second connection line 221, the fourth connection line 221 and the sixth connection line 221 are connected to each other from left to right. In fig. 7-9, these interconnecting connection lines 221 are shown by means of framing the connection lines 221.

It is noted that although only two array common-sources, the first array common-source 211 and the second array common-source 212, are shown in fig. 6-10, it is understood that the three-dimensional memory 200 may include one or more array common-sources. For embodiments where the three-dimensional memory 200 includes only one array common source, the connection line 221 is electrically connected to the array common source. For embodiments in which the three-dimensional memory 200 includes a plurality of array common sources, one connection line 221 of the plurality of connection lines 221 may be electrically connected to one of the plurality of array common sources, or may be electrically connected to at least two of the plurality of array common sources at the same time.

The dummy connection lines 222 are disposed on both sides of the connection lines 221 in the three-dimensional memory 200 of this embodiment, so as to reduce the risk of short circuit between the connection lines 221 and the bit lines 223. In addition, since the dummy connection lines 222 are disposed on both sides of the plurality of connection lines 221, process window protection is provided when the first conductive patterns 220 are formed using a Self-aligned Double Patterning (SADP) process or the like.

Fig. 11 is a partial top view of a three-dimensional memory 300 according to some embodiments of the invention. Fig. 12 is a partial cross-sectional view of the three-dimensional memory 300 shown in fig. 11 taken along line a-a. Fig. 13 is a partial cross-sectional view of the three-dimensional memory 300 shown in fig. 11 taken along line B-B. Fig. 14 is a partial cross-sectional view of the three-dimensional memory 300 shown in fig. 11 taken along line C-C. Fig. 15 is a partial cross-sectional view of the three-dimensional memory 300 shown in fig. 11 taken along line D-D. Referring collectively to fig. 11-15, three-dimensional memory 300 may include substrate 300a and stacked layers 300b in a core region. The stack layer 300b may include gate layers and spacer layers alternately stacked in a direction perpendicular to the substrate 300 a. The stacked layer 300b has a first array common-source 311 and a second array common-source 312 perpendicular to the substrate 300a and extending along the first direction D1. The first array common-source 311 and the second array common-source 312 are located on the substrate 300a and penetrate through the stack layer 300 b. The upper surfaces of the first array common-source 311 and the second array common-source 312 may be substantially coplanar with the upper surface of the stacked layer 300 b. The stacked layer 300b also has a channel hole 370 perpendicular to the substrate 300a, in which the memory layer and the channel layer are sequentially disposed along the channel hole 370 from the outside to the inside. Here, the memory layer may include a charge blocking layer, a charge trapping layer, and a tunneling layer. The upper portion of the stacked layer 300b also has a top select gate 360 extending along the first direction D1. The top select gate 360 is located between the first array common-source 311 and the second array common-source 312.

The three-dimensional memory 300 may further include a first conductive pattern 320 and a second conductive pattern 330 on the stacked layer 300 b. The second conductive pattern 330 is positioned between the first conductive pattern 320 and the stacked layer 300 b. That is, the second conductive pattern 330 is located on the first and second array

common sources

311 and 312, and the first conductive pattern 320 is located on the second conductive pattern 330.

The first conductive pattern 320 may be divided into an array common source node connection region 320a and a bit line region 320b according to their functions. The array common-source connection region 320a is located between two bit line regions 320 b. The array common-source connection region 320a includes a plurality of connection lines 321 electrically connected to the first array common-source 311 and/or the second array common-source 312, and a plurality of dummy connection lines 322 electrically disconnected from the first array common-source 311 and the second array common-source 312. The bit line region 320b includes a plurality of bit lines 323. The connection line 321, the dummy connection line 322, and the bit line 323 all extend in the second direction D2. In some embodiments, the first direction D1 and the second direction D2 are perpendicular to each other.

Referring to fig. 11-14, a plurality of dummy connection lines 322 are disposed at both sides of the plurality of connection lines 321, and a plurality of bit lines 323 are disposed at both sides of the plurality of dummy connection lines 322. That is, the dummy connection line 322 is located between the connection line 321 and the bit line 323, and the dummy connection line 322 is disposed adjacent to the bit line 323.

In some embodiments, at least two connection lines 321 of the plurality of connection lines 321 are electrically connected to each other. As shown in fig. 11, the second connecting line 321, the fourth connecting line 321 and the sixth connecting line 321 are connected to each other from left to right. In fig. 12-14, these interconnecting connection lines 321 are shown by means of a frame outside the connection lines 321.

The connection line 321 may be electrically connected to the first array common-source 311 and/or the second array common-source 312 through the second conductive pattern 330. Specifically, the second conductive pattern 330 includes one or more first conductive lines 331 electrically connected to the connection line 321. The first conductive line 331 may extend in the second direction D2.

In some embodiments, some of the first conductive lines 331 are connected to each other. As shown in fig. 11, the second first conductive line 331 and the second first conductive line 331 are connected to each other from left to right. In fig. 12-14, these interconnected first conductors 331 are shown by means of a frame outside the first conductors 331.

In some embodiments, one first conductive line 331 is electrically connected to a plurality of connection lines 321. That is, a plurality of connection lines 321 may be connected to the same first conductive line 331. For example, one first conductive line 331 electrically connects two adjacent connection lines 321. As shown in fig. 11, the second connection line 321 and the third connection line 321 are electrically connected to the same first conductive line 331, and the fourth connection line 321 and the fifth connection line 321 are electrically connected to the same first conductive line 331, as counted from left to right.

In some embodiments, the plurality of connection lines 321 are respectively connected to the plurality of first conductive lines 331 through the plurality of conductive plugs 340. That is, each of the conductive plugs 340 is connected to one of the connection lines 321 and one of the first conductive lines 331, respectively. It is understood that one conductive plug 340 may also connect a plurality of connection lines 321, which is not limited by the present invention. Likewise, one conductive plug 340 may be connected to a plurality of first conductive lines 331.

In some embodiments, the first conductive line 331 may be connected to the first array common-source 311 and/or the second array common-source 312 through the conductive contact block 350. That is, one or more conductive contact blocks 350 are connected to the first conductive line 331 and the first array common-source 311, respectively, and/or one or more conductive contact blocks 350 are connected to the first conductive line 331 and the second array common-source 312, respectively.

In some embodiments, the second conductive pattern 330 may include one or more second conductive lines 332 connected with the bit lines 323. The second wire 332 may extend in the second direction D2. In some embodiments, the second wire 332 may also electrically connect the channel layer in the channel hole 370. For example, one second wire 332 may electrically connect the channel layers in two channel holes adjacent in the second direction D2.

In some embodiments, the bit lines 323 are connected to the second conductive lines 332 through conductive plugs 340, respectively. That is, each of the conductive plugs 340 is connected to one bit line 323 and one second conductive line 332, respectively. It is understood that one conductive plug 340 may also connect a plurality of bit lines 323, which is not a limitation of the present invention. Likewise, one conductive plug 340 may connect a plurality of second conductive lines 332.

In some embodiments, the second conductive pattern 330 may include one or more third conductive lines 333 electrically connected to the dummy connection lines 322. In some embodiments, one dummy connection line 322 may electrically connect a plurality of third conductive lines 333. In some embodiments, one third wire 333 may electrically connect the plurality of dummy connection lines 322. In some embodiments, the dummy connection line 322 may be connected to the third conductive line 333 through the conductive plug 340. That is, the conductive plugs 340 connect the dummy connection lines 322 and the third conductive lines 333, respectively.

Although one dummy connection line 322 is disposed on both sides of the plurality of connection lines 321 in the three-dimensional memory 300 shown in fig. 11 to 14, it is understood that at least one of both sides of the plurality of connection lines 321 may be provided with a plurality of dummy connection lines 322. For example, two dummy connection lines 322 are provided on one side of the plurality of connection lines 321, and one dummy connection line 322 is provided on the other side. The number of dummy connection lines 322 provided on both sides of the plurality of connection lines 321 may be the same or different.

In some embodiments, some of the connection lines 321 of the plurality of connection lines 321 electrically connect the first array common-source electrode 311 and the second array common-source electrode 312 at the same time to provide current to the first array common-source electrode 311 and the second array common-source electrode 312 at the same time.

It is noted that although only two array common-sources, the first array common-source 311 and the second array common-source 312, are shown in fig. 11-15, it is understood that the three-dimensional memory 300 may include one or more array common-sources. For embodiments where the three-dimensional memory 300 includes only one array common source, the connection line 321 is electrically connected to the array common source. For embodiments in which the three-dimensional memory 300 includes a plurality of array common sources, one connection line 321 of the plurality of connection lines 321 may be electrically connected to one of the plurality of array common sources, or may be simultaneously electrically connected to at least two of the plurality of array common sources.

In the three-dimensional memory 300 of the present embodiment, the dummy connection lines 322 are disposed on two sides of the connection lines 321, so as to reduce the risk of short circuit between the connection lines 321 and the bit lines 323. In addition, since the dummy connection lines 322 are disposed on both sides of the plurality of connection lines 321, process window protection is provided when the first conductive patterns 320 are formed using a Self-aligned Double Patterning (SADP) process or the like.

Figure 16 is a partial top view of a three-dimensional memory 400 according to some embodiments of the inventions. Fig. 17 is a partial cross-sectional view of the three-dimensional memory 400 shown in fig. 16 taken along line a-a. Fig. 18 is a partial cross-sectional view of the three-dimensional memory 400 shown in fig. 16 taken along line B-B. Fig. 19 is a partial cross-sectional view of the three-dimensional memory 400 shown in fig. 16 taken along line C-C. Fig. 20 is a partial cross-sectional view of the three-dimensional memory 400 shown in fig. 16 taken along line D-D. As shown in conjunction with fig. 16-20, three-dimensional memory 400 may include substrate 400a and stacked layers 400b in a core region. The stack layer 400b may include gate layers and spacer layers alternately stacked in a direction perpendicular to the substrate 400 a. The stacked layer 400b has a first array common-source 411 and a second array common-source 412 perpendicular to the substrate 400a and extending in the first direction D1. The first array common-source 411 and the second array common-source 412 are located on the substrate 400a and penetrate through the stack layer 400 b. The upper surfaces of the first and second array

common sources

411 and 412 may be substantially coplanar with the upper surface of the stack layer 400 b. The stacked layer 400b also has a channel hole 470 perpendicular to the substrate 400a, in which the memory layer and the channel layer are sequentially disposed along the channel hole 470 from the outside to the inside. Here, the memory layer may include a charge blocking layer, a charge trapping layer, and a tunneling layer. The upper portion of the stacked layer 400b also has a top select gate 460 extending along the first direction D1. The top select gate 460 is located between the first array common-source 411 and the second array common-source 412.

The three-dimensional memory 400 may further include a first conductive pattern 420 and a second conductive pattern 430 on the stacked layer 400 b. The second conductive pattern 430 is positioned between the first conductive pattern 420 and the stacked layer 400 b. That is, the second conductive pattern 430 is located on the first and second array

common sources

411 and 412, and the first conductive pattern 420 is located on the second conductive pattern 430.

The first conductive pattern 420 may be divided into an array common source node connection region 420a and a bit line region 420b according to their functions. The array common-source connection region 420a is located between two bit line regions 420 b. The array common-source connection region 420a includes one connection line 421 electrically connected to the first array common-source 411 and/or the second array common-source 412, and a plurality of dummy connection lines 422 electrically unconnected to the first array common-source 411 and the second array common-source 412. The bit line region 420b includes a plurality of bit lines 423. In some embodiments, the width of the connection line 421 is greater than the width of the dummy connection line 422 and/or the bit line 423. The connection line 421, the dummy connection line 422, and the bit line 423 all extend in the second direction D2. In some embodiments, the first direction D1 and the second direction D2 are perpendicular to each other.

Referring to fig. 16-20 in combination, a plurality of dummy connection lines 422 are located at both sides of the connection line 421, and a plurality of bit lines 423 are located at both sides of the plurality of dummy connection lines 422. That is, the dummy connection line 422 is located between the connection line 421 and the bit line 423, and the dummy connection line 422 is disposed adjacent to the bit line 423.

The connection line 421 may be electrically connected to the first array common-source 411 and/or the second array common-source 412 through the second conductive pattern 430. Specifically, the second conductive pattern 430 includes one or more first conductive lines 431 electrically connected to the connection lines 421. The first conductive line 431 may extend in the second direction D2.

In some embodiments, some of the plurality of first conductive lines 431 are interconnected to each other. As shown in fig. 16, the second first conductive line 431 and the second first conductive line 431 are connected to each other from left to right. In fig. 17-19, these interconnected first conductors 431 are shown by framing the first conductors 431.

The connection line 421 may be connected to a plurality of first conductive lines 431, or may be connected to one first conductive line 431. In some embodiments, the connection lines 421 are respectively connected to the first conductive lines 431 through the conductive plugs 440. That is, each of the conductive plugs 440 connects the connection line 421 and one of the first conductive lines 431, respectively. It is understood that one conductive plug 440 may connect a plurality of first conductive lines 431.

In some embodiments, the first conductive line 431 may be connected to the first array common-source 411 and/or the second array common-source 412 through a conductive contact block 450. That is, one or more conductive contact blocks 450 are connected to the first conductive line 431 and the first array common source 411, respectively, and/or one or more conductive contact blocks 450 are connected to the first conductive line 431 and the second array common source 412, respectively.

In some embodiments, the second conductive pattern 430 may include one or more second conductive lines 432 connected to the bit lines 423. The second wire 432 may extend in the second direction D2. In some embodiments, the second wire 432 may also electrically connect the channel layer in the channel hole 470. For example, one second wire 432 may electrically connect the channel layers in two channel holes adjacent in the second direction D2.

In some embodiments, the plurality of bit lines 423 are respectively connected to the plurality of second conductive lines 432 through a plurality of conductive plugs 440. That is, each of the conductive plugs 440 is connected to one bit line 323 and one second conductive line 432, respectively. It is understood that one conductive plug 440 may also connect a plurality of bit lines 423, which is not a limitation of the present invention. Likewise, one conductive plug 440 may connect a plurality of second conductive lines 432.

In some embodiments, the second conductive pattern 430 may include one or more third conductive lines 433 electrically connected to the dummy connection lines 422. In some embodiments, one dummy connection line 422 may electrically connect a plurality of third conductive lines 433. In some embodiments, one third wire 433 may electrically connect a plurality of dummy connection lines 422. In some embodiments, the dummy connection line 422 may be connected to the third conductive line 433 through a conductive plug 440. That is, the conductive plugs 440 are connected to the dummy connection lines 422 and the third conductive lines 433, respectively.

Although one dummy connection line 422 is disposed on both sides of the connection line 421 in the three-dimensional memory 400 shown in fig. 16 to 19, it is understood that at least one of both sides of the connection line 421 may be provided with a plurality of dummy connection lines 422. For example, two dummy connection lines 422 are disposed on one side of the connection line 421, and one dummy connection line 422 is disposed on the other side. The number of dummy connection lines 422 provided on both sides of the connection line 421 may be the same or different.

In some embodiments, the connection line 421 may electrically connect the first array common-source 411 and the second array common-source 412 at the same time to provide current to the first array common-source 411 and the second array common-source 412 at the same time.

It is noted that although only two array common-sources, the first array common-source 411 and the second array common-source 412, are shown in fig. 16-20, it is understood that the three-dimensional memory 400 may include one or more array common-sources. For embodiments where the three-dimensional memory 400 includes only one array common source, the connection line 421 is electrically connected to the array common source. For embodiments in which the three-dimensional memory 400 includes a plurality of array common sources, the connection line 421 may be electrically connected to one of the plurality of array common sources, or may be electrically connected to at least two of the plurality of array common sources.

The dummy connection lines 422 are disposed on both sides of the connection lines 421 in the three-dimensional memory 400 of this embodiment, so as to reduce the risk of short circuit between the connection lines 421 and the bit lines 423. In addition, since the dummy connection lines 422 are disposed on both sides of the connection line 421, process window protection is provided when the first conductive pattern 420 is formed using a Self-aligned Double Patterning (SADP) process or the like.

Compared to the three-dimensional memory 300 shown in fig. 11-15, the width of the connection line 421 in the first conductive pattern 420 of the three-dimensional memory 400 is greater than the sum of the widths of the plurality of connection lines 321, and the connection line 421 has a lower resistance.

Other details of the three-dimensional memory device, such as word line connection regions, peripheral interconnects, etc., are not material to the present invention and will not be described further herein.

In the context of the present invention, the three-dimensional memory device may be a 3D flash memory, such as a 3D NAND flash memory.

This application uses specific words to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.

Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.

Claims

1. A three-dimensional memory, comprising:

one or more array common sources extending in a first direction on a substrate; and

a first conductive pattern on the one or more array common sources comprising:

one or more connection lines extending in a second direction electrically connecting at least one of the array common sources;

dummy connection lines extending in the second direction and located at both sides of the one or more connection lines; and

a plurality of bit lines extending in the second direction and located on both sides of the dummy connection line in a direction away from the one or more connection lines.

2. The three-dimensional memory according to claim 1, wherein the dummy connection line is adjacent to the bit line.

3. The three-dimensional memory according to claim 1, wherein at least one side of the one or more connection lines is provided with a plurality of the dummy connection lines.

4. The three-dimensional memory according to claim 1, wherein the one or more connecting lines simultaneously electrically connect at least two of the plurality of array common sources.

5. The three-dimensional memory according to claim 1, wherein at least two of the plurality of connection lines are connected to each other.

6. The three-dimensional memory according to claim 1, further comprising a second conductive pattern between the one or more array common sources and the first conductive pattern, at least one of the connection lines being electrically connected to at least one of the array common sources through the second conductive pattern.

7. The three-dimensional memory according to claim 6, wherein the second conductive pattern comprises one or more first conductive lines extending in the second direction, the one or more first conductive lines electrically connecting the connection lines.

8. The three-dimensional memory according to claim 7, wherein at least two of the plurality of first conductive lines are connected to each other.

9. The three-dimensional memory according to claim 7, wherein at least one of the first conductive lines electrically connects a plurality of the connection lines.

10. The three-dimensional memory according to claim 9, wherein at least one of the first conductive lines electrically connects two adjacent connection lines.

11. The three-dimensional memory according to claim 6, wherein the second conductive pattern comprises one or more second conductive lines extending in the second direction, electrically connecting the bit lines.

12. The three-dimensional memory according to claim 11, wherein at least one of the second conductive lines further electrically connects channel layers in two channel holes adjacent in the second direction.

13. The three-dimensional memory according to claim 6, wherein the second conductive pattern comprises one or more third conductive lines extending in the second direction, electrically connecting the dummy connection lines.

14. The three-dimensional memory according to claim 13, wherein at least one of the dummy connection lines connects a plurality of the third conductive lines.

15. The three-dimensional memory according to claim 6, further comprising a plurality of conductive plugs connected to the first conductive patterns and the second conductive patterns, respectively.

16. The three-dimensional memory according to claim 7, further comprising a plurality of conductive contact blocks respectively connected to the first conductive line and the array common source.

17. The three-dimensional memory according to claim 1, wherein the first conductive pattern includes one of the connection lines, and a width of the connection line is greater than a width of the dummy connection line and/or the bit line.

18. The three-dimensional memory according to claim 1, wherein the first direction and the second direction are perpendicular to each other.