CN109326636B - Cell structure and power device - Google Patents
Cell structure and power device Download PDFInfo
- Publication number
- CN109326636B CN109326636B CN201811199560.9A CN201811199560A CN109326636B CN 109326636 B CN109326636 B CN 109326636B CN 201811199560 A CN201811199560 A CN 201811199560A CN 109326636 B CN109326636 B CN 109326636B
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- wells
- upper sides
- grid oxide
- oxide layer
- epitaxial layer
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- 210000004027 cell Anatomy 0.000 claims description 16
- 210000003850 cellular structure Anatomy 0.000 claims description 4
- 230000006872 improvement Effects 0.000 abstract description 6
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000004075 alteration Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a cell structure and a power device. The cell comprises an N-epitaxial layer and two P-wells symmetrically arranged at the upper sides of the N-epitaxial layer at intervals, wherein the upper sides in the two P-wells are respectively provided with a first N+ well, the upper sides of the inner ends of the P-wells, the upper sides in the first N+ wells and the upper sides of the N-epitaxial layer between the two P-wells are covered with a first grid oxide layer, the upper sides of the first grid oxide layer are provided with first polycrystalline strips, the P-wells at the two sides in the middle of the first polycrystalline strips are respectively and transversely provided with two second N+ wells at intervals, the upper sides in the two second N+ wells and the upper sides of the P-wells between the two second N+ wells are transversely provided with second grid oxide layers, and the upper sides of the second grid oxide layers are provided with second polycrystalline strips. The invention can guide the trend of the avalanche current through structural improvement, thereby improving the avalanche resistance. After improvement by the scheme, the avalanche resistance of the device can be generally improved by more than 50 percent.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to a cell structure and a power device.
Background
VDMOS (Vertical Double-diffused Metal Oxide Semicondector) devices have the advantages of high switching speed, small switching loss, high input impedance, high voltage driving, high frequency and the like, and are widely accepted and used in the market. In VDMOS device application, an important index is avalanche resistance, and the higher the avalanche resistance is, the wider the application range is. There are two types of cell designs that are currently common, one is a grid design and the other is a square design, both of which have limited avalanche resistance. With the continuous development of VDMOS devices, the structure of the VDMOS devices is continuously improved, and avalanche resistance is improved as much as possible, so that the impact resistance is improved.
Disclosure of Invention
The invention aims at overcoming the defects in the prior art and provides a cell structure and a power device.
In order to achieve the above object, in a first aspect, the present invention provides a cellular structure, including an N-epitaxial layer and two P-wells symmetrically disposed at an upper side of the N-epitaxial layer at intervals, wherein the upper sides in the two P-wells are respectively provided with a first n+ well, the upper sides of the inner ends of the P-wells, the upper sides in the first n+ wells and the upper sides of the N-epitaxial layer between the two P-wells are covered with a first gate oxide layer, the upper sides of the first gate oxide layer are provided with first polycrystalline strips, the P-wells on two sides in the middle of the first polycrystalline strips are respectively and transversely provided with two second n+ wells at intervals, the upper sides in the two second n+ wells and the upper sides of the P-wells between the two second n+ wells are transversely provided with second gate oxide layers, and the upper sides of the second gate oxide layer are provided with second polycrystalline strips.
Preferably, the width of the second poly-strip is 2 to 4 μm.
Preferably, the first and second polycrystalline strips have a thickness ofTo/>
In a second aspect, the invention also provides a power device comprising a plurality of cells as claimed in any one of claims 1 to 3, said plurality of cells being arranged and connected in an array.
Preferably, the spacing between the second poly-strips of two longitudinally adjacent connected cells is 15 to 20 μm.
The beneficial effects are that: the invention can guide the trend of the avalanche current through structural improvement, thereby improving the avalanche resistance. After improvement by the scheme, the avalanche resistance of the device can be generally improved by more than 50 percent.
Drawings
FIG. 1 is a schematic perspective view of a cellular structure according to an embodiment of the present invention;
FIG. 2 is a front view of a cellular structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a partial structure of a power device according to an embodiment of the present invention;
fig. 4 is a bottom view A-A of fig. 3.
Detailed Description
The invention will be further illustrated by the following drawings and specific examples, which are carried out on the basis of the technical solutions of the invention, it being understood that these examples are only intended to illustrate the invention and are not intended to limit the scope of the invention.
As shown in fig. 1 to 4, the embodiment of the present invention provides a cell structure including an N-epitaxial layer 1 and two P-wells 2 disposed on the upper side of the N-epitaxial layer 1, the two P-wells 2 being disposed symmetrically with respect to the axial centerline of the N-epitaxial layer 1, and the two P-wells 2 being spaced apart from each other by a portion of the N-epitaxial layer 1. The upper sides in the two P-wells 2 are respectively provided with a first N+ well 3, the upper sides in the inner ends of the P-wells 2, the upper sides in the first N+ wells 3 and the upper sides of the N-epitaxial layers 1 between the two P-wells 2 are covered with a first grid oxide layer 4, the upper sides of the first grid oxide layers 4 are provided with first polycrystalline strips 5, the P-wells 2 on the two sides in the middle of the first polycrystalline strips 5 are respectively and transversely provided with two second N+ wells 6 at intervals, the upper sides in the two second N+ wells 6 and the upper sides of the P-wells 2 between the two second N+ wells 6 are transversely provided with second grid oxide layers 7, and the upper sides of the second grid oxide layers 7 are provided with second polycrystalline strips 8. The thicknesses of the first poly-crystal bar 5 and the second poly-crystal bar 8 are preferablyTo/>The width of the second poly-strip 8 is critical, and if the poly-strip is too wide, the P-wells 2 are separated to form individual P-wells, and the effect of improving avalanche resistance is not good if the poly-strip is too narrow, as in the case of square cells, and the width of the second poly-strip 8 is preferably 2 to 4 μm.
During manufacturing, a gate oxide layer is formed on an N-epitaxial layer, the thickness of the gate oxide layer is determined according to the requirement of the threshold voltage of the device, polycrystal is deposited on the gate oxide layer, a P-well injection region, a first polycrystalline strip and a second polycrystalline strip are formed through the process steps of polycrystal doping, photoetching, engraving and the like, boron is injected into the P-well injection region, a P-well is formed through high-temperature annealing, an N+ well injection region is formed through N+ well photoetching, and an N+ well is formed through a high-temperature annealing process after arsenic element or phosphorus element is injected into the N+ well.
As shown in fig. 3 to 4, the present invention also provides a power device, which includes a plurality of the above-mentioned cells, and the plurality of cells are arranged and connected in an array. The distance d between the second polycrystalline strips 8 of two longitudinally adjacent connected elementary cells is preferably 15 to 20 μm, which ensures that the position of the current path leading to avalanche resistance is sufficient.
In summary, the invention can guide the trend of the avalanche current through the structural improvement, thereby improving the avalanche resistance. After improvement by the scheme, the avalanche resistance of the device can be generally improved by more than 50 percent.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that other parts not specifically described are within the prior art or common general knowledge to a person of ordinary skill in the art. Modifications and alterations may be made without departing from the principles of this invention, and such modifications and alterations should also be considered as being within the scope of the invention.
Claims (4)
1. The cell structure is characterized by comprising an N-epitaxial layer and two P-wells symmetrically arranged at the upper sides of the N-epitaxial layer at intervals, wherein a first N+ well is respectively arranged at the upper sides in the two P-wells, a first grid oxide layer is covered at the upper sides of the inner ends of the P-wells, the upper sides of the first N+ wells and the upper sides of the N-epitaxial layer between the two P-wells, a first polycrystalline strip is arranged at the upper sides of the first grid oxide layer, two second N+ wells are respectively arranged at the upper sides of the P-wells at the middle of the first polycrystalline strip at intervals in a transverse direction, a second grid oxide layer is transversely arranged at the upper sides of the inner upper sides of the two second N+ wells and the upper sides of the P-wells between the two second N+ wells, a second polycrystalline strip is arranged at the upper sides of the second grid oxide layer, and a structure formed by the first grid oxide layer and the first polycrystalline strip is perpendicular to a structure formed by the second grid oxide layer and the second polycrystalline strip;
the width of the second poly-strip is 2 to 4 μm so that the P-well at the lower side thereof is not blocked.
2. The cellular structure of claim 1, wherein the first and second poly strips have a thickness of 4000 a to 10000 a.
3. A power device comprising a plurality of cell structures according to any one of claims 1 to 2, said plurality of cell structures being arranged and connected in an array.
4. A power device according to claim 3, wherein the spacing between the second poly-strips of two longitudinally adjacent connected cells is 15 to 20 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811199560.9A CN109326636B (en) | 2018-10-16 | 2018-10-16 | Cell structure and power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811199560.9A CN109326636B (en) | 2018-10-16 | 2018-10-16 | Cell structure and power device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109326636A CN109326636A (en) | 2019-02-12 |
| CN109326636B true CN109326636B (en) | 2024-06-21 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811199560.9A Active CN109326636B (en) | 2018-10-16 | 2018-10-16 | Cell structure and power device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109326636B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102694028A (en) * | 2011-03-23 | 2012-09-26 | 株式会社东芝 | Power semiconductor device |
| CN209087848U (en) * | 2018-10-16 | 2019-07-09 | 南京华瑞微集成电路有限公司 | A kind of structure cell and power device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000077663A (en) * | 1998-09-02 | 2000-03-14 | Mitsubishi Electric Corp | Field-effect semiconductor device |
| US8072000B2 (en) * | 2009-04-29 | 2011-12-06 | Force Mos Technology Co., Ltd. | Avalanche capability improvement in power semiconductor devices having dummy cells around edge of active area |
| CN104733523A (en) * | 2013-12-19 | 2015-06-24 | 比亚迪股份有限公司 | MOSFET power device and forming method thereof |
| CN110299401A (en) * | 2019-07-25 | 2019-10-01 | 无锡昌德微电子股份有限公司 | A kind of VDMOS and its manufacturing method |
-
2018
- 2018-10-16 CN CN201811199560.9A patent/CN109326636B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102694028A (en) * | 2011-03-23 | 2012-09-26 | 株式会社东芝 | Power semiconductor device |
| CN209087848U (en) * | 2018-10-16 | 2019-07-09 | 南京华瑞微集成电路有限公司 | A kind of structure cell and power device |
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| Publication number | Publication date |
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| CN109326636A (en) | 2019-02-12 |
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