CN109324535A - Control unit, programmable controller - Google Patents
Control unit, programmable controller Download PDFInfo
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- CN109324535A CN109324535A CN201810694455.6A CN201810694455A CN109324535A CN 109324535 A CN109324535 A CN 109324535A CN 201810694455 A CN201810694455 A CN 201810694455A CN 109324535 A CN109324535 A CN 109324535A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
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- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Programmable Controllers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The purpose of the present invention is be able to carry out the processing of timing corresponding with the expanding element of connection.The CPU (21) of control unit (10) has clock generation unit (21b).Clock generation unit (21b) generates the reference clock signal as CPU (21) movement benchmark.CPU (21) is based on the reference clock generated by clock generation unit (21b), generates the 1st clock timing and the 2nd clock timing.CPU (21) determines the expanding element connecting with control unit (10).CPU (21) switches to the 1st clock timing in the case where only expanding element (41,42) connect, and switches to the 2nd clock timing in the case where only expanding element (51,52) or expanding element (41,42,51,52) connect.
Description
Technical field
The present invention relates to control units, programmable controller.
Background technique
In the past, the measurement that programmable controller (PLC) is controlled, carried out by various sensors for the sequence of external equipment
Deng.It is different according to the function of being needed using purpose of cyclelog.Therefore, it is proposed to which connection has on the control unit
The programmable controller for having the expanding element of function corresponding with purpose is used and constituting (referring for example to patent document 1).Control
Unit and expanding element connected to it constitute the bus for receiving and dispatching control command, data.Control unit is via bus and expands
Unit communication is opened up, expanding element is controlled.
Existing technical literature
Patent document
Patent document 1: No. 4214657 bulletins of Japanese Patent No.
Summary of the invention
The problem of present invention is to be solved
However, expanding element includes communication, controls the different element of timing in the case where having.In this way, acting timing not
With expanding element and deposit in the case where being connected to 1 control unit, control unit is designed to be able to and attachable expansion
Open up unit communication, that is, the most slow expanding element of timing can be connected, i.e., with fixed timing corresponding with the expanding element of slow timing
It is acted.Therefore, in the cyclelog that the expanding element for the movement for being only capable of high speed is connect with control unit, to control list
The design timing of member is periodically acted slowly.So the processing of control unit is limited by the design of expanding element.
The present invention is to complete in order to solve the above problem, and its purpose is to provide a kind of extension lists that can be carried out and connect
The control unit of the processing of first corresponding timing, programmable controller.
The solution to the problem
The control unit to solve the above problems has the 1st connector and the 2nd connector, and the 1st expanding element is via the described 1st
Connector is connected along the 1st direction, so that the 1st bus extends along the 1st direction, and the 2nd expanding element is via described
2nd connector is connect along with the 2nd direction in the 1st contrary direction, so that the 2nd bus is prolonged along the 2nd direction
It stretches, described control unit includes reference clock generation unit, generates reference clock；1st clock generating unit is based on the base
Punctual clock generates the 1st clock timing corresponding with the 1st expanding element；2nd clock generating unit is based on the reference clock
Generate 2nd clock timing corresponding and different with the 1st clock timing from the 2nd expanding element；Clock switching unit is cut
Change the 1st clock timing and the 2nd clock timing；Judging unit is connected, determines the 1st expanding element and the described 2nd
The connection of expanding element；Individual processing unit, the judgement based on the connection judging unit is as a result, being only connected with described the
In the case where 1 expanding element, the 1st clock timing is switched to using the clock switching unit and executes processing, connecting
In the case where stating the 1st expanding element and the 2nd expanding element or being only connected with the 2nd expanding element, using it is described when
Clock switch unit switches to the 2nd clock timing and executes processing.
According to this constitution, being based on reference clock, the 1st clock timing and the 2nd clock timing are generated.Moreover, determining the 1st extension
The connection of unit and the 2nd expanding element, based on judgement as a result, the 1st clock timing of switching and the 2nd clock timing.Therefore, only
In the case that 1st expanding element connects, due to being acted with the 1st clock timing, it is able to carry out the processing of high speed.In addition,
Only the 2nd expanding element or the 1st connected with the 2nd expanding element in the case where, when due to the slower than the 1st clock timing the 2nd
Therefore clock timed activity can reliably handle the expanding element of connection.
It is the universal serial bus for carrying out serial communication that above-mentioned control unit, which is preferably the 1st bus, and the 2nd bus is
Carry out the parallel bus of parallel communications.
According to this constitution, can make to communicate the different expanding element of form and connect and located with control unit with depositing
Reason.
Above-mentioned control unit preferably includes internal bus；Interface portion is connected to the internal bus and the described 2nd
Between connector；Memory portion is connect with the internal bus, is accessed by the processing unit, and the processing unit is via institute
It states internal bus and accesses the memory portion, and connect via the internal bus and interface portion control via the described 2nd
The 2nd expanding element of device connection is connect, the 2nd clock timing is set according to the interface portion and the memory portion
's.
According to this constitution, being able to carry out in the control unit with the memory portion being connect with internal bus to storage
The access in device portion and the processing for the expanding element being connect with control unit.
Above-mentioned control unit is preferably the 1st clock generating unit with the timing equal with the reference clock timing
The 1st clock timing is generated, the 2nd clock generating unit is based on the reference clock, by the 1st clock timing frequency dividing
Timing generates the 2nd clock timing.
For example, needing to generate the additional of the 1st clock timing in the case where having with reference clock different timing
Circuit.In addition, being needed attached in the case where having in the case where not dividing the 1st clock timing in order to generate the 2nd clock timing
It is powered on road.In contrast, according to the above configuration, it is fixed that the 1st clock can be easily produced in the case where not needing adjunct circuit
When and the 2nd clock timing.
The programmable controller to solve the above problems includes: the control unit with the 1st connector and the 2nd connector；With
1st expanding element of the 1st connector connection and at least one of the 2nd expanding element being connect with the 2nd connector,
1st expanding element is connected via the 1st connector along the 1st direction, so that the 1st bus be made to prolong in the 1st direction
It stretches, the 2nd expanding element is connect via the 2nd connector along with the 2nd direction in the 1st contrary direction, from
And extending the 2nd bus in the 2nd direction, described control unit includes reference clock generation unit, generates reference clock；
1st clock generating unit generates the 1st clock timing corresponding with the 1st expanding element based on the reference clock；When the 2nd
Clock generation unit is generated corresponding and different with the 1st clock timing from the 2nd expanding element based on the reference clock
2nd clock timing；Clock switching unit switches the 1st clock timing and the 2nd clock timing；Judging unit is connected, is sentenced
The connection of fixed 1st expanding element and the 2nd expanding element；Individual processing unit is based on the connection judging unit
Judgement as a result, in the case where being only connected with 1 expanding element, when switching to the 1st using the clock switching unit
Clock timing simultaneously executes processing, is being connected with the 1st expanding element and the 2nd expanding element or is only being connected with the described 2nd
In the case where expanding element, the 2nd clock timing is switched to using the clock switching unit and executes processing.
According to this constitution, being based on reference clock, the 1st clock timing and the 2nd clock timing are generated.Moreover, determining the 1st extension
The connection of unit and the 2nd expanding element, based on judgement as a result, the 1st clock timing of switching and the 2nd clock timing.Therefore, only
In the case that 1st expanding element connects, due to being acted with the 1st clock timing, it is able to carry out the processing of high speed.In addition,
Only the 2nd expanding element or the 1st connected with the 2nd expanding element in the case where, when due to the slower than the 1st clock timing the 2nd
Therefore clock timed activity can reliably handle the expanding element of connection.
It is the universal serial bus for carrying out serial communication that above-mentioned programmable controller, which is preferably the 1st bus, and the described 2nd is total
Line is the parallel bus for carrying out parallel communications.
According to this constitution, can make to communicate the different expanding element of form and connect and located with control unit with depositing
Reason.
Above-mentioned programmable controller is preferably described control unit and also includes internal bus；Interface portion, in the inside
It is connected between bus and the 2nd connector；Memory portion is connect with the internal bus, is accessed by the processing unit, institute
It states processing unit and accesses the memory portion via the internal bus, and via the internal bus and the interface portion control
The 2nd expanding element connected via the 2nd connector is made, the 2nd clock timing is according to the interface portion and institute
It states memory portion and sets.
According to this constitution, being able to carry out in the control unit with the memory portion being connect with internal bus to storage
The access in device portion and the processing for the expanding element being connect with control unit.
Above-mentioned programmable controller is preferably the 1st clock generating unit with equal with the reference clock timing
Timing generates the 1st clock timing, and the 2nd clock generating unit is based on the reference clock, by the 1st clock timing point
The timing of frequency generates the 2nd clock timing.
For example, needing to generate the additional of the 1st clock timing in the case where having with reference clock different timing
Circuit.In addition, being needed attached in the case where having in the case where not dividing the 1st clock timing in order to generate the 2nd clock timing
It is powered on road.In contrast, according to the above configuration, it is fixed that the 1st clock can be easily produced in the case where not needing adjunct circuit
When and the 2nd clock timing.
The effect of invention
Control unit according to the present invention, programmable controller, can with timing corresponding with the expanding element of connection into
Row processing.
Detailed description of the invention
Fig. 1 is the summary composition figure of programmable controller.
Fig. 2 (a) (b) is the perspective view of control unit.
Fig. 3 (a) (b) is the explanatory diagram of expanding element.
Fig. 4 is the explanatory diagram for showing the electric structure of programmable controller.
Fig. 5 is the explanatory diagram for showing the processing of control unit.
Fig. 6 (a)~(c) is the Action Specification figure of programmable controller.
Fig. 7 (a) (b) is the synoptic diagram for showing the Inner Constitution example of control unit.
The explanation of label
10 ... control units, 12 ... connectors (the 1st connector), 14 ... connectors (the 2nd connector), 21 ... CPU (benchmark
Clock generating unit, the 1st clock generating unit, the 2nd clock generating unit, clock switching unit, processing unit), 22 ... is internal
Bus, 23 ... memory portions, 24 ... interface portions (portion IF), 41,42 ... expanding elements, 51,52 ... expanding elements, BU1 ... the 1st are total
Line, the 2nd bus of BU2 ....
Specific embodiment
In the following, being illustrated to each embodiment.
In addition, the constituent element amplification in attached drawing is shown for ease of understanding in the case where having.It is constituted in the case where having
The dimensional ratios of element are different from the element in actual element or other accompanying drawings.
As shown in Figure 1, programmable controller (PLC) includes 1 control unit 10；More (being 2 in Fig. 1) extensions are single
Member 41,42；And more (being 2 in Fig. 1) expanding elements 51,52.
Control unit 10 is shaped generally as cuboid.Expanding element 41,42 is disposed in one in the two sides of control unit 10
Side (being right side in present embodiment).Expanding element 51,52 is disposed in the other side (this embodiment party in the two sides of control unit 10
In formula be left side), i.e., relative to control unit 10 expanding element 41,42 opposite side.
As shown in Fig. 2 (b), control unit 10 has the connector 12 exposed from the opening 11a of right side 11.In addition, such as
Shown in Fig. 2 (a), control unit 10 has the connector 14 exposed from the opening 13a of left side 13.
As shown in Fig. 3 (b), expanding element 41 has from left side connector 41a outstanding.Connector 41a can be with
The connector 12 of control unit 10 shown in Fig. 2 (b) connects.In addition, expanding element 41 right side have with shown in Fig. 2 (b)
Control unit 10 the same connector 41b of connector 12.Expanding element 42 and expanding element 41 equally have connector
42a、42b。
The connector 41a of expanding element 41 is connect with the connector 12 of control unit 10 shown in Fig. 2 (b), will be extended
The connector 42a of unit 42 is connect with the connector 41b of expanding element 41.As a result, as shown in Figure 1, on the right side of control unit 10
Side is connected with expanding element 41,42.
As shown in Fig. 3 (a), expanding element 51 has from right side connector 51a outstanding.Connector 51a can be with
The connector 14 of control unit 10 shown in Fig. 2 (a) connects.In addition, expanding element 41 left side have with shown in Fig. 2 (a)
Control unit 10 the same connector 51b of connector 14.Expanding element 52 and expanding element 51 equally have connector
52a、52b。
The connector 51a of expanding element 51 is connect with the connector 14 of control unit 10 shown in Fig. 2 (a), will be extended
The connector 52a of unit 52 is connect with the connector 51b of expanding element 51.As a result, as shown in Figure 1, on a left side for control unit 10
Side is connected with expanding element 51,52.
In control unit 10, such as the quantity of expanding element that can be connect respectively with right side and left side according to design setting.
For example, being at best able to 3 expanding elements of connection on the right side of control unit 10.In addition, in the left side of control unit 10, at most
4 expanding elements can be connected.
As shown in Fig. 7 (a), control unit 10 has printed board 15,16.Connector 12 is installed in printed board 15,
Connector 14 is installed in printed board 16.Two printed boards 15,16 are interconnected by connecting component 17.Connecting component 17
Base mother daughter board connector, flexible cable etc. in this way.In addition, printed board needs not be 2, connector 12,14 is towards different
Direction.So being also possible to the control unit 10a with 1 printed board 18 as shown in Fig. 7 (b).That is, control is single
Member 10,10a include the connector 12 for being mounted on a face of printed board 15,18；It is mounted on the another of printed board 16,18
The connector 14 in a face.
Next, illustrating the electric structure of control unit 10.
As shown in figure 4, control unit 10 has 1 central calculation processing apparatus (hereinafter referred to as CPU) 21 as control unit.
CPU21 has memory 21a.The operation program of CPU21 is stored in memory 21a, the ephemeral data of operation program, various is set
Fixed number according to etc..CPU21 has clock generation unit 21b.When clock generation unit 21b generates the movement base reference of reference for becoming CPU21
Clock signal.CPU21 is acted and the clock timing based on reference clock, executes the operation program of memory 21a.
Control unit 10 has memory portion 23, which connect via internal bus 22 with CPU21.Memory
Portion 23 is, for example, SRAM (Static Random Access Memory, static random access memory).Internal bus 22 wraps
Contain: transmitting the address bus for specifying the address signal of address；Transmit the data/address bus of data；Transmitting control signal (such as
RD (Read is read), WR (Write writes), CS (Chip Select, chip selection), OE (Output Enable enables output)
Deng) control bus.CPU21 accesses memory portion 23 via internal bus 22, and the write-in of data is carried out for memory portion 23
And reading.
CPU21 is connect with connector 12.The connector 41a of expanding element 41 is connected in connector 12.In the extension list
The connector 41b of member 41 is connected with the connector 42a of expanding element 42.The control unit 10 and expanding element 41 that connect in this way,
42 form the 1st bus B U1.
Expanding element 41,42 has control unit 41c, the 42c connecting respectively with the 1st bus B U1.1st bus B U1 is serial
Bus.Signal of the CPU21 for the 1st bus B U1 transmitting-receiving serial communication.The signal of serial communication includes expansion clock signal
(ESCK), SOD serial output data (ESO), expansion serial input data (ESI) are expanded.CPU21 is via the 1st bus B U1 and extension
Control unit 41c, 42c serial communication of unit 41,42.For example, CPU21 is sent out via the 1st bus B U1 to each control unit 41c, 42c
Send order, the data of processing.In addition, CPU21 via the 1st bus B U1 receive sent from each control unit 41c, 42c data,
State.
As shown in figure 4, control unit 10 has interface portion (the hereinafter referred to as portion IF) 24.In the present embodiment, the portion IF 24
It is connect via internal bus 22 with CPU21.
The portion IF 24 is connect with connector 14.The connector 51a of expanding element 51 is connected in connector 14.In the extension list
The connector 51b of member 51 is connected with the connector 52a of expanding element 52.The control unit 10 and expanding element 51 that connect in this way,
52 form the 2nd bus B U2.
Expanding element 51,52 has control unit 51c, the 52c connecting respectively with the 2nd bus B U2.The portion IF 24 is bus
Interface, for receiving and dispatching various signals between the CPU21 of control unit 10 and control unit 51c, 52c of each expanding element 51,52
(address signal, data, control signal).Moreover, the 2nd bus B U2 is parallel bus, comprising transmit respectively address signal, data,
Control the signal wire of signal.That is, the CPU21 of control unit 10 is same as access of the control unit 10 for memory portion 23, visit
Ask control unit 51c, 52c of expanding element 51,52.
As described above, the 1st bus B U1 is universal serial bus, the 2nd bus B U2 is parallel bus.Use the string of the 1st bus B U1
The communication speed of parallel communications of the communication speed than using the 2nd bus B U2 of row communication is fast.For example, fast being suitable for communication speed
Expanding element clock timing under, the expanding element slow relative to communication speed, clock timing is too fast and cannot handle.It is another
Aspect is only connected with the fast expanding element of communication speed when being fixed as being suitable for the clock timing of the slow expanding element of communication speed
In the case where, it cannot quickly handle the expanding element.Therefore, CPU21, which has, adjusts movement use according to the expanding element of connection
The function of clock timing.
Specifically, CPU21 generates the 1st clock timing and the 2nd based on the reference clock generated by clock generation unit 21b
Clock timing.1st clock timing is adapted for constituting the clock timing of the expanding element 41,42 of the 1st bus B U1, the 2nd clock timing
It is adapted for constituting the clock timing of the expanding element 51,52 of the 2nd bus B U2.CPU21 make reference clock become 1/2m times (m=0,
1, the 1st clock timing 2 ...), is generated.In addition, CPU21 makes the 1st 1/2n times of clock timing (n=0,1,2 ...), the is generated
2 clock timings.For example, when CPU21 generates the 1st of timing (frequency identical with reference clock: m=0) identical as reference clock
Clock timing.In addition, CPU21 is based on reference clock, the timing of the 1st clock timing frequency dividing (such as 2 frequency dividing: n=1) is generated the
2 clock timings.
Moreover, CPU21 determines the expanding element connecting with control unit 10.The judgement of expanding element can for example pass through company
Whether the scheduled terminal for connecing device 12,14 is in an open state to carry out.For example, expanding element is in the circuit of signal output,
With the pull-up resistor and transistor connecting with predetermined terminal, level (the L electricity of terminal is changed using the on-off of transistor
Flat, H level) and output data.In this case, can determine whether the terminal is open shape according to scheduled terminal level
Whether state connects expanding element.
Control unit 10 has input unit 25 and output section 26.Input unit 25 and output section 26 are arranged to the function from unit
Energy.
Control unit 10 has power supply unit 27.Operation voltage needed for power supply unit 27 generates the movement of control unit 10.Separately
Outside, power supply unit 27 is to 41,42,51, the 52 supply action voltage of expanding element connecting with control unit 10.
Next, whether connection status of the CPU21 according to expanding element, i.e. expanding element connect with 2 connectors 12,14
It connects, is the 1st clock timing or the 2nd clock timing by movement exchange-column shift.
(A) it is connected with expanding element in connector 12, is not connected with having the case where expanding element in connector 14.
In this case, CPU21 and the fast expanding element 41,42 of communication speed are consistent, will movement exchange-column shift to the 1st when
Clock timing.
(B) it is not connected with having expanding element in connector 12, the case where connector 14 is connected with expanding element.
In this case, CPU21 and the slow expanding element 51,52 of communication speed are consistent, will movement exchange-column shift to the 2nd when
Clock timing.
(C) the case where connector 12 and connector 14 are connected with expanding element.
In this case, CPU21 and the slow expanding element 51,52 of communication speed are consistent, will movement exchange-column shift to the 2nd when
Clock timing.
(D) it is not connected with having the case where expanding element in connector 12 and connector 14.
In this case, clock timing, the i.e. movement exchange-column shift to the 1st clock timing that CPU21 can act the present apparatus.
Moreover, CPU21 handles the expanding element with the clock timing connection after switching.
The control unit 10 of present embodiment has the memory portion 23 connecting with internal bus 22.As described above, at this
Internal bus 22 is connected with the portion IF 24 for connecting expanding element 51,52.So the 2nd clock timing is based on via the portion IF
24 carry out parallel communications expanding element 51,52 access and for memory portion 23 access and set.
Fig. 5 shows the process flow of CPU21.
Firstly, CPU21 determines the connection (step S1) of expanding element.
Next, CPU21 carries out the switching (step S2) of clock timing.
Moreover, CPU21 carries out the setting (step S3) of channel number to the expanding element of connection.Channel number is for example being schemed
In 1, relative to the expanding element 51,52 connecting with left side, " 1 ", " 2 " are successively set from the unit close to control unit 10.
In addition, successively setting the channel number of " 1 "~" 4 " in the case where 4 expanding elements are connect with left side.In addition, in Fig. 1,
Relative to the expanding element 41,42 connecting with right side, " 5 ", " 6 " are successively set from the unit close to control unit 10.In addition,
In the case that 3 expanding elements are connect with right side, the channel number of " 5 "~" 7 " is successively set.
Moreover, clock timing of the CPU21 according to setting, successively executes step S4~step S11 processing.Firstly, CPU21
Executing channel number is that " 0 " (is illustrated as " CH0 ".In the following, equally being shown about channel number) from unit processing (step
Rapid S4).From the processing that the processing of unit is for input unit 25 and output section 26 shown in Fig. 4.Next, CPU21 is successively held
Row is for channel number " 1 "~" 7 " processing (step S5~step S11).In addition, in the present embodiment, in expanding element
51,52 setting channel number " 1 ", " 2 " sets channel number " 5 ", " 6 " in expanding element 41,42.So CPU21 is in step
In S5, processing is executed for expanding element 51, in step s 6, processing is executed for expanding element 52.Further, CPU21 exists
In step S9, processing is executed for expanding element 41, in step slo, processing is executed for expanding element 42.In addition, about
The channel number not set, such as can also carry out skipping the processing of processing or connection confirmation.In addition, about above-mentioned setting
Channel number expanding element, confirmation can be attached in each processing.Moreover, passing through connection confirmation discovery connection
In the case where state change, it can also be appropriately carried out and show mistake in display unit (not shown), light error light, to upper
The processing such as device notification error.
(effect)
Next, illustrating the effect of above-mentioned programmable controller.
As shown in Fig. 6 (a), programmable controller includes control unit 10；The extension being connect with the right side of control unit 10
Unit 41,42.Control unit 10 and expanding element 41,42 constitute the 1st bus B U1 shown in Fig. 4.The CPU21 of control unit 10
(referring to Fig. 4) the 1st clock timing of setting.Utilize the 1st clock timing, high speed access expanding element 41,42.
As shown in Fig. 6 (b), programmable controller includes control unit 10, the extension connecting with the left side of control unit 10
Unit 51,52.Control unit 10 and expanding element 51,52 constitute the 2nd bus B U2 shown in Fig. 4.The CPU21 of control unit 10
(referring to Fig. 4) the 2nd clock timing of setting.Utilize the 2nd clock timing, reliable access expanding element 51,52.
As shown in Fig. 6 (c), programmable controller includes control unit 10；The extension being connect with the right side of control unit 10
Unit 41,42；The expanding element 51,52 being connect with the left side of control unit 10.Control unit 10 and expanding element 41,42 are constituted
1st bus B U1 shown in Fig. 4.Control unit 10 and expanding element 51,52 constitute the 2nd bus B U2 shown in Fig. 4.In the situation
Under, CPU21 (referring to Fig. 4) the 2nd clock timing of setting of control unit 10.Using the 2nd clock timing, in communication speed difference
Expanding element 41,42 and expanding element 51,52 and deposit in the programmable controller that connect, reliably access expanding element
41、42、51、52。
As previously discussed, according to the present embodiment, effect below is obtained.
(1) CPU21 of control unit 10 has clock generation unit 21b.Clock generation unit 21b is generated as the dynamic of CPU21
Make the reference clock signal of benchmark.CPU21 based on the reference clock generated by clock generation unit 21b, generate the 1st clock timing and
2nd clock timing.CPU21 determines the expanding element connecting with control unit 10.CPU21 is connected in only expanding element 41,42
In the case where switch to the 1st clock timing, in the feelings that only expanding element 51,52 or expanding element 41,42,51,52 connect
The 2nd clock timing is switched under condition.
So in the case where connecting and composing expanding element 41,42 of the 1st bus B U1, due to the 1st clock timing into
Action is made, and therefore, is able to carry out the processing of high speed.In addition, in the expanding element 51,52 for connecting and composing the 2nd bus B U2 or expanding
In the case where opening up unit 41,42,51,52, due to being acted with 2nd clock timing slower than the 1st clock timing, Neng Gouke
By the expanding element of ground processing connection.
(2) the 1st bus B U1 are the universal serial bus for carrying out serial communication, and the 2nd bus B U2 is the parallel of progress parallel communications
Bus.Thus it is possible to which the different expanding element 41,42,51,52 of form will be communicated and connect and carry out with control unit 10 with depositing
Processing.
(3) control unit 10 includes internal bus 22；22 connector 14 of internal bus and between the portion IF 24 that connects；
The memory portion 23 being connect with internal bus 22.CPU21 accesses memory portion 23 via internal bus 22, and controls via interior
The expanding element 51 that portion's bus 22 and the portion IF 24 are connect with connector 14；The expanding element 52 being connect with the expanding element 51.
CPU21 sets the 2nd clock timing according to the portion IF 24 and memory portion 23.So having the storage connecting with internal bus 22
In the control unit 10 in device portion 23, the expanding element that is able to carry out the access to memory portion 23 and is connect with control unit 10
51,52 processing.
(4) CPU21 makes reference clock become 1/2m times (m=0,1,2 ...), generates the 1st clock timing.In addition, CPU21
Make the 1st 1/2n times of clock timing (n=0,1,2 ...), generates the 2nd clock timing.For example, CPU21 is generated and reference clock
1st clock timing of identical timing (frequency identical with reference clock: m=0).In addition, CPU21 is based on reference clock, it will
The timing of 1st clock timing frequency dividing (such as 2 frequency dividing: n=1) generates the 2nd clock timing.
For example, needing to generate the additional of the 1st clock timing in the case where having with reference clock different timing
Circuit.In addition, being needed attached in the case where having in the case where not dividing the 1st clock timing in order to generate the 2nd clock timing
It is powered on road.Therefore, in the present embodiment, the 1st clock timing can be easily produced in the case where not needing adjunct circuit
With the 2nd clock timing.
In addition, the respective embodiments described above can also be implemented by form below.
For the above embodiment, the 1st clock timing and the 2nd clock timing can also be suitably set.For example, when by benchmark
The frequency dividing of clock 2 divides reference clock 3 to set the 2nd clock timing to set the 1st clock timing.It sets, can also obtain in this way
To effect same as the above embodiment.
In the above-described embodiment, it is connected with memory portion 23 and the portion IF 24 in internal bus 22, but constitutes and is also possible to
Memory portion 23 and the portion IF 24 are connect with mutually different internal bus.It sets, can also obtain same with above embodiment in this way
The effect of sample.
For the above embodiment, the maximum for the expanding element connecting with the left side of control unit 10 can also be suitably changed
Number of units.Alternatively, it is also possible to suitably change the maximum number of units for the expanding element connecting with the right side of control unit 10.
For the above embodiment, at least one of input unit 25 shown in Fig. 4 and output section 26 also be can be omitted.
It for the above embodiment, can also be with the suitably additional such as network connection, storage of control unit 10 shown in Fig. 4
The other functions such as card.
For the above embodiment, the channel number relative to expanding element can also be suitably changed.For example, in Fig. 4,
Channel number " 1 ", " 2 " can be set for the expanding element 41,42 that connect with the right side of control unit 10, with control unit
The expanding element 51,52 of 10 left side connection sets channel number " 4 ", " 5 ".Furthermore it is possible in expanding element 41,42,51,52
Set channel number " 1 ", " 2 ", " 3 ", " 4 " (or expanding element 51,52,41,42 set channel number " 1 ", " 2 ", " 3 ",
“4”)。
For the above embodiment, reference clock can be divided (more than 2 frequency dividings) and generates the 1st clock timing.In addition,
Reference clock can also be divided and divide above for 3 and generate the 2nd clock timing.
For the above embodiment, reference clock can be doubled and (makes 2n times of frequency (n=0,1,2 ...) or more) simultaneously
Generate the 1st clock timing.Alternatively, it is also possible to which reference clock is doubled and generates the 2nd clock timing.
For the above embodiment, reference clock can be doubled and generates the 1st clock timing, and reference clock is divided
Frequency simultaneously generates the 2nd clock timing.Furthermore it is possible to which reference clock is divided and generates the 1st clock timing, and make reference clock times
Increase and generates the 2nd clock timing.
It for the above embodiment, can also be by the 1st bus and the 2nd bus as the serial total of progress serial communication
Line.Alternatively, it is also possible to the parallel bus by the 1st bus and the 2nd bus as progress parallel communications.
Claims (8)
1. a kind of control unit, there is the 1st connector and the 2nd connector, the 1st expanding element via the 1st connector along
The connection of 1st direction extends to the 1st bus along the 1st direction, and the 2nd expanding element is via the 2nd connector edge
Connect with the 2nd direction in the 1st contrary direction and extend along the 2nd direction to the 2nd bus, the control is singly
Member includes
Reference clock generation unit generates reference clock；
1st clock generating unit generates the 1st clock timing corresponding with the 1st expanding element based on the reference clock；
2nd clock generating unit, based on the reference clock generate it is corresponding with the 2nd expanding element and with the 1st clock
Periodically the 2nd different clock timing；
Clock switching unit switches the 1st clock timing and the 2nd clock timing；
Judging unit is connected, determines the connection of the 1st expanding element and the 2nd expanding element；
Individual processing unit, the judgement based on the connection judging unit is as a result, being only connected with the 1st expanding element
In the case of, the 1st clock timing is switched to using the clock switching unit and executes processing, and being connected with, the 1st extension is single
First and described 2nd expanding element or in the case where being only connected with the 2nd expanding element, utilizes the clock switching unit
It switches to the 2nd clock timing and executes processing.
2. control unit as described in claim 1,
1st bus is the universal serial bus for carrying out serial communication,
2nd bus is the parallel bus for carrying out parallel communications.
3. control unit as claimed in claim 1 or 2, comprising:
Internal bus；
Interface portion is connected between the internal bus and the 2nd connector；
Memory portion is connect with the internal bus, is accessed by the processing unit,
The processing unit accesses the memory portion via the internal bus, and via the internal bus and described connects
Oral area controls the 2nd expanding element connected via the 2nd connector,
2nd clock timing is set according to the interface portion and the memory portion.
4. such as described in any item control units of claims 1 to 3,
1st clock generating unit generates the 1st clock timing with the timing equal with the reference clock timing,
2nd clock generating unit is based on the reference clock, and the timing of the 1st clock timing frequency dividing is generated described the
2 clock timings.
5. a kind of programmable controller, includes: the control unit with the 1st connector and the 2nd connector；It is connect with the described 1st
1st expanding element of device connection and at least one of the 2nd expanding element being connect with the 2nd connector,
1st expanding element is connected via the 1st connector along the 1st direction, to make the 1st bus in the 1st side
To extension,
2nd expanding element is connect via the 2nd connector along with the 2nd direction in the 1st contrary direction, from
And extend the 2nd bus in the 2nd direction,
Described control unit includes
Reference clock generation unit generates reference clock；
1st clock generating unit generates the 1st clock timing corresponding with the 1st expanding element based on the reference clock；
2nd clock generating unit, based on the reference clock generate it is corresponding with the 2nd expanding element and with the 1st clock
Periodically the 2nd different clock timing；
Clock switching unit switches the 1st clock timing and the 2nd clock timing；
Judging unit is connected, determines the connection of the 1st expanding element and the 2nd expanding element；
Individual processing unit, the judgement based on the connection judging unit is as a result, being only connected with the 1st expanding element
In the case of, the 1st clock timing is switched to using the clock switching unit and executes processing, and being connected with, the 1st extension is single
First and described 2nd expanding element or in the case where being only connected with the 2nd expanding element, is cut using the clock switching unit
It shifts to the 2nd clock timing and executes processing.
6. programmable controller as claimed in claim 5
1st bus is the universal serial bus for carrying out serial communication,
2nd bus is the parallel bus for carrying out parallel communications.
7. such as programmable controller described in claim 5 or 6,
Described control unit also includes
Internal bus；
Interface portion is connected between the internal bus and the 2nd connector；
Memory portion is connect with the internal bus, is accessed by the processing unit,
The processing unit accesses the memory portion via the internal bus, and via the internal bus and described connects
Oral area controls the 2nd expanding element connected via the 2nd connector,
2nd clock timing is set according to the interface portion and the memory portion.
8. such as described in any item programmable controllers of claim 5~7,
1st clock generating unit generates the 1st clock timing with the timing equal with the reference clock timing,
2nd clock generating unit is based on the reference clock, and the timing of the 5th clock timing frequency dividing is generated described the
2 clock timings.
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| JP2017-147929 | 2017-07-31 | ||
| JP2017147929A JP7095961B2 (en) | 2017-07-31 | 2017-07-31 | Control unit, programmable controller |
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| CN109324535B CN109324535B (en) | 2021-05-14 |
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| CN109324535B (en) | 2021-05-14 |
| JP2019028758A (en) | 2019-02-21 |
| JP7095961B2 (en) | 2022-07-05 |
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