CN109300921B - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN109300921B CN109300921B CN201811362562.5A CN201811362562A CN109300921B CN 109300921 B CN109300921 B CN 109300921B CN 201811362562 A CN201811362562 A CN 201811362562A CN 109300921 B CN109300921 B CN 109300921B
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- 239000000758 substrate Substances 0.000 title claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 175
- 229910052751 metal Inorganic materials 0.000 claims abstract description 175
- 239000010410 layer Substances 0.000 description 51
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4822—Beam leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02373—Layout of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02375—Top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The utility model provides an array substrate, includes display area and non-display area, the non-display area includes that the multiunit fan-out walks the line, every group fan-out is walked including the overlapping setting and is walked the first metal that is insulating each other, the second metal is walked line and third metal and is walked line, the second metal is walked line and is included first overlap portion and second overlap portion, first overlap portion and fan-out walk the first metal of line and walk line partial overlap with the third metal of line, second overlap portion and adjacent another group fan-out walk the first metal of line and walk line partial overlap with the third metal. The array substrate can realize narrow frames and improve the display quality. The invention also relates to a display panel.
Description
Technical Field
The invention relates to the technical field of displays, in particular to an array substrate and a display panel.
Background
Fig. 1a is a schematic structural diagram of a conventional array substrate. Fig. 1b is a schematic structural diagram of another conventional array substrate. As shown in fig. 1a and 1b, the array substrate has an effective display area and a non-display area. The effective display area is provided with a plurality of pixels to form a pixel array, and the non-display area is provided with a peripheral circuit. Each pixel generally includes at least a Thin Film Transistor (TFT) and a pixel electrode to which the TFT is connected, and is surrounded by two adjacent scan lines and two adjacent data lines. The scanning lines and the data lines extend from the effective display area to the non-display area and are electrically connected with the driving chip through the peripheral circuit of the non-display area. The peripheral line is formed by concentrating one end of the peripheral line which connects the scanning line and the data line to the area where the driving chip is located.
Because the metal wires in the fan-out wires are more, the required wire layout space is large, and the frame of the array substrate cannot be narrowed. The first metal layer M1 and the second metal layer M2 are alternately or overlappingly distributed to reduce the wiring space, so that the frame of the array substrate can be reduced, but the frame is limited to be reduced. In addition, the first metal layer M1 and the second metal layer M2 are prone to shift during the interlayer alignment process, which results in an excessive capacitance difference between the layers and affects the display quality.
Disclosure of Invention
In view of this, the present invention provides an array substrate, which can realize a narrow frame and improve display quality.
The utility model provides an array substrate, includes display area and non-display area, the non-display area includes that the multiunit fan-out walks the line, every group fan-out is walked including the overlapping setting and is walked the first metal that is insulating each other, the second metal is walked line and third metal and is walked line, the second metal is walked line and is included first overlap portion and second overlap portion, first overlap portion and fan-out walk the first metal of line and walk line partial overlap with the third metal of line, second overlap portion and adjacent another group fan-out walk the first metal of line and walk line partial overlap with the third metal.
In an embodiment of the invention, the second metal trace further includes a connecting portion, and the connecting portion is connected between the first overlapping portion and the second overlapping portion.
In an embodiment of the present invention, the connecting portion is connected to end portions of the first overlapping portion and the second overlapping portion.
In an embodiment of the invention, the first overlapping portion is parallel to the second overlapping portion, and an overlapping length of the first overlapping portion and the first metal trace and the third metal trace is equal to an overlapping length of the second overlapping portion and the first metal trace and the third metal trace.
In an embodiment of the present invention, the non-display area is provided with a first metal layer, a second metal layer and a third metal layer;
the first metal layer comprises at least two first metal routing lines;
the second metal layer comprises at least one second metal routing;
the third metal layer comprises at least two third metal routing lines.
In an embodiment of the invention, the non-display region is provided with a first insulating layer and a second insulating layer, the first insulating layer is disposed between the first metal layer and the second metal layer, and the second insulating layer is disposed between the second metal layer and the third metal layer.
In an embodiment of the present invention, the array substrate further includes a substrate, the first metal layer is disposed on the substrate, and the first insulating layer is disposed on the first metal layer and the substrate.
In an embodiment of the present invention, the metal line widths of the first metal trace, the second metal trace, and the third metal trace are equal, a distance between the first metal trace and the second metal trace is equal to a distance between the second metal trace and the third metal trace, an overlapping width between the first overlapping portion and the first metal trace is equal to 1/3, and an overlapping width between the first overlapping portion and the third metal trace is equal to 1/3.
In an embodiment of the invention, the display area includes a plurality of signal traces, the non-display area includes a driving chip, and the plurality of fan-out traces are electrically connected between the signal traces and the driving chip.
The invention also provides a display panel comprising the array substrate.
The non-display area of the array substrate comprises a plurality of groups of fan-out wires, each group of fan-out wires comprises a first metal wire, a second metal wire and a third metal wire which are arranged in a stacked mode and are insulated from each other, the second metal wire comprises a first overlapping portion and a second overlapping portion, the first overlapping portion is partially overlapped with the first metal wire and the third metal wire of the fan-out wires, and the second overlapping portion is partially overlapped with the first metal wire and the third metal wire of the other adjacent group of fan-out wires. The area of the non-display area occupied by the fan-out wires can be reduced, the narrow frame is realized, the interlayer capacitance difference caused by OVL offset can be compensated, the RC Loading among the first metal wires, the second metal wires and the third metal wires is effectively reduced, and the display quality is improved.
Drawings
Fig. 1a is a schematic structural diagram of a conventional array substrate.
Fig. 1b is a schematic structural diagram of another conventional array substrate.
Fig. 2 is a schematic front view of an array substrate according to the present invention.
Fig. 3 is a schematic partial cross-sectional view of the array substrate shown in fig. 2 taken along iii-iii.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be further described with reference to the accompanying drawings.
Fig. 2 is a schematic front view of an array substrate according to the present invention. Fig. 3 is a schematic partial cross-sectional view of the array substrate shown in fig. 2 taken along iii-iii. As shown in fig. 2 and 3, the array substrate 100 includes a display region 10 and a non-display region 20.
The display region 10 includes a plurality of signal traces 11, and the plurality of signal traces 11 may include a plurality of scan lines for providing gate driving signals, a plurality of data lines for providing display data signals, and a touch driving signal line for providing touch signals. A plurality of pixels are arranged in the display area 10 to form a pixel array, each pixel includes at least a Thin Film Transistor (TFT) and a pixel electrode to which the TFT is connected, and each pixel is surrounded by two adjacent scan lines and two adjacent data lines.
The non-display area 20 includes a plurality of sets of fan-out traces 21 and driving chips 22. The fan-out trace 21 is electrically connected between the signal trace 11 and the driving chip 22. Each group of fan-out traces 21 includes a first metal trace 212, a second metal trace 213 and a third metal trace 214 that are stacked and insulated from each other, and the second metal trace 213 is located between the first metal trace 212 and the third metal trace 214. Specifically, one end of the first metal trace 212, the second metal trace 213 and the third metal trace 214 is connected to the signal trace 11, and the other end of the first metal trace 212, the second metal trace 213 and the third metal trace 214 is connected to the driving chip 22, and specifically can be electrically connected to the pad of the driving chip 22. For example, referring to fig. 2, one end of the first metal trace 212 is connected to the data line, and the other end of the first metal trace 212 is connected to the driving chip 22; one end of the second metal wire 213 is connected to the data line, and the other end of the second metal wire 213 is connected to the driving chip 22; one end of the third metal trace 214 is connected to the data line, and the other end of the third metal trace 214 is connected to the driving chip 22.
As shown in fig. 3, the array substrate 100 further includes a substrate 23, a first insulating layer 24, and a second insulating layer 25. The plurality of fan-out traces 21 are located on the substrate base plate 23, specifically, a first metal layer M1 is formed on the substrate base plate 23, and at least two first metal traces 212 are formed on the first metal layer M1 by using exposure and development processes; a first insulating layer 24 is arranged on the first metal layer M1, a second metal layer M2 is arranged on the first insulating layer 24, and at least one second metal wire 213 is formed on the second metal layer M2 by adopting an exposure and development process; a second insulating layer 25 is sequentially formed on the second metal layer M2, a third metal layer M3 is disposed on the second insulating layer 25, and at least two third metal traces 214 are formed on the third metal layer M3 by using an exposure and development process, wherein the first insulating layer 24 is located between the first metal layer M1 and the second metal layer M2, and the second insulating layer 25 is located between the second metal layer M2 and the third metal layer M3; a third insulating layer is also formed on the third metal layer M3.
In the present embodiment, the first metal trace 212, the second metal trace 213 and the third metal trace 214 may be made of a metal material (e.g., silver, copper), and their constituent materials may be the same or different from each other.
The first insulating layer 24 is a gate insulating layer, and the material thereof may be silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto, and any common gate insulating layer material may be used; the second insulating layer 25 and the third insulating layer are passivation layers, and the material thereof may be silicon oxide, silicon nitride or organic material.
As shown in fig. 2 and 3, in the present embodiment, the second metal trace 213 includes a first overlapping portion 213a, a second overlapping portion 213b and a connecting portion 213 c. The connection portion 213c is connected between the first overlapping portion 213a and the second overlapping portion 213b, the first overlapping portion 213a partially overlaps the first metal trace 212 and the third metal trace 214 of the fan-out trace 21, and the second overlapping portion 213b partially overlaps the first metal trace 212 and the third metal trace 214 of another adjacent set of fan-out traces 21.
In a preferred embodiment, the first overlapping portion 213a and the second overlapping portion 213b are disposed in a staggered manner, wherein the first overlapping portion 213a overlaps with the second half portion of the first metal trace 212 and the third metal trace 214 (along the length direction of the fan-out trace 21), and the second overlapping portion 213b overlaps with the first half portion of the first metal trace 212 and the third metal trace 214 (along the length direction of the fan-out trace 21).
In a preferred embodiment, the connection portion 213c is connected to the ends of the first and second overlapping portions 213a and 213b, and the connection portion 213c is perpendicular to the first and second overlapping portions 213a and 213 b.
In a preferred embodiment, the first overlapping portion 213a is parallel to the second overlapping portion 213b, and the overlapping length of the first overlapping portion 213a and the first and third metal traces 212 and 214 is equal to the overlapping length of the second overlapping portion 213b and the first and third metal traces 212 and 214.
In a preferred embodiment, the metal line widths of the first metal line 212, the second metal line 213 and the third metal line 214 are equal, the distance between the first metal line 212 and the second metal line 213 is equal to the distance between the second metal line 213 and the third metal line 214, the overlapping width between the first overlapping portion 213a and the second overlapping portion 213b and the first metal line 212 is equal to 1/3 the line width of the first metal line 212, the overlapping width between the first overlapping portion 213a and the second overlapping portion 213b and the third metal line 214 is equal to 1/3 the line width of the third metal line 214, and at this time, the OVL of the first metal line 212, the second metal line 213 and the third metal line 214 is equal to 0 (offset between layers).
The non-display area 20 of the array substrate 100 of the invention includes a plurality of sets of fan-out traces 21, each set of fan-out traces 21 includes a first metal trace 212, a second metal trace 213 and a third metal trace 214 that are disposed in an overlapping manner and insulated from each other, the second metal trace 213 includes a first overlapping portion 213a, a second overlapping portion 213b and a connecting portion 213c, the connecting portion 213c is connected between the first overlapping portion 213a and the second overlapping portion 213b, the first overlapping portion 213a is partially overlapped with the first metal trace 212 and the third metal trace 214 of the fan-out trace 21, and the second overlapping portion 213b is partially overlapped with the first metal trace 212 and the third metal trace 214 of another set of fan-out traces 21 adjacent to each other. The area of the non-display area 20 occupied by the fan-out routing 21 can be reduced, a narrow frame is realized, interlayer capacitance difference caused by OVL offset can be compensated, RC Loading among the first metal routing 212, the second metal routing 213 and the third metal routing 214 is effectively reduced, and the display quality is improved.
The present invention further provides a display panel, which includes the array substrate 100, and please refer to the prior art for the structure and function of the display panel, which is not described herein again.
The present invention is not limited to the specific details of the above-described embodiments, and various simple modifications may be made to the technical solution of the present invention within the technical idea of the present invention, and these simple modifications are within the protective scope of the present invention. The various features described in the foregoing detailed description may be combined in any suitable manner without departing from the scope of the invention. The invention is not described in detail in order to avoid unnecessary repetition.
Claims (10)
1. An array substrate, comprising:
a display area (10);
the non-display area (20) comprises a plurality of groups of fan-out wires (21), each group of fan-out wires (21) comprises a first metal wire (212), a second metal wire (213) and a third metal wire (214) which are arranged in an overlapping mode and are insulated from each other, the second metal wire (213) comprises a first overlapping portion (213a) and a second overlapping portion (213b), the first overlapping portion (213a) is partially overlapped with the first metal wire (212) and the third metal wire (214) of the fan-out wires (21), and the second overlapping portion (213b) is partially overlapped with the first metal wire (212) and the third metal wire (214) of the other adjacent group of fan-out wires (21).
2. The array substrate of claim 1, wherein the second metal trace (213) further comprises a connection portion (213c), and the connection portion (213c) is connected between the first overlapping portion (213a) and the second overlapping portion (213 b).
3. The array substrate of claim 2, wherein the connection portion (213c) is connected to ends of the first overlapping portion (213a) and the second overlapping portion (213 b).
4. The array substrate of claim 2, wherein the first overlapping portion (213a) is parallel to the second overlapping portion (213b), and an overlapping length of the first overlapping portion (213a) and the first metal trace (212) and the third metal trace (214) is equal to an overlapping length of the second overlapping portion (213b) and the first metal trace (212) and the third metal trace (214).
5. The array substrate according to claim 1, wherein the non-display area (20) is provided with a first metal layer, a second metal layer and a third metal layer;
the first metal layer comprises at least two first metal traces (212);
the second metal layer comprises at least one second metal trace (213);
the third metal layer includes at least two third metal traces (214).
6. The array substrate of claim 5, wherein the non-display region (20) is provided with a first insulating layer (24) and a second insulating layer (25), the first insulating layer (24) is disposed between the first metal layer and the second metal layer, and the second insulating layer (25) is disposed between the second metal layer and the third metal layer.
7. The array substrate of claim 6, further comprising a substrate base plate (23), wherein the first metal layer is disposed on the substrate base plate (23), and wherein the first insulating layer (24) is disposed on the first metal layer and the substrate base plate (23).
8. The array substrate according to claim 6, wherein the metal line widths of the first metal trace (212), the second metal trace (213) and the third metal trace (214) are equal, the distance between the first metal trace (212) and the second metal trace (213) is equal to the distance between the second metal trace (213) and the third metal trace (214), the overlapping width between the first overlapping portion (213a) and the second overlapping portion (213b) and the first metal trace (212) is equal to 1/3, and the overlapping width between the first overlapping portion (213a) and the second overlapping portion (213b) and the third metal trace (214) is equal to 1/3 the line width of the third metal trace (214).
9. The array substrate of claim 1, wherein the display area (10) comprises a plurality of signal traces (11), the non-display area (20) comprises a driving chip (22), and a plurality of sets of the fan-out traces (21) are electrically connected between the signal traces (11) and the driving chip (22).
10. A display panel comprising the array substrate according to any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811362562.5A CN109300921B (en) | 2018-11-15 | 2018-11-15 | Array substrate and display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811362562.5A CN109300921B (en) | 2018-11-15 | 2018-11-15 | Array substrate and display panel |
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| CN109300921A CN109300921A (en) | 2019-02-01 |
| CN109300921B true CN109300921B (en) | 2020-09-01 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110928085B (en) * | 2019-11-26 | 2021-01-15 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| CN110837820B (en) * | 2019-11-26 | 2022-05-31 | 厦门天马微电子有限公司 | Array substrate and display panel |
| CN111367129A (en) * | 2020-04-09 | 2020-07-03 | 深圳市华星光电半导体显示技术有限公司 | Fan-out routing structure and display panel |
| CN114609836B (en) * | 2022-03-07 | 2023-07-25 | 武汉华星光电技术有限公司 | Display panel and display device |
| CN114883348A (en) * | 2022-06-07 | 2022-08-09 | 武汉华星光电半导体显示技术有限公司 | Display panel and display terminal |
| WO2024087192A1 (en) * | 2022-10-28 | 2024-05-02 | 京东方科技集团股份有限公司 | Display module and preparation method therefor, and display apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105158998A (en) * | 2015-09-14 | 2015-12-16 | 深圳市华星光电技术有限公司 | Liquid crystal display device and display panel thereof |
| CN106444182A (en) * | 2016-10-31 | 2017-02-22 | 厦门天马微电子有限公司 | Array substrate and display panel |
| CN106647071A (en) * | 2017-02-15 | 2017-05-10 | 上海中航光电子有限公司 | Array substrate, display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101676810B1 (en) * | 2014-10-30 | 2016-11-16 | 삼성전자주식회사 | Semiconductor device and display driver IC including the same and display device including the same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105158998A (en) * | 2015-09-14 | 2015-12-16 | 深圳市华星光电技术有限公司 | Liquid crystal display device and display panel thereof |
| CN106444182A (en) * | 2016-10-31 | 2017-02-22 | 厦门天马微电子有限公司 | Array substrate and display panel |
| CN106647071A (en) * | 2017-02-15 | 2017-05-10 | 上海中航光电子有限公司 | Array substrate, display panel and display device |
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