CN109300787B - 回收碳面极性碳化硅衬底的方法 - Google Patents

回收碳面极性碳化硅衬底的方法 Download PDF

Info

Publication number
CN109300787B
CN109300787B CN201811104661.3A CN201811104661A CN109300787B CN 109300787 B CN109300787 B CN 109300787B CN 201811104661 A CN201811104661 A CN 201811104661A CN 109300787 B CN109300787 B CN 109300787B
Authority
CN
China
Prior art keywords
silicon carbide
carbide substrates
polar
carbon face
face polarity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201811104661.3A
Other languages
English (en)
Other versions
CN109300787A (zh
Inventor
倪贤锋
范谦
何伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Han Hua Semiconductors Co Ltd
Original Assignee
Suzhou Han Hua Semiconductors Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Han Hua Semiconductors Co Ltd filed Critical Suzhou Han Hua Semiconductors Co Ltd
Priority to CN201811104661.3A priority Critical patent/CN109300787B/zh
Publication of CN109300787A publication Critical patent/CN109300787A/zh
Application granted granted Critical
Publication of CN109300787B publication Critical patent/CN109300787B/zh
Priority to US16/562,452 priority patent/US10763174B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
    • H01L21/7813Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate leaving a reusable substrate, e.g. epitaxial lift off
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • H01L21/30612Etching of AIIIBV compounds
    • H01L21/30617Anisotropic liquid etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02079Cleaning for reclaiming
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • H01L21/30612Etching of AIIIBV compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Weting (AREA)

Abstract

本申请提出一种回收碳面极性碳化硅衬底的方法,包括:提供一外延结构,所述外延结构包括待回收的碳面极性碳化硅衬底、以及依次层叠于所述碳化硅衬底上的氮面极性的氮化镓缓冲层、势垒层和氮面极性的氮化镓沟道层;采用湿法刻蚀去除所述氮面极性的氮化镓沟道层、势垒层和氮面极性的氮化镓缓冲层;清洗所述碳面极性碳化硅衬底并吹干。本申请所提出的碳面极性的碳化硅衬底的回收方法,能够加快去除外延结构的速率,加快了回收效率,并且无需使用抛光和研磨工艺,不会减少碳化硅衬底的厚度,降低了后续工艺的难度。

Description

回收碳面极性碳化硅衬底的方法
技术领域
本发明涉及半导体技术领域,特别是涉及一种回收碳面极性碳化硅衬底的方法。
背景技术
近年来,基于氮化物的HEMT(高电子迁移率晶体管)已经在移动,卫星,雷达通信等领域得到应用。在用于氮化物材料沉积的主流衬底(例如蓝宝石,硅,碳化硅等)中,由于碳化硅的制造成本较高且市场上的供应有限,所以碳化硅衬底的成本通常是其他类型衬底的10倍以上。并且,虽然碳化硅衬底具有很高的成本,但是目前主要的高性能HEMT器件均需要使用碳化硅衬底,碳化硅衬底由于对HEMT器件性能方面的高要求而无法被其它衬底代替。因此,在测试之后或氮化物材料沉积失败后对碳化硅衬底进行回收具有显著的经济效益。
回收可再用于HEMT外延的碳化硅衬底在技术上非常具有挑战性,因为回收的碳化硅衬底不仅需要表面光滑而且衬底表面不能有任何微量的化学污染。目前常规的碳化硅回收技术涉及机械减薄和抛光,由于各种抛光剂与研磨液的使用,很容易引入化学污染。此外,常规回收方法由于使用研磨与抛光工艺会使碳化硅衬底的厚度变薄,而衬底厚度变化会引起随后的氮化物外延参数(例如外延过程中衬底表面温度)的变化,进而影响最终器件的性能。
发明内容
本申请提出一种回收碳面极性碳化硅衬底的方法,包括:
提供一外延结构,所述外延结构包括待回收的碳面极性碳化硅衬底、以及依次层叠于所述碳化硅衬底上的氮面极性的氮化镓缓冲层、势垒层和氮面极性的氮化镓沟道层;
采用湿法刻蚀去除所述氮面极性的氮化镓沟道层、势垒层和氮面极性的氮化镓缓冲层;
清洗所述碳面极性碳化硅衬底并吹干。
在一个实施例中,所述湿法刻蚀采用10%-50%的KOH溶液。
在一个实施例中,在所述KOH溶液中加入乙二醇,并将溶液加热到100℃以上。
在一个实施例中,所述湿法刻蚀的溶液为氢氧化钠、磷酸、柠檬酸中的任一种或者多种的混合溶液。
在一个实施例中,所述湿法刻蚀的速率大于100nm/min。
在一个实施例中,清洗所述碳化硅衬底表面并吹干,具体包括:
使用去离子水清洗所述碳化硅衬底表面;
使用氮气吹干所述碳化硅衬底。
在一个实施例中,在湿法刻蚀过程中,采用UV光照射所述外延结构。
在一个实施例中,所述UV光为波长短于所述氮化镓带隙波长的光波。
本申请所提出的碳面极性的碳化硅衬底的回收方法,能够加快去除外延结构的速率,加快了回收效率,并且无需使用抛光和研磨工艺,不会减少碳化硅衬底的厚度,降低了后续工艺的难度。
附图说明
图1为本申请一个实施例所提出的回收碳化硅衬底方法流程图;
图2为待回收的外延结构的示意图;
图3为碳化硅衬底的示意图。
具体实施方式
以下结合附图和具体实施例对本发明提出的回收碳面极性碳化硅衬底的方法作进一步详细说明。根据下面说明和权利要求书,本发明的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本发明实施例的目的。
请参考图1-图3,本实施例所提出的回收碳化硅衬底的方法包括:
S10:提供一外延结构,所述外延结构包括待回收的碳面极性碳化硅衬底,以及依次位于所述碳化硅衬底上的氮面极性的氮化镓缓冲层、势垒层和氮面极性的氮化镓沟道层。
具体的,请参考图2,所述外延结构包括依次层叠的碳化硅衬底1、氮化镓缓冲层2、势垒层3和氮化镓沟道层4。所述氮化镓缓冲层2的厚度大于1微米,所述势垒层3的厚度为10nm-100nm,所述氮化镓沟道层4的厚度为10nm-100nm。所述碳面极性的碳化硅衬底是指所述碳化硅衬底与所述氮化镓缓冲层相接触的面为碳面极性。所述氮面极性的氮化镓缓冲层是指所述氮化镓缓冲层与所述势垒层相接触的面为氮面极性。所述氮面极性的沟道层是指所述氮化镓沟道层与所述势垒层接触的面为镓面极性,相对的另一面为氮面极性,所述氮化镓沟道层与所述势垒层相接触的表面存在二维电子气,形成导电通道。外延结构中的碳化硅衬底和氮化镓缓冲层,在没有特别说明的情况下,一般为硅面极性的碳化硅衬底和镓面极性的氮化镓缓冲层。由于氮化镓的极性不同,去除氮化镓的方法也相应的不同。本申请针对性的提出一种为回收碳面极性的碳化硅衬底,去除氮面极性的氮化镓的方法。
S20:采用湿法刻蚀去除所述氮面极性的氮化镓沟道层、势垒层和氮面极性的氮化镓缓冲层。
具体的,所述湿法刻蚀是将包含氮面极性的氮化镓沟道层4、势垒层3和氮面极性的氮化镓缓冲层2的外延结构浸入到溶液中,使其全部被腐蚀,只保留碳面极性的碳化硅衬底1,形成如图3所示的结构。所述溶液可以是10%-50%KOH(氢氧化钾)的混合溶液,也可以是氢氧化钠、磷酸、柠檬酸中的一种或者混合溶液。所述湿法刻蚀的速率大于100/min。为了加快湿法刻蚀速率,可以在KOH溶液中加入乙二醇,并将混合溶液加热至100℃以上。并且可以再湿法刻蚀的过程中,适当搅拌溶液,使刻蚀更加均匀。此外,在湿法刻蚀过程中,还可以用UV光照射外延层2,以提高刻蚀速率,所述UV光可以是波长短于氮化镓材料带隙波长的光波,例如Xe光。UV照射可以在外延材料内形成电子空穴对,表面的空穴可以促进氧化物的形成,由此促进外延结构的刻蚀。
S30:清洗所述碳化硅衬底表面并吹干。
具体的,使用去离子水清洗碳化硅衬底1表面上的化学物质,然后用氮气吹干所述碳化硅衬底1,即完成碳化硅衬底1的回收。之后在所述碳化硅衬底1上可以再次进行外延生长。
本申请所提出的碳面极性的碳化硅衬底的回收方法,能够加快去除外延结构的速率,加快了回收效率,并且无需使用抛光和研磨工艺,不会减少碳化硅衬底的厚度,降低了后续工艺的难度。
以上所述实施例的各技术特征可以进行任意的组合,为使描述简洁,未对上述实施例中的各个技术特征所有可能的组合都进行描述,然而,只要这些技术特征的组合不存在矛盾,都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求为准。

Claims (8)

1.一种回收碳面极性碳化硅衬底的方法,其特征在于,包括:
提供一外延结构,所述外延结构包括待回收的碳面极性碳化硅衬底、以及依次层叠于所述碳化硅衬底上的氮面极性的氮化镓缓冲层、势垒层和氮面极性的氮化镓沟道层;
采用湿法刻蚀去除所述氮面极性的氮化镓沟道层、势垒层和氮面极性的氮化镓缓冲层;
清洗所述碳面极性碳化硅衬底并吹干。
2.根据权利要求1所述的回收碳面极性碳化硅衬底的方法,所述湿法刻蚀采用10%-50%的KOH溶液。
3.根据权利要求2所述的回收碳面极性碳化硅衬底的方法,其特征在于,在所述KOH溶液中加入乙二醇,并将溶液加热到100℃以上。
4.根据权利要求1所述的回收碳面极性碳化硅衬底的方法,其特征在于,所述湿法刻蚀的溶液为氢氧化钠、磷酸、柠檬酸中的任一种或者多种的混合溶液。
5.根据权利要求1所述的回收碳面极性碳化硅衬底的方法,其特征在于,所述湿法刻蚀的速率大于100nm/min。
6.根据权利要求1所述的回收碳面极性碳化硅衬底的方法,其特征在于,清洗所述碳化硅衬底表面并吹干,具体包括:
使用去离子水清洗所述碳化硅衬底表面;
使用氮气吹干所述碳化硅衬底。
7.根据权利要求1所述的回收碳面极性碳化硅衬底的方法,其特征在于,在湿法刻蚀过程中,采用UV光照射所述外延结构。
8.根据权利要求7所述的回收碳面极性碳化硅衬底的方法,其特征在于,所述UV光为波长短于所述氮化镓带隙波长的光波。
CN201811104661.3A 2018-09-21 2018-09-21 回收碳面极性碳化硅衬底的方法 Active CN109300787B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201811104661.3A CN109300787B (zh) 2018-09-21 2018-09-21 回收碳面极性碳化硅衬底的方法
US16/562,452 US10763174B2 (en) 2018-09-21 2019-09-06 Method for recovering carbon-face-polarized silicon carbide substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811104661.3A CN109300787B (zh) 2018-09-21 2018-09-21 回收碳面极性碳化硅衬底的方法

Publications (2)

Publication Number Publication Date
CN109300787A CN109300787A (zh) 2019-02-01
CN109300787B true CN109300787B (zh) 2019-07-12

Family

ID=65164053

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811104661.3A Active CN109300787B (zh) 2018-09-21 2018-09-21 回收碳面极性碳化硅衬底的方法

Country Status (2)

Country Link
US (1) US10763174B2 (zh)
CN (1) CN109300787B (zh)

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1427002B1 (en) * 2002-12-06 2017-04-12 Soitec A method for recycling a substrate using local cutting
US20060016786A1 (en) * 2004-07-26 2006-01-26 Bing-Yue Tsui Method and apparatus for removing SiC or low k material film
WO2010151721A1 (en) * 2009-06-25 2010-12-29 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Transistor with enhanced channel charge inducing material layer and threshold voltage control
JP5377212B2 (ja) * 2009-10-13 2013-12-25 信越化学工業株式会社 単結晶ダイヤモンド基板の製造方法
TW201234611A (en) * 2010-11-15 2012-08-16 Hoya Corp Silicon carbide substrate and semiconductor element
US8907553B2 (en) * 2012-01-24 2014-12-09 The United States of America as represented by the Secretary of Commerce, the National Institute of Standards and Technology Cold field electron emitters based on silicon carbide structures
US9006791B2 (en) * 2013-03-15 2015-04-14 The Government Of The United States Of America, As Represented By The Secretary Of The Navy III-nitride P-channel field effect transistor with hole carriers in the channel
CN110301033B (zh) * 2017-02-16 2023-06-09 信越化学工业株式会社 化合物半导体层叠基板及其制造方法以及半导体元件
EP3591101A4 (en) * 2017-03-02 2021-01-13 Shin-Etsu Chemical Co., Ltd. MANUFACTURING METHOD FOR A SILICON CARBIDE SUBSTRATE AND SILICON CARBIDE SUBSTRATE
CN107326435A (zh) * 2017-07-28 2017-11-07 西安交通大学 一种生长GaN的SiC衬底的剥离方法

Also Published As

Publication number Publication date
US10763174B2 (en) 2020-09-01
CN109300787A (zh) 2019-02-01
US20190393090A1 (en) 2019-12-26

Similar Documents

Publication Publication Date Title
US8617962B2 (en) Method for finishing a substrate of the semiconductor-on-insulator type
US7985637B2 (en) Manufacturing method for compound semiconductor device and etching solution
US20170301772A1 (en) GaN DEVICES FABRICATED VIA WAFER BONDING
CN109065449B (zh) 外延结构的减薄方法
US9824891B1 (en) Method of manufacturing the thin film
JP2009272619A (ja) 貼り合わせ基板の製造方法
TW200737349A (en) Methods for forming thin oxide layers on semiconductor wafers
CN109300787B (zh) 回收碳面极性碳化硅衬底的方法
CN106257686A (zh) 半导体器件及其制造方法
CN105826181A (zh) 防止ono结构剥落缺陷的方法
TWI493617B (zh) 部分隔離矽基板之三族氮化物半導體裝置之製作方法
WO2015172505A1 (zh) 一种离子注入的方法
CN105513963A (zh) 半导体结构、形成方法以及场效应晶体管
CN114068329A (zh) 基于cmp刻蚀技术制备凹槽栅增强型hemt器件的方法
US20140084422A1 (en) Reclaimed Wafer And A Method For Reclaiming A Wafer
US20120264302A1 (en) Chemical mechanical polishing process
CN109308992A (zh) 回收碳化硅衬底的方法
CN107342221A (zh) 一种SiC基GaN晶体的深孔刻蚀方法
CN104716041B (zh) 一种半导体器件的制造方法
JP5443833B2 (ja) 貼り合わせsoi基板の製造方法
KR102109893B1 (ko) 접합 웨이퍼의 제조방법
CN106128957B (zh) 一种GaAs纳米线的制作方法
US20170372967A1 (en) Process for fabricating a transistor structure including a plugging step
CN105161413A (zh) 加工多晶硅表面的方法以及加工基板表面的方法
CN116959995A (zh) 一种高效热管理的金刚石基SiC MOSFET的制备方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CP02 Change in the address of a patent holder

Address after: 215127 west side of b0-1f, Zhongyuan industrial building, No. 259, Changyang street, Suzhou Industrial Park, Suzhou area, China (Jiangsu) pilot Free Trade Zone, Suzhou, Jiangsu

Patentee after: Suzhou Han Hua Semiconductor Co.,Ltd.

Address before: Room 303, building 11, Northwest District, Suzhou nano City, 99 Jinjihu Avenue, Suzhou Industrial Park, 215000, Jiangsu Province

Patentee before: Suzhou Han Hua Semiconductor Co.,Ltd.

CP02 Change in the address of a patent holder