CN109286596A - Band processing system - Google Patents
Band processing system Download PDFInfo
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- CN109286596A CN109286596A CN201710593565.9A CN201710593565A CN109286596A CN 109286596 A CN109286596 A CN 109286596A CN 201710593565 A CN201710593565 A CN 201710593565A CN 109286596 A CN109286596 A CN 109286596A
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- bus
- physical layer
- layer subsystem
- module
- processing system
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Security & Cryptography (AREA)
- Power Engineering (AREA)
- Bus Control (AREA)
Abstract
The present invention provides a kind of band processing system, the system includes the physical layer subsystem for carrying out physical layer process and the agreement layer subsystem for carrying out protocol layer processing, it is characterized in that, the band processing system further includes bus bridge, for the connection between the second bus in the first bus in the physical layer subsystem and the agreement layer subsystem.System of the invention can realize the connection in baseband chip between physical layer subsystem and agreement layer subsystem by way of high speed interconnection bridge, so that baseband chip has the dynamic adjustment capability of function, in addition, can be realized direct, parallel, a large amount of memory access function between two subsystems.
Description
Technical field
The present invention relates to wireless communication technology field more particularly to a kind of band processing systems or baseband processing chip.
Background technique
In digital communication systems, Base-Band Processing mainly includes signal processing, data link layer and the net of physical layer
The agreement process of network layers etc., currently, digital base band processor is realized either using more IC chips using SoC
(System on Chip) chip is realized, is realized in single chip with DSP (Digital Signal
Processor the protocol processes function of the physical layer function based on) and the data link layer based on embedded type CPU and network layer etc.
Energy.
In current baseband chip system, using such as Fig. 1 institute between physical layer subsystem and agreement layer subsystem
The connection mode shown, by the dual port RAM of an asynchronous clock, (Random Access Memory is come real between two subsystems
Existing data sharing, realizes mutual phase control by interruption or semaphore.For this connection scheme, between two subsystems
Data sharing can only be realized by dual port RAM, DSP data instance be accessed with CPU, the realization process includes: CPU will need access
The format arranged according to one of address be sent to some agreed address of dual port RAM；CPU is interrupted or semaphore notifies
RISC (Reduced Instruction Set Computer) processor；Risc processor goes the agreed address acquirement CPU of the dual port RAM of agreement to need to visit
The address asked；The return address in dual port RAM that risc processor arranges the data-moving of agreed address to CPU；At RISC
It manages device interruption or semaphore notifies CPU；CPU obtains the data for needing the address accessed from the return address that dual port RAM is arranged.
In this mode of the prior art, the respective internal storage space of two subsystems can not be visited directly by another subsystem
It asks, when the mutual access being related between frequent two subsystems, the cost of data interaction will be very huge.
Summary of the invention
It is an object of the invention to overcome the defect of the above-mentioned prior art, physical layer subsystem in a kind of baseband chip is provided
With the method for communicating of agreement layer subsystem.
According to the first aspect of the invention, a kind of band processing system is provided.The system includes for carrying out physical layer
The physical layer subsystem of processing and agreement layer subsystem for carrying out protocol layer processing, which is characterized in that the Base-Band Processing system
System further includes bus bridge, for the second bus in the first bus in the physical layer subsystem and the agreement layer subsystem it
Between connection.
In band processing system of the invention, the physical layer subsystem includes the DSP mould being articulated in the first bus
Block and RISC module.
In band processing system of the invention, the agreement layer subsystem includes the CPU mould of mounting on the second bus
Block.
In band processing system of the invention, the bus bridge includes:
Source bus protocol conversion module, for being converted to multichannel according to source bus rate for the concurrent main access of source bus
Storage-type is synchronous from accessing and be submitted to asynchronous bus parallel queue module；
Asynchronous bus parallel queue module, for provide identical with source bus rate independent read-write interface and offer and
The identical read-write interface of purpose Bus Speed；
Purpose bus protocol conversion module takes for the rate according to purpose bus from asynchronous bus parallel queue module
The data of storage-type out are converted into the access of purpose bus and are sent to purpose bus.
In band processing system of the invention, the source bus be first bus or second bus, it is described
Purpose bus is second bus or first bus.
In band processing system of the invention, the source bus protocol conversion module includes parallel write address conversion
Module writes data conversion submodule, write response transform subblock, read address transform subblock, reads data transform subblock；It is described
Asynchronous bus parallel queue module includes that the parallel submodule of unilateral five write of unilateral reading is carried out by the way of first in first out；
The purpose bus protocol conversion module includes turning for being adapted to the parallel write address transform subblock of purpose bus, writing data
It changes submodule, write response transform subblock, read address transform subblock, read data transform subblock.
In band processing system of the invention, first bus is ahb bus, pci bus or AXI bus.
In band processing system of the invention, second bus is ahb bus, pci bus or AXI bus.
According to the second aspect of the invention, a kind of wireless communications products are provided comprising at base band of the invention
Reason system.
Compared with the prior art, the advantages of the present invention are as follows:
It is realized between baseband chip physical layer subsystem and agreement layer subsystem by way of high speed interconnection bridge
Connection so that baseband chip has the dynamic adjustment capability of function；It can be realized between two subsystems direct, parallel, big
The memory access function of amount accesses the advantages such as more quick, addressing space and data volume are unrestricted, concurrently access to promote.
Detailed description of the invention
The following drawings only makees schematical description and interpretation to the present invention, is not intended to limit the scope of the present invention, in which:
Fig. 1 shows the method for communicating between baseband chip physical layer subsystem and agreement layer subsystem in the prior art
Schematic diagram.
Fig. 2 shows the connection sides between physical layer subsystem according to an embodiment of the invention and agreement layer subsystem
The schematic diagram of method.
Fig. 3 shows the structural schematic diagram of bus bridge according to an embodiment of the invention.
Specific embodiment
It is logical below in conjunction with attached drawing in order to keep the purpose of the present invention, technical solution, design method and advantage more clear
Crossing specific embodiment, the present invention is described in more detail.It should be appreciated that specific embodiment described herein is only to explain
The present invention is not intended to limit the present invention.
Fig. 2 shows the method for communicating of physical layer subsystem according to an embodiment of the invention and agreement layer subsystem
Schematic diagram.
Baseband system 200 includes physical layer subsystem 210 and agreement layer subsystem 220, baseband system 200 or base band core
Piece be decoded for synthesizing the baseband signal that will emit, or to the baseband signal received, for example, for WCDMA and
The communication system etc. of LTE, physical layer subsystem 210 complete the processing for the layer one (i.e. physical layer) that 3GPP is defined, for example, sending number
According to coding, modulation, encryption etc., receive synchronization, demodulation, decryption, decoding of data etc.；Agreement layer subsystem 220 is for completing
The protocol processes of layer two (including RLC, MAC, PDCP) and layer three (i.e. radio resource control layer), it is also achievable and application processing
Control and data interaction etc. to physical layer are realized in interaction.
In the embodiment of fig. 2, physical layer subsystem 200 includes but are not limited to DSP, risc processor, other modules
Deng being interconnected between each module by bus A.Agreement layer subsystem 220 includes but is not limited to CPU, other modules, each module
Between pass through bus B interconnect.
CPU is the control centre of entire baseband system, can run real-time embedded operating system, such as Nucleus
Commonly used in completing physical layer function, risc processor only carries out limited usual instructions by simplifying for hardware by PLUS, DSP.
It should be understood that Fig. 2 illustrate only the basic functional block diagram of baseband system, it may also include other in baseband system
Functional module, for example, RAM, ROM etc..
Bus A for example can be ahb bus (Advanced High Performance Bus, Advanced High-Performance Bus),
APB bus (Advanced Peripheral Bus, peripheral bus), AXI (Advanced eXtensible Interface)
Bus etc..Bus B for example can be pci bus etc., AXI bus etc., the present invention to the type of bus with no restriction.
In the embodiment of fig. 2, between the bus A in physical layer subsystem 210 and the bus B of agreement layer subsystem 220
Full connection, including two bus bridges, i.e. physical layer to protocol layer bridge and protocol layer to physics are carried out by way of bus bridge
Layer bridge.In this way, DSP, risc processor and other modules of physical layer subsystem 210 is allowed to pass through physical layer
CPU, other modules of agreement layer subsystem 220 are efficiently directly accessed to protocol layer bridge, meanwhile, agreement layer subsystem 220
CPU, other modules efficiently can be directly accessed by protocol layer to physical layer bridge physical layer subsystem 210 DSP,
Risc processor etc..
Fig. 3 shows the physical layer of Fig. 2 to the functional block diagram of protocol layer bridge, the function and its class of protocol layer and physical layer bridge
Seemingly, hereinafter, it will be only introduced by taking physical layer to protocol layer bridge as an example.The bus bridge respectively includes source bus agreement and turns
It changes, asynchronous bus parallel queue, purpose bus protocol three modules of conversion.
The concurrent main access of source bus is converted to multichannel storage according to source bus rate by source bus protocol conversion module
Type is synchronous from access, is submitted to asynchronous bus parallel queue module.
Asynchronous bus parallel queue module, independent read-write interface and the offer purpose bus for providing source bus same rate are same
The read-write interface of rate, meanwhile, have the task storage queue that can match depth.
Purpose bus protocol conversion module takes out from asynchronous bus parallel queue module and stores according to purpose Bus Speed
The data of type, the access for being converted into purpose bus are sent to purpose bus.
It should be understood that source bus is bus A, and purpose bus is total for physical layer bridge to protocol layer bridge
Line B, for protocol layer to physical layer bridge, source bus is bus B, and purpose bus is bus A.Bus A and bus B can be phase
The bus of same type is also possible to different types of bus.
For example, for the bus bridge between AXI and AXI, effect is by AXI and AXI same type but different configuration of total
Line is converted.Specifically, the structure of comparative diagram 3, source bus protocol conversion module are subdivided into five parallel submodules, point
It is not write address conversion, writes data conversion, write response conversion, read address conversion, reads data conversion.Write address conversion module according to
The write address VALID and write address READY of AXI protocol, by the control information such as ID, SIZE, BURSTLEN of write address together with writing
Address information samples and is written to the asynchronous bus parallel queue module of Fig. 3；It writes data conversion module and number is write according to AXI protocol
According to VALID and data READY is write, by the control signal such as ID, WSTRB for writing data together with writing data sampling and the different of Fig. 3 is written
Walk bus parallel Queue module；And so on, write response conversion, read address conversion, reading data conversion are also that will accordingly control letter
Number and data sampling and the asynchronous bus parallel queue module of Fig. 3 is written.Asynchronous bus parallel queue module can also be subdivided into simultaneously
Five capable submodules, by the way of first in first out, by the data of five submodules carry out it is unilateral write unilateral reading, in addition,
The data bit width of each submodule is consistent, to carry out the conversion such as address, data between AXI and AXI.Purpose bus
Protocol conversion module is equally divided into five parallel submodules, be respectively write address conversion, write data conversion, write response conversion,
Data conversion is read in read address conversion, is realized write address, is write data, write response, read address, reading data under purpose AXI bus
Agreement matching.
In another example effect is by the ground on two kinds of different bus of AHB and PCI for the bus bridge between AHB and PCI
Location, data and control signal, are converted according to the protocol requirement of AHB and pci bus.The function of bus bridge includes receiving to come from
Meet the address of ahb bus agreement and controls signal and be the agreement met in pci bus through protocol conversion；To from bus pair
The data of the equipment in face are buffered, this is because ahb bus and pci bus are the different buses of frequency, the two is in agreement
Too many wait state cannot be inserted by requiring, if will will affect the bandwidth of the two without data buffering；Execute address
Conversion due to PCI only support to address by word single or burst and reads and writes affairs, and AHB can support that byte or half-word address, because
The byte address occurred on AHB address bus is converted directly into the word address in pci bus by this bus bridge.
Specifically, by taking CPU access DSP storage as an example, as shown in connection with fig. 2, the specific process of bus bridge is as follows: CPU
Initiate the access of destination address；Protocol layer is done directly conversion to physical layer bridge, and access is transformed into physical layer subsystem, access
Destination address is DSP target storage address；DSP destination address is accessed correctly, and access result passes to protocol layer to physical layer
Bridge；Protocol layer returns to CPU for result is accessed to physical layer bridge, and access terminates.
It should be understood that the process of RISC access protocol layer subsystem and above-mentioned almost the same, only access is by physics
Layer arrives protocol layer bridge, and details are not described herein for detailed process.
Total described, access and Stored Procedure are entirely to be turned using the direct storage address that bus bridge carries out in the present invention
Change and protocol conversion, compared with the existing technology in by the way that for dual port RAM mechanism, the present invention is not necessarily to reciprocity end CPU or RISC
Multiple response, thus make access more rapidly；Moreover, the address space of access and the data volume of single reference be also not limited to it is double
The size of mouth RAM；Using the structure of bus bridge, can support the module of physical layer subsystem and agreement layer subsystem, as RISC,
CPU, DSP etc., the mutual access of completely concurrent progress, have maximum degree of parallelism.In addition, bus bridge mode of the invention is more
The function of being suitable for physical layer subsystem and agreement layer subsystem needs the case where dynamically changing, for example, when needing in physical layer
When subsystem or agreement layer subsystem increase new function, or when need to change certain existing capabilities of physical layer subsystem by
When protocol layer subsystem processes, the internal structure and function of bus bridge are not necessarily to any change, and for the side of existing dual port RAM
Formula, then need to consider whether the dual port RAM (it is usually provided by third party) can support the change of this function.
It can be applied in terminal or the base station of the wireless communication systems such as WCDMA, LTE based on baseband chip of the invention.
Various embodiments of the present invention are described above, above description is exemplary, and non-exclusive, and
It is not limited to disclosed each embodiment.Without departing from the scope and spirit of illustrated each embodiment, for this skill
Many modifications and changes are obvious for the those of ordinary skill in art field.The selection of term used herein, purport
In principle, the practical application or to the technological improvement in market for best explaining each embodiment, or make the art its
Its those of ordinary skill can understand each embodiment disclosed herein.
Claims (9)
1. a kind of band processing system, including the physical layer subsystem for carrying out physical layer process and for carrying out at protocol layer
The agreement layer subsystem of reason, which is characterized in that the band processing system further includes bus bridge, in the physical layer subsystem
The connection between the second bus in first bus and the agreement layer subsystem.
2. system according to claim 1, which is characterized in that the physical layer subsystem includes being articulated in the first bus
DSP module and RISC module.
3. system according to claim 1, which is characterized in that the agreement layer subsystem includes mounting on the second bus
CPU module.
4. system according to claim 1, which is characterized in that the bus bridge includes:
Source bus protocol conversion module, for being converted to multichannel storage according to source bus rate for the concurrent main access of source bus
Type is synchronous from accessing and be submitted to asynchronous bus parallel queue module；
Asynchronous bus parallel queue module, for providing independent read-write interface identical with source bus rate and offer and purpose
The identical read-write interface of Bus Speed；
Purpose bus protocol conversion module is deposited for the rate according to purpose bus from the taking-up of asynchronous bus parallel queue module
The data of storage type are converted into the access of purpose bus and are sent to purpose bus.
5. system according to claim 4, which is characterized in that the source bus is first bus or described second total
Line, the purpose bus are second bus or first bus.
6. system according to claim 4, which is characterized in that the source bus protocol conversion module includes parallel writing ground
Location transform subblock writes data conversion submodule, write response transform subblock, read address transform subblock, reads data conversion
Module；
Asynchronous bus parallel queue module includes that unilateral five write of unilateral reading are carried out by the way of first in first out parallel
Submodule；
The purpose bus protocol conversion module includes for being adapted to the parallel write address transform subblock of purpose bus, writing number
According to transform subblock, write response transform subblock, read address transform subblock, read data transform subblock.
7. band processing system according to claim 1, which is characterized in that first bus is ahb bus, PCI is total
Line or AXI bus.
8. band processing system according to claim 1, which is characterized in that second bus is ahb bus, PCI is total
Line or AXI bus.
9. a kind of wireless communications products, including band processing system according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710593565.9A CN109286596A (en) | 2017-07-20 | 2017-07-20 | Band processing system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710593565.9A CN109286596A (en) | 2017-07-20 | 2017-07-20 | Band processing system |
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| CN109286596A true CN109286596A (en) | 2019-01-29 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003007643A1 (en) * | 2001-07-09 | 2003-01-23 | Advanced Micro Devices, Inc. | Separate communications channels for data and control codes |
| CN201966900U (en) * | 2011-01-07 | 2011-09-07 | 深圳市天微电子有限公司 | Baseband chip with system on chip and interphone |
| CN103605632A (en) * | 2013-11-18 | 2014-02-26 | 山东大学 | Method and device for communication between AXI (advanced extensible interface) bus and AHB (advanced high-performance bus) |
-
2017
- 2017-07-20 CN CN201710593565.9A patent/CN109286596A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003007643A1 (en) * | 2001-07-09 | 2003-01-23 | Advanced Micro Devices, Inc. | Separate communications channels for data and control codes |
| CN201966900U (en) * | 2011-01-07 | 2011-09-07 | 深圳市天微电子有限公司 | Baseband chip with system on chip and interphone |
| CN103605632A (en) * | 2013-11-18 | 2014-02-26 | 山东大学 | Method and device for communication between AXI (advanced extensible interface) bus and AHB (advanced high-performance bus) |
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Application publication date: 20190129 |