CN109274340A - A kind of broadband limiting amplifier circuit - Google Patents
A kind of broadband limiting amplifier circuit Download PDFInfo
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- CN109274340A CN109274340A CN201810992946.9A CN201810992946A CN109274340A CN 109274340 A CN109274340 A CN 109274340A CN 201810992946 A CN201810992946 A CN 201810992946A CN 109274340 A CN109274340 A CN 109274340A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
- H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
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Abstract
A kind of broadband limiting amplifier circuit, belongs to Analogous Integrated Electronic Circuits technical field.Including first order amplifier, second level amplifier and third level amplifier, the first NMOS tube and the second NMOS tube are that input connects the small swing signal output in front end to pipe in first order amplifier, first PMOS tube and the second PMOS tube are load pipe, the difference output of first order amplifier passes through the NMOS tube grid of source follower structure in a polycrystalline resistor concatenation second level amplifier respectively, high frequency zero is introduced in signal path, signal bandwidth is expanded, while source follower reduces output impedance, output pole pushes high frequency treatment to；The output signal of prime amplifier is enlarged into the full swing signal that peak-to-peak value is equal to supply voltage by third level amplifier.The present invention does not waste additional voltage margin while expanding bandwidth, can work in low voltage domain；And the present invention replaces inductance component with the source follower that resistance concatenates to provide high frequency zero, reduces circuit area, saves chip area；The present invention can also be superimposed other technologies for expanding bandwidth.
Description
Technical field
The invention belongs to Analogous Integrated Electronic Circuits technical fields, are related to a kind of broadband limiting amplifier circuit, and in particular to one
Kind does not use passive inductance and can apply the broadband limiting amplifier circuit in low voltage domain.
Background technique
Broadband limiting amplifier is usually applied to the small swing signal of input to be amplified to the full amplitude of oscillation, and wideband limiting is put
Big device, most typical structure are Cherry-Hopper amplifiers, it is characterized by local parallel negative-feedback technology, are changed
The frequency response of dual-stage amplifier has been apt to it, traditional Cherry-Hooper amplifier is as shown in Figure 1, negative anti-by introducing resistance
Bandwidth has been expanded in feedback.But the defect of the structure is also clearly, tail current flows through feedback resistance RFWith load resistance RD, consumption
A large amount of voltage remaining, it is difficult to be applied to low voltage domain.
In addition to local parallel negative-feedback technology, bandwidth can also be increased using zero point is introduced, increase bandwidth using zero point
Principle be to offset influence of the pole to bandwidth by introducing zero point in circuit, to achieve the purpose that expand bandwidth.At present
The main technology for expanding bandwidth using zero point has: inductance peak value technology and capacitive peak technology.
Inductance peak value technology, also known as shunt compensation technology, as shown in Figure 2.The technology is by increasing in the load R of circuit
Coilloading L introduces zero point spread bandwidth using inductance L.
By the small-signal model of 2 circuit of analysis chart, the input and output voltage transmission function of circuit can be obtained are as follows:
Wherein gmIndicate mutual conductance, s indicates frequency.
Through above formula it is found that compared with traditional common-source amplifier, peak amplifier in parallel has had more a pole and one
Zero point, appropriate selection parameter setting, can achieve the purpose for expanding bandwidth.But this method has one disadvantage in that and is exactly,
Realize that inductance needs to expend very big area in CMOS technology, so limiting the application of this technology.
Summary of the invention
For being difficult to apply the problem big in low voltage domain and area, this hair existing for above-mentioned Conventional wide band limiting amplifier
It is bright to propose a kind of broadband limiting amplifier circuit, have the function of expanding bandwidth well and not waste additional voltage abundant
Degree, can work in low supply voltage, while replace inductance component to provide high frequency zero using the source follower of resistance concatenation, from
And reduce circuit area.
The technical scheme is that
A kind of broadband limiting amplifier circuit, including first order amplifier, second level amplifier and third level amplifier,
The first order amplifier includes the first NMOS tube M1, the second NMOS tube M2, the first PMOS tube M3, the second PMOS tube M4
With the first current source I1,
Positive input of the grid of first NMOS tube M1 as the broadband limiting amplifier circuit, drain electrode connection the
The drain electrode of two PMOS tube M4, source electrode connect the source electrode of the second NMOS tube M2 and by being grounded after the first current source I1；
Negative input of the grid of second NMOS tube M2 as the broadband limiting amplifier circuit, drain electrode connection the
The drain electrode of one PMOS tube M3；
The source electrode of first PMOS tube M3 and the second PMOS tube M4 connect supply voltage；
The second level amplifier includes third NMOS tube M5, the 4th NMOS tube M6, the second current source I2, third current source
I3, first resistor R1 and second resistance R2, wherein first resistor R1 and second resistance R2 be polycrystalline resistor, third NMOS tube M5 and
4th NMOS tube M6 is depletion type NMOS tube；
The grid of third NMOS tube M5 pass through first resistor R1 after connect first order amplifier in the first PMOS tube M3 drain electrode,
Its source electrode connects the grid of the first PMOS tube M3 in first order amplifier as the positive output end of the second level amplifier and passes through
It is grounded after second current source I2, the drain electrode of the 4th NMOS tube M6 of drain electrode connection simultaneously connects supply voltage；
The grid of 4th NMOS tube M6 pass through second resistance R2 after connect first order amplifier in the second PMOS tube M4 drain electrode,
Its source electrode connects the grid of the second PMOS tube M4 in first order amplifier as the negative sense output end of the second level amplifier and passes through
It is grounded after third current source I3；
The third level amplifier is for putting the positive output end signal of the second level amplifier and negative sense output end signal
The full swing signal that greatly peak-to-peak value is equal to supply voltage obtains the output signal of the broadband limiting amplifier circuit.
Specifically, the third level amplifier includes the 5th NMOS tube M7, the 6th NMOS tube M8, the 7th NMOS tube M9, the 8th
NMOS tube M10, the 9th NMOS tube 11, the tenth NMOS tube M12, the 11st NMOS tube M13 and the 12nd NMOS tube M14,
The grid of 5th NMOS tube M7 connects the grid of the 7th NMOS tube M9 and connects the positive defeated of the second level amplifier
Outlet, source electrode connect the grid and the grid of drain electrode and the tenth NMOS tube M12 of the 9th NMOS tube 11, drain electrode connection the 6th
NMOS tube M8, the 7th NMOS tube M9 and the 8th NMOS tube M10 drain electrode and connect supply voltage；
The grid of 6th NMOS tube M8 connect the grid of the 8th NMOS tube M10 and connect the second level amplifier negative sense it is defeated
Outlet, source electrode connect the drain electrode of the tenth NMOS tube M12 and the negative sense output end as the broadband limiting amplifier circuit；
The grid leak of 11st NMOS tube M13 is shorted and connects the source electrode and the 12nd NMOS tube M14 of the 7th NMOS tube M9
Grid, source electrode connect source electrode and the ground connection of the 9th NMOS tube 11, the tenth NMOS tube M12 and the 12nd NMOS tube M14；
The source electrode of 8th NMOS tube M10 connects the drain electrode of the 12nd NMOS tube M14 and as the broadband limiting amplifier
The positive output end of circuit.
The invention has the benefit that the present invention has the function of expanding bandwidth well and does not waste additional voltage
Nargin can work at low supply voltages；And the present invention to provide high frequency zero but uses resistance without using inductance component
The source follower of concatenation is realized, is greatly reduced circuit area, is saved chip area；In addition the technology can be superimposed other expansions
Technology of bandwidth such as capacitive peak technology, inverse proportion concatenation technology, capacity neutralization technology etc..
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of the difference Cherry-Hooper amplifier of traditional ohmic load.
Fig. 2 is the structural schematic diagram using the basic circuit of the amplifier of inductance peak value technology.
Fig. 3 is a kind of structural schematic diagram of broadband limiting amplifier circuit proposed by the present invention.
Fig. 4 is the circuit model that resistance drives source follower in the present invention.
Fig. 5 is the equivalent circuit that resistance drives source follower in the present invention.
Specific embodiment
The present invention will be described in detail in the following with reference to the drawings and specific embodiments；
Broadband limiting amplifier circuit proposed by the present invention is three-level amplifier, as shown in figure 3, first order amplifier includes first
NMOS tube M1, the second NMOS tube M2, the first PMOS tube M3, the second PMOS tube M4 and the first current source I1, the first NMOS tube M1's
Positive input of the grid as broadband limiting amplifier circuit, the drain electrode of the second PMOS tube M4 of drain electrode connection, source electrode connect
Connect the source electrode of the second NMOS tube M2 and by being grounded after the first current source I1；The grid of second NMOS tube M2 is put as wideband limiting
The negative input of big device circuit, the drain electrode of the first PMOS tube M3 of drain electrode connection；First PMOS tube M3 and the second PMOS tube M4
Source electrode connect supply voltage.First NMOS tube M1 and the second NMOS tube M2 is input to pipe, connects the small swing signal output in front end,
First PMOS tube M3 and the second PMOS tube M4 is load pipe.
Second level amplifier includes third NMOS tube M5, the 4th NMOS tube M6, the second current source I2, third current source I3,
One resistance R1 and second resistance R2, wherein first resistor R1 and second resistance R2 is polycrystalline resistor, third NMOS tube M5 and the 4th
NMOS tube M6 is depletion type NMOS tube；The grid of third NMOS tube M5 connects first in first order amplifier after passing through first resistor R1
The drain electrode of PMOS tube M3, source electrode is as the first PMOS tube M3 in the positive output end connection first order amplifier of second level amplifier
Grid and by being grounded after the second current source I2, the drain electrode of the 4th NMOS tube M6 of drain electrode connection simultaneously connects supply voltage；4th
The grid of NMOS tube M6 passes through the drain electrode that the second PMOS tube M4 in first order amplifier is connected after second resistance R2, and source electrode is as the
The negative sense output end of second level amplifier connects the grid of the second PMOS tube M4 in first order amplifier and is followed by by third current source I3
Ground.
First order amplifier is the five pipe amplifier of fully differential with diode connection pmos load, wherein the first current source I1 is
Tail current source also illustrates that a metal-oxide-semiconductor；Third NMOS tube M5 and the 4th NMOS tube M6 is equal source follower structure in the amplifier of the second level；
The difference output of first order amplifier passes through the NMOS of source follower structure in a polycrystalline poly resistance concatenation second level amplifier respectively
Tube grid, the i.e. drain electrode of the first NMOS tube M1 pass through the grid of the 4th NMOS tube M6 of second resistance R2 connection, the second NMOS tube M2
Drain electrode by the grid of first resistor R1 connection third NMOS tube M5, while the source of third NMOS tube M5 and the 4th NMOS tube M6
Pole connects the grid of first order load pipe the first PMOS tube M3 and the second PMOS tube M4, and such first order load pipe can be equivalent to
Diode connection；Source follower NMOS input in the second level is depletion type NMOS to pipe (i.e. third NMOS tube M5 and the 4th NMOS tube M6)
Pipe guarantees that its threshold voltage is less than the threshold value of first order amplifier load PMOS pipe (i.e. the first PMOS tube M3 and the second PMOS tube M4)
Voltage, so that the first PMOS tube M3, the second PMOS tube M4, third NMOS tube M5 and the 4th NMOS tube M6 work are in saturation region, electricity
Road works normally.High frequency zero is introduced to expand signal band using polycrystalline poly resistance concatenation source follower structure in the amplifier of the second level
Width does not introduce passive inductance compared with common Cherry-Hooper structure, is not required to additional attrition voltage nargin, and save
Chip area；Meanwhile source follower reduces output impedance, output pole pushes high frequency region to.
The grid of second level source follower source level output termination third level amplifier, third level amplifier is single tube amplifier, by prime
The output signal of amplifier is enlarged into the full swing signal that peak-to-peak value is equal to supply voltage, gives third level amplifier as shown in Figure 3
A kind of circuit implementation, including the 5th NMOS tube M7, the 6th NMOS tube M8, the 7th NMOS tube M9, the 8th NMOS tube M10,
9th NMOS tube 11, the tenth NMOS tube M12, the 11st NMOS tube M13 and the 12nd NMOS tube M14, the grid of the 5th NMOS tube M7
Pole connects the grid of the 7th NMOS tube M9 and connects the positive output end of second level amplifier, and source electrode connects the 9th NMOS tube 11
The grid of grid and drain electrode and the tenth NMOS tube M12, drain electrode connection the 6th NMOS tube M8, the 7th NMOS tube M9 and the 8th
The drain electrode of NMOS tube M10 simultaneously connects supply voltage；The grid of 6th NMOS tube M8 connects the grid of the 8th NMOS tube M10 and connection
The negative sense output end of second level amplifier, source electrode connect the drain electrode of the tenth NMOS tube M12 and as broadband limiting amplifier circuits
Negative sense output end；The grid leak of 11st NMOS tube M13 is shorted and connects the source electrode and the 12nd NMOS tube of the 7th NMOS tube M9
The grid of M14, source electrode connect source electrode and the ground connection of the 9th NMOS tube 11, the tenth NMOS tube M12 and the 12nd NMOS tube M14；
The source electrode of 8th NMOS tube M10 connects the drain electrode of the 12nd NMOS tube M14 and as the positive defeated of broadband limiting amplifier circuit
Outlet.
When source follower is driven by resistance, a zero point is introduced in transfer function, output impedance shows as inductance characteristic.Electricity
Source follower and the equivalent small-signal model for hindering driving are as shown in Figure 4, Figure 5.
It analyzes equivalent small-signal model and acquires transfer function are as follows:
Wherein gmFor metal-oxide-semiconductor mutual conductance, Cgs is metal-oxide-semiconductor gate-source parasitic capacitance, and Cgd is gate-drain parasitic capacitances, RsTo be serially connected in
The resistance of metal-oxide-semiconductor grid, CLFor load capacitance.
By above-mentioned transfer function it is found that Left half-plane there are a zero points:
Meanwhile there is also two high frequency poles, and it is apart from each other, dominant pole is about are as follows:
The output impedance of source follower are as follows:
At low frequency, the output impedance of source follower is about 1/gm；In high frequency, output impedance increases, and is approximately Rs.Source with
Device output impedance this characteristic varying with frequency is similar to inductance, it is believed that and it is active inductive load, the of broad band amplifier
Second level exactly relies on the source follower structure to greatly expand bandwidth.
In conclusion a kind of broadband limiting amplifier circuit proposed by the present invention, has the function of expanding bandwidth well
And additional voltage margin is not wasted, it can work in low supply voltage；Inductor is replaced using the source follower of resistance concatenation
Part provides high frequency zero, to reduce circuit area, saves chip area；The present invention can be superimposed other expansions simultaneously
Technology of bandwidth such as capacitive peak technology, inverse proportion concatenation technology, capacity neutralization technology etc..
Those skilled in the art disclosed the technical disclosures can make various do not depart from originally according to the present invention
Various other specific variations and combinations of essence are invented, these variations and combinations are still within the scope of the present invention.
Claims (2)
1. a kind of broadband limiting amplifier circuit, which is characterized in that transported including first order amplifier, second level amplifier and the third level
It puts,
The first order amplifier includes the first NMOS tube (M1), the second NMOS tube (M2), the first PMOS tube (M3), the second PMOS tube
(M4) and the first current source (I1),
Positive input of the grid of first NMOS tube (M1) as the broadband limiting amplifier circuit, drain electrode connection second
The drain electrode of PMOS tube (M4), the source electrode of source electrode connection the second NMOS tube (M2) are simultaneously grounded by the first current source (I1) afterwards；
Negative input of the grid of second NMOS tube (M2) as the broadband limiting amplifier circuit, drain electrode connection first
The drain electrode of PMOS tube (M3)；
First PMOS tube (M3) connects supply voltage with the source electrode of the second PMOS tube (M4)；
The second level amplifier includes third NMOS tube (M5), the 4th NMOS tube (M6), the second current source (I2), third current source
(I3), first resistor (R1) and second resistance (R2), wherein first resistor (R1) and second resistance (R2) are polycrystalline resistor, third
NMOS tube (M5) and the 4th NMOS tube (M6) are depletion type NMOS tube；
The grid of third NMOS tube (M5) connects the leakage of the first PMOS tube (M3) in first order amplifier by first resistor (R1) afterwards
Pole, source electrode connect the grid of the first PMOS tube (M3) in first order amplifier simultaneously as the positive output end of the second level amplifier
It is grounded afterwards by the second current source (I2), the drain electrode of drain electrode the 4th NMOS tube (M6) of connection simultaneously connects supply voltage；
The grid of 4th NMOS tube (M6) connects the leakage of the second PMOS tube (M4) in first order amplifier by second resistance (R2) afterwards
Pole, source electrode connect the grid of the second PMOS tube (M4) in first order amplifier simultaneously as the negative sense output end of the second level amplifier
It is grounded afterwards by third current source (I3)；
The third level amplifier is for the positive output end signal of the second level amplifier and negative sense output end signal to be enlarged into
The full swing signal that peak-to-peak value is equal to supply voltage obtains the output signal of the broadband limiting amplifier circuit.
2. broadband limiting amplifier circuit according to claim 1, which is characterized in that the third level amplifier includes the 5th
NMOS tube (M7), the 6th NMOS tube (M8), the 7th NMOS tube (M9), the 8th NMOS tube (M10), the 9th NMOS tube (11), the tenth
NMOS tube (M12), the 11st NMOS tube (M13) and the 12nd NMOS tube (M14),
The grid of 5th NMOS tube (M7) connects the grid of the 7th NMOS tube (M9) and connects the positive defeated of the second level amplifier
Outlet, source electrode connect the grid and the grid of drain electrode and the tenth NMOS tube (M12) of the 9th NMOS tube (11), drain electrode connection
6th NMOS tube (M8), the 7th NMOS tube (M9) and the 8th NMOS tube (M10) drain electrode and connect supply voltage；
The grid of 6th NMOS tube (M8) connect the grid of the 8th NMOS tube (M10) and connect the second level amplifier negative sense it is defeated
Outlet, source electrode connect the drain electrode of the tenth NMOS tube (M12) and the negative sense output end as the broadband limiting amplifier circuit；
The grid leak of 11st NMOS tube (M13) is shorted and connects the source electrode and the 12nd NMOS tube (M14) of the 7th NMOS tube (M9)
Grid, source electrode connect the 9th NMOS tube (11), the tenth NMOS tube (M12) and the 12nd NMOS tube (M14) source electrode and connect
Ground；
The source electrode of 8th NMOS tube (M10) connects the drain electrode of the 12nd NMOS tube (M14) and as the broadband limiting amplifier
The positive output end of circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810992946.9A CN109274340B (en) | 2018-08-29 | 2018-08-29 | Broadband limiting amplifier circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810992946.9A CN109274340B (en) | 2018-08-29 | 2018-08-29 | Broadband limiting amplifier circuit |
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| CN109274340B CN109274340B (en) | 2021-06-08 |
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Cited By (5)
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| CN110086436A (en) * | 2019-05-10 | 2019-08-02 | 南京牛芯微电子有限公司 | A kind of HF Wideband Amplifiers |
| CN111030694A (en) * | 2019-12-12 | 2020-04-17 | 西安电子科技大学 | Ultra-wideband source random hold amplifier based on inductive peaking |
| CN111464139A (en) * | 2020-04-24 | 2020-07-28 | 电子科技大学 | Common-mode feedback circuit suitable for wide-swing fully-differential operational amplifier |
| CN116317966A (en) * | 2023-03-29 | 2023-06-23 | 南京米乐为微电子科技有限公司 | Amplifying circuit |
| CN116566368A (en) * | 2023-05-24 | 2023-08-08 | 韬润半导体(无锡)有限公司 | Switching circuit and multiplexer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN111030694B (en) * | 2019-12-12 | 2023-03-21 | 西安电子科技大学 | Ultra-wideband source random hold amplifier based on inductive peaking |
| CN111464139A (en) * | 2020-04-24 | 2020-07-28 | 电子科技大学 | Common-mode feedback circuit suitable for wide-swing fully-differential operational amplifier |
| CN111464139B (en) * | 2020-04-24 | 2023-06-23 | 电子科技大学 | Common mode feedback circuit suitable for wide-swing full-differential operational amplifier |
| CN116317966A (en) * | 2023-03-29 | 2023-06-23 | 南京米乐为微电子科技有限公司 | Amplifying circuit |
| CN116566368A (en) * | 2023-05-24 | 2023-08-08 | 韬润半导体(无锡)有限公司 | Switching circuit and multiplexer |
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| CN109274340B (en) | 2021-06-08 |
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