CN109216295A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN109216295A
CN109216295A CN201810630896.XA CN201810630896A CN109216295A CN 109216295 A CN109216295 A CN 109216295A CN 201810630896 A CN201810630896 A CN 201810630896A CN 109216295 A CN109216295 A CN 109216295A
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CN
China
Prior art keywords
insulating materials
component
semiconductor
semiconductor packages
bonding wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
CN201810630896.XA
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English (en)
Inventor
蔡宪聪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
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Filing date
Publication date
Priority claimed from US15/894,874 external-priority patent/US10847488B2/en
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of CN109216295A publication Critical patent/CN109216295A/zh
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Abstract

本发明公开一种半导体封装，包括：载体基底，具有上表面；半导体晶粒，安装在所述上表面上；多个接合引线，将所述半导体晶粒的主动面连接至所述载体基板的上表面；绝缘材料；封装所述多个接合引线；部件，安装在所述绝缘材料上；以及模塑料，覆盖所述载体基板的上表面并封装所述半导体晶粒、多个接合引线、部件和绝缘材料。这样可以避免在加工时相邻的引线之间的短路问题，并且绝缘材料还可以保护接合引线以及为接合引线提供额外的机械支撑，使得在接合引线可以支撑安装在上面的部件，这样可以增加封装的集成度，提高封装空间的利用率，以及减小封装的占用面积。

Description

半导体封装
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体封装。
背景技术
在集成电路(IC，integrated circuit)封装行业中，会持续地期望为具有更多数量的输入/输出(I/O，input/output)端子焊盘的半导体晶粒提供密度越来越高的IC封装。当使用传统的引线接合(bonding)封装技术时，对于给定尺寸的晶粒，随着I/O端子焊盘数量的增加，相邻的接合引线(bonding wire)之间的间距或空间变得越来越小。
在塑料IC封装的模塑(molding)或封装(encapsulation)期间，塑料模塑料熔化流入模腔中并会施加足够高的应力以使接合引线移位或者变形，因此导致接合引线(bondingwire)扫动(sweep)。接合引线的移位或者变形导致相邻的接合引线彼此接触，这将导致相邻引线之间的短路。
尽管已经提出了各种方法来减少IC封装的封装工艺期间的接合引线，但是这些方法中的许多方法需要额外的工艺步骤或需要专门的设备。这些额外的工艺步骤或专门的设备的要求增加了封装的生产成本，因此不是期望的解决方式。
发明内容
有鉴于此，本发明提供一种半导体封装，以解决封装工艺期间相邻接合线之间的短路问题。
根据本发明的第一方面，公开一种半导体封装，包括：
载体基底，具有上表面；
半导体晶粒，安装在所述上表面上；
多个接合引线，将所述半导体晶粒的主动面连接至所述载体基板的上表面；
绝缘材料，封装所述多个接合引线；
部件，安装在所述绝缘材料上；以及
模塑料，覆盖所述载体基板的上表面并封装所述半导体晶粒、多个接合引线、部件和绝缘材料。
根据本发明的第二个方面，公开一种半导体封装，包括：
载体基底，具有上表面；
半导体晶粒，安装在所述上表面上；
多个第一接合引线，将所述半导体晶粒连接至所述载体基板；
绝缘材料，封装所述多个第一接合引线；
部件，安装在所述绝缘材料上；
多个第二接合引线，将所述部件连接至所述载体基板；以及
模塑料，覆盖所述载体基板的上表面并且封装所述半导体晶粒、部件、多个第一接合引线、多个第二接合引线和绝缘材料。
根据本发明的第三个方面，公开一种半导体封装，包括：
载体基底，具有上表面；
第一半导体晶粒，安装在所述上表面上；
多个第一接合引线，将所述第一半导体晶粒连接至所述载体基板；
第一绝缘材料，封装所述多个第一接合引线；
第二半导体晶粒，安装在所述第一绝缘材料上；
多个第二接合引线，将所述第二半导体晶粒连接至所述载体基板；
第二绝缘材料，封装所述多个第二接合引线；
部件，安装在所述第二绝缘材料上；以及
模塑料，覆盖所述载体基板的上表面并且封装所述部件、第一半导体晶粒、第二半导体晶粒、多个第一接合引线、多个第二接合引线、第一绝缘材料和第二绝缘材料。
本发明提供的半导体封装由于包括绝缘材料封装多个接合引线，从而避免在加工时相邻的引线之间的短路问题，并且绝缘材料还可以保护接合引线以及为接合引线提供额外的机械支撑，使得在接合引线可以支撑安装在上面的部件，这样可以增加封装的集成度，提高封装空间的利用率，以及减小封装的占用面积。
在阅读了随后以不同附图展示的优选实施例的详细说明之后，本发明的这些和其它目标对本领域普通技术人员来说无疑将变得明显。
附图说明
图1是示出根据本发明实施例具有涂覆的接合引线的示例性半导体封装的横截面示意图；
图2是图1中两个相邻接合引线的透视示意图，为了清晰起见图中没有示出模塑料；
图3是示出两个相邻的接合引线和涂覆的绝缘材料的横截面示意图；
图4至图7示出了横截面示意图，用于表示本发明一个实施例的用于形成具有经涂覆的接合引线的半导体封装的示例性方法；
图8是半导体封装的俯视示意图，示出了半导体晶粒周围的示例性区域，其中该区域喷涂了绝缘材料；
图9是示出根据本发明另一实施例的用于将绝缘材料涂覆到接合引线上的浸渍工艺的横截面示意图；
图10A是根据本发明另一实施例的半导体IC封装的俯视示意图；
图10B是根据本发明又一实施例的半导体封装的俯视示意图；
图11是沿图10A中的虚线I-I'截取的横截面示意图；
图12是模塑之后的半导体IC封装的图示；
图13是根据本发明另一实施例的半导体封装的俯视示意图；
图14是沿着图13中的虚线II-II'截取的横截面示意图；
图15是根据本发明又一实施例的半导体封装的横截面示意图；
图16是根据本发明又一实施例的半导体封装的横截面示意图；
图17是根据本发明又一实施例的半导体封装的横截面示意图。
具体实施方式
在说明书和随后的权利要求书中始终使用特定术语来指代特定组件。正如本领域技术人员所认识到的，制造商可以用不同的名称指代组件。本文件无意于区分那些名称不同但功能相同的组件。在以下的说明书和权利要求中，术语“包括”和“包括”被用于开放式类型，因此应当被解释为意味着“包括，但不限于...”。此外，术语“耦合”旨在表示间接或直接的电连接。因此，如果一个设备耦合到另一设备，则该连接可以是直接电连接，或者经由其它设备和连接的间接电连接。
以下描述是实施本发明的最佳设想方式。这一描述是为了说明本发明的一般原理而不是用来限制的本发明。本发明的范围通过所附权利要求书来确定。
下面将参考特定实施例并且参考某些附图来描述本发明，但是本发明不限于此，并且仅由权利要求限制。所描述的附图仅是示意性的而并非限制性的。在附图中，为了说明的目的，一些元件的尺寸可能被夸大，而不是按比例绘制。在本发明的实践中，尺寸和相对尺寸不对应于实际尺寸。
请参考图1和图2。图1示出了根据本发明一个实施例的具有涂覆的接合引线的示例性半导体封装的横截面示意图。图2是图1中两个相邻接合引线的透视示意图，为了清晰起见图中没有示出模塑料。
如图1和图2所示，半导体封装1包括具有上表面10a的载体基板10。半导体晶粒20安装在上表面10a上。半导体晶粒20具有主动面(active surface)20a，并设有多个输入/输出(I/O，input/output)焊盘210分布在主动面20a上。根据说明性的实施例，半导体晶粒20通过多个接合引线30电连接到载体基板10的上表面10a上的接合指(bond finger)110。根据说明性的实施例，接合引线30可以包括铜、金、银或任何适合的导电材料。根据说明性的实施例，载体基板10可以包括封装基板、中间层基板或引线框架(leadframe)基板，但是不限于此。
根据说明性的实施例，接合引线30部分地涂覆有绝缘材料40。根据说明性的实施例，绝缘材料40可以包括聚合物、环氧树脂或树脂，但不限于此。可以固化涂覆在接合引线30上的绝缘材料40以为接合引线30提供额外的机械支撑，这样不仅可以保护接合引线，同时还可以使接合引线30具备支撑能力。绝缘材料40保护接合线30并且能够阻止在半导体封装1的封装过程期间的接合引线的扫动(sweep)。根据说明性的实施例，绝缘材料40具有低电容率(permittivity)或低介电常数(低k，low-k)，具有低电容率或低介电常数的绝缘材料40可以防止短路以及减轻相邻引线之间的串扰(crosstalk)。在其他实施例中，接合引线30可以完全地涂覆有绝缘材料40以提供更满意的隔离效果，同时进一步为接合引线30提供更强的机械支撑。
根据说明性的实施例，半导体封装1还包括位于载体基板10的上表面10a上的模塑料50。模塑料50封装接合引线30、绝缘材料40和半导体晶粒20。根据说明性的实施例，模塑料50可以包括环氧树脂和填充材料，但不限于此。根据说明性的实施例，绝缘材料40可以具有与模塑料50相同的成分(例如相同的环氧组合物)，但是绝缘材料40可以没有填充材料或具有较低含量的填充材料。根据说明性的实施例，绝缘材料40包括小于50ppm(parts permillion，百万分之)的卤素(halogen)含量以防止接合引线30的腐蚀。根据另一实施例，绝缘材料40可具有与模塑料50不同的成分，使用不同的成分或材料可以方便绝缘材料40与模塑料50在不同的制程中形成，当然也可以在同一制程中形成。此外采用同一种成分或材料时，绝缘材料40与模塑料50也可以在不同的制程中形成，或者在同一制程中形成。
如图2所示，为了简单起见，仅示出了两个相邻的接合引线30a和30b。绝缘材料40部分地涂覆在两个相邻的接合引线30a和30b上的最可能与相邻引线短路的部分上，引线扫动时引起的上述相邻的引线短路发生在半导体封装1的封装过程期间。根据说明性的实施例，绝缘材料40也可以形成在载体基板10的上表面10a上或半导体封装1中的其他地方。形成在载体基板10的上表面10a上的绝缘材料40可以增强模塑料50和载体基板10之间的界面粘合强度。
两个相邻的接合引线30a和30b可以具有不同的弧线高度(loop height)，以方便生产制造以及适应不同的安装需求。由于涂覆在接合引线30a和30b上的绝缘材料40可以避免封装过程中的异常引线扫动，并提供显著的隔离效果，因此使用本发明是有优势的。此外，可以降低两个相邻的接合引线30a和30b的弧线高度，使得在相同的空间中可以布置更多的引线。
图3示出了两个相邻的接合引线和涂覆的绝缘材料的横截面示意图。如图3所示，根据说明性的实施例，当从接合引线30的横截面中观察时，绝缘材料40可以仅覆盖每根接合引线30的至少一部分，例如上半部分。根据说明性的实施例，每根接合引线30的下半部分未被绝缘材料40覆盖。然而，应理解的是，在一些实施例中，绝缘材料40可以完全包裹每根接合引线30，即上半部分和下半部分均覆盖有绝缘材料。
图4至图7示出了横截面示意图，用于表示本发明一个实施例的用于形成具有经涂覆的接合引线的半导体封装的示例性方法，其中相同的数字标记表示相似的层、区域或元件。如图4所示，半导体晶粒20安装在载体基板10的上表面10a上。根据说明性的实施例，载体基板10可以包括封装基板、中间层基板或引线框架基板，但是不限于此。半导体晶粒20可以通过使用粘合剂(图中未明确示出)粘附到上表面10a，但是不限于此。根据说明性的实施例，半导体晶粒20通过多个接合引线30电连接到载体基板10的上表面10a上的接合指110。
在引线接合工艺之后，将绝缘材料40喷涂到位于预定区域内的接合引线30上。例如，参照图8所示，预定区域可以为围绕半导体晶粒20所展示的区域140。可以将绝缘材料40喷涂到位于区域140内的接合引线30上，该区域内的接合引线在封装工艺期间最有可能与相邻引线短路，因此在该区域内喷涂绝缘材料40可以进一步提高引线之间的隔离效果，防止短路、串扰。根据说明性的实施例，可以将绝缘材料40喷涂到载体基板10的上表面10a上或喷涂到半导体晶粒20的主动面20a上，这样可以增强模塑料和基板表面/晶粒表面之间的界面粘合强度。应该理解的是，图8中所示的区域140仅用于说明的目的而不是对本发明的限制，本发明绝缘材料还可以喷涂到其他区域。
根据说明性的实施例，可通过使用喷射式喷雾器400或其他类似的工具将绝缘材料40喷涂到接合引线30上。然而，在一些实施例中，可以通过使用浸渍工艺(dippingprocess)将绝缘材料40涂覆到接合引线30上。例如，参照图9，容器500容纳有液态的绝缘材料40。将半导体封装1翻转并且可以将接合引线30部分地或全部地浸入绝缘材料40中以涂覆接合引线30。接着，可以执行干燥处理或烘烤处理以去除溶剂。
如图5及图6所示，在喷涂绝缘材料40之后，可以执行可选的固化工艺600以固化绝缘材料40。根据说明性的实施例，固化工艺可以在光化辐射(actinic radiation)条件下进行，此外固化工艺600可以在烘箱中条件下进行，但是不限于此。例如，固化工艺可以是在紫外线(ultraviolet，UV)或红外(infrared，IR)照射下的快速固化工艺。固化工艺600是在烘烤下的快速固化工艺。可以理解的是，在一些实施例中，可以省略固化工艺600，并且绝缘材料40可以在随后的阶段与模塑料一起固化。
如图7所示，模塑料50形成在载体基板10的上表面10a上以密封接合引线30、绝缘材料40和半导体晶粒20。根据说明性的实施例，模塑料50可以包括环氧树脂和填充材料，但是不限于此。根据说明性的实施例，绝缘材料40可以具有与模塑料50相同的成分(例如相同的环氧组合物)，但是绝缘材料40可以没有填充材料或具有较低含量的填充材料。根据说明性的实施例，绝缘材料40包括小于50ppm的卤素含量以防止焊线30的腐蚀。根据另一实施例，绝缘材料40可具有与模塑料50不同的成分。
请参考图10A至图12。图10A是根据本发明另一实施例的半导体封装的示意性俯视图。图10B是根据本发明又一实施例的半导体封装的俯视示意图。图11是沿着图10A中的虚线I-I'截取的示意性横截面图。图12示出了模塑之后的半导体封装。为清楚表示，其中一些图示中包括以透视展示的部分。相似的层、区域或元件由相同的数字编号表示。
如图10A、10B和图11所示，半导体封装2包括具有上表面10a和底表面10b的载体基板10。半导体晶粒20安装在上表面10a上。半导体晶粒20具有主动面20a，并设有多个输入/输出(I/O)焊盘210分布在主动面20a上。根据说明性的实施例，半导体晶粒20通过多排(multi-tier)接合引线30电连接到载体基板10的上表面10a上的接合指110。根据说明性的实施例，接合引线30可以包括铜、金、银或任何适合的导电材料。根据说明性的实施例，载体基板10可以包括封装基板或中间层基板，但是不限于此。
根据说明性的实施例，接合引线30上施加有绝缘材料41。例如，绝缘材料41可以围绕或在半导体晶粒20周围以矩形环状施加，但是不限于此，例如绝缘材料41可以在其他位置施加，或以圆形、多边形等形状施加。本实施例中，绝缘材料41主要用于封装接合引线30，因此布置有接合引线30的位置一般即会施加绝缘材料41，而接合引线30一般是围绕半导体晶粒20的周边设置。具体的，接合引线30的一端可连接至半导体晶粒20的主动面20a上，因此绝缘材料41随着接合引线30而围绕半导体晶粒20的周边设置，更具体的说，绝缘材料41随着接合引线30而围绕半导体晶粒20的主动面20a的周边设置。当然由于接合引线30的另一端连接至载体基板10的主动面10a上，因此绝缘材料41将从半导体晶粒20的主动面20a的周边(接合引线30的一端连接于此)延伸到载体基板10的主动面10a上(接合引线30的另一端连接于此)。这样在载体基板10的主动面10a上设有绝缘材料41的区域就围绕着半导体晶粒20了，例如围绕半导体晶粒20一周，或围绕半导体晶粒20的主动面20a一周。因此从竖直方向上看，绝缘材料41不仅覆盖半导体晶粒20的主动面20a的周边部分，也覆盖了部分载体基板10的主动面10a(例如围绕半导体晶粒20的主动面20a的部分)。绝缘材料41可以完全覆盖多排接合引线30并且仅与主动面20a的周边区域直接接触，如上所述，周边区域包括半导体晶粒20的主动面20a的周边部分以及载体基板10的主动面10a围绕半导体晶粒20的主动面20a的部分。例如如图10A、10B和11所示，绝缘材料41可以覆盖半导体晶粒20的主动面20a的周边部分，以及覆盖载体基板10的主动面10a的部分(该部分围绕半导体晶粒20的主动面20a)。当然也可以将绝缘材料41布置的更广泛，例如覆盖主动面20a的全部，或者覆盖其他区域或更多载体基板10的主动面10a的区域。此外，绝缘材料41可以有一部分或全部与该周边区域直接接触，例如绝缘材料41有一部分或全部或与半导体晶粒20的主动面20a直接接触，或/和有一部分或全部与载体基板10的主动面10a直接接触；绝缘材料41也可以有一部分未与该周边区域直接接触，例如绝缘材料41有一部分未与半导体晶粒20的主动面20a直接接触，或/和有一部分未与载体基板10的主动面10a直接接触；绝缘材料41还可以全部未与该周边区域直接接触，例如绝缘材料41全部未与半导体晶粒20的主动面20a直接接触，或/和全部未与载体基板10的主动面10a直接接触。可以理解的是，绝缘材料41可以仅覆盖接合引线30的一部分。矩形环状的绝缘材料41可以是连续的或者可以是不连续的。根据说明性的实施例，绝缘材料41可以与半导体晶粒20的侧壁直接接触。绝缘材料41的主要目的是用于封装接合引线30，因此绝缘材料41可以根据具体需求选择布置的更多或更少，也可以根据具体需求选择与封装的其他位置(例如主动面10a、20a等)直接接触或未直接接触等。
根据说明性的实施例，绝缘材料41可以包括聚合物、环氧树脂、填料或树脂，但是不限于此。可以固化涂覆在接合引线30上的绝缘材料41以向接合引线30提供额外的机械支撑，增加接合引线30的机械强度和支撑能力，并且多个接合引线30与绝缘材料组合起来具有更高的机械强度和支撑能力。绝缘材料41保护接合引线30并且能够在阻止随后的封装过程期间接合引线的扫动。根据说明性的实施例，绝缘材料41具有低电容率或低介电常数(低k)。具有低电容率或低介电常数的绝缘材料41可防止短路以及减轻相邻引线之间的串扰。
根据说明性的实施例，部件200直接安装在绝缘材料41和/或接合引线30上，具有绝缘材料41的接合引线30可以支撑部件200，设置部件200可以帮助散热，例如帮助半导体晶粒20、接合引线30的散热，此外还可以在部件200上设置其他结构，例如其他电路结构等等，因此部件200还可以为其他结构提供支撑。例如，部件200可以是虚设(dummy)硅晶粒、金属片或散热片，但不限于此。部件采用这些结构(虚设硅晶粒、金属片或散热片)均可以帮助散热，使半导体晶粒、接合引线的热量可以更快的散出，帮助降低封装温度，保证封装运行的稳定，并且还可以在这些结构上设置更多的电路或其他结构，提高封装集成度。部件200可通过使用粘合剂或粘合层202附着到绝缘材料41，这样可以使部件200稳定的安装和固定，保证封装结构的稳定性和牢固性。如图10A所示，根据说明性的实施例，部件200可具有细长形状并且部件200的长轴可以沿着半导体封装2的对角线方向延伸，这种方式可以使部件覆盖更大面积的接合引线，从而使部件能够帮助更大面积的接合引线散热，提高部件的辅助散热能力。其中长轴为部件长度的轴线方向。而沿对角线是指部件可以在对角线的路径上，并非一定要连接到对角，当然也可以连接到对角，或超出对角，更具体的说，部件至少有一部分在对角线的路径上，且部件的长度延伸方向是在对角线的路径上的。此外，图10A中仅为示例，虽然图10A中部件可能不是非常精确的在对角线上延伸，但是经过本段描述之后，应当可以理解本实施的方案，部件的位置是可以调整的，且可以调整到沿对角线延伸的位置和方向上。模流(mold flow)的方向可以与部件200的长轴正交，也即部件200模塑成型时材料的流动方向垂直于长轴。此外，如图10A所示，部件200的长轴(或长边)可以与半导体封装2的长边不平行，例如成一定的角度(如锐角)；换句话说，也可以是部件200的长轴(或长边)可以与半导体封装2的短边不垂直，例如成一定的角度(如锐角)。根据另一个实施例，如图10B所示，部件200的长边(或长轴)可以与半导体封装2的长边平行；换句话说，也可以是部件200的长轴(或长边)可以与半导体封装2的短边垂直。部件200安装的方位和位置可以根据散热需要进行具体的布置，例如将部件200的位置和方位布置为靠近最大热量产生处，从而帮助高温区域散热。此外，部件200的数量还可以设置为两个、三个或更多个。
如图12所示，在载体基板10的上表面10a上形成模塑料50，以封装接合引线30、绝缘材料41、部件200和半导体晶粒20。根据说明性的实施例，模塑料50可以包括环氧树脂和填充材料，但不限于此。根据说明性的实施例，绝缘材料41可以具有与模塑料50相同的成分(例如相同的环氧组合物)，但是绝缘材料41可以没有填充材料或具有较低含量的填充材料。根据说明性的实施例，绝缘材料41和模塑料50具有不同的成分。根据说明性的实施例，绝缘材料41包括小于50ppm的卤素含量以防止接合引线30的腐蚀。在形成模塑料50之后，在底表面10b上形成例如焊球的连接元件60。
图13是根据本发明另一实施例的半导体封装的俯视示意图。图14是沿图13中的虚线II-II'截取的横截面示意图。为清楚表示，图示中包括以透视展示的部分。相似的层、区域或元件由相同的数字编号表示。如图13和图14所示，类似地，半导体封装3包括安装在绝缘材料41上的部件200。根据说明性的实施例，部件200可以是半导体晶粒并且通过接合引线31以引线接合的方式连接到载体基板10。部件200与下面的半导体晶粒20完全重叠(即部件200完全覆盖了半导体晶粒20)。当然部件200也可以与半导体晶粒不完全重叠，例如仅部分重叠，或也可以不重叠。如图13中可见，部件200的表面积大于下面的半导体晶粒20的表面积。当然部件200的表面积也可以小于或等于下面的半导体晶粒20的表面积。部件200的长边具有长度L。部件200由绝缘材料41和接合引线30、31支撑。如图14中所示，在部件200的边缘与部件200和绝缘材料41之间的接触点CP之间具有长度为t的悬挂部230。悬挂部的长度t可以大于1/3L并且可以小于1/2L，也就是悬挂部的长度可以占部件200的长度的1/3到1/2(大于1/3并小于1/2)。此外，部件200和绝缘材料41之间的接触点CP在竖直方向上的投影可以在半导体晶粒20上或之外；当接触点CP的投影在半导体晶粒之外时，部件200也可以不与半导体晶粒重叠。
模塑料50形成在载体基板10的上表面10a上以封装接合引线30、31、绝缘材料41、部件200和半导体晶粒20。可以通过转印模(transfer mold)或压缩模(compression mold)的工艺形成模塑料50，但不限于此。
图15是根据本发明又一实施例的半导体封装的截面示意图，其中相似的层、区域或元件由相同的数字编号表示。如图15所示，类似地，半导体封装4包括安装在绝缘材料41上的部件200。根据说明性的实施例，部件200可以是半导体晶粒并且通过接合引线31引线接合到载体基板。根据说明性的实施例，可将绝缘材料42施加到接合引线31以便保护接合引线31并为接合引线31提供额外的机械支撑，增加接合引线31的机械强度和支撑能力，并且多个接合引线31与绝缘材料组合起来具有更高的机械强度和支撑能力。根据说明性的实施例，部件300可以经由粘合层302直接安装在绝缘材料42和/或接合引线30上，具有绝缘材料42的接合引线31可以支撑部件300。例如，部件300可以包括分离的无源器件，无源器件包括但不限于电容器、电阻器或电感器。根据说明性的实施例，可以通过接合引线32将部件300引线接合到载体基板10和/或部件200。模塑料50形成在载体基板10的上表面10a上以封装接合引线30、31、32、绝缘材料41、42、部件200、部件300和半导体晶粒20。虽然图中仅示出了两个部件300，但是部件300可以有更多个，例如三个、四个或更多。此外，部件300也可以与部件200一样为一个整体而不是分离的，或者除了分离的部件300之外还设有其他的为一个整体的部件。
图16是根据本发明又一实施例的半导体封装的示意性横截面图，其中相似的层、区域或元件由相同的数字编号表示。如图16所示，图16中的半导体封装5与图14中的半导体封装3之间的差异在于图16中的半导体封装5包括在部件200与半导体晶粒20之间的间隔件700。间隔件700可以通过使用粘合层702粘附到半导体晶粒20的主动面20a。当然图16中也可以在接合引线31上设有绝缘材料，以及也可以在接合引线上设置部件(例如图15中的部件300)。
图17是根据本发明又一实施例的半导体封装的示意性截面图，其中相似的层、区域或元件由相同的数字编号表示。如图17所示，半导体封装6包括直接安装在绝缘材料41和/或接合引线30上的部件200。其中部件200在图示中为两个，分别在左边的绝缘材料41和/或接合引线30上以及在右边的绝缘材料41和/或接合引线30上，两个部件200为分离的。虽然图中仅示出了两个部件200，但是部件200可以有更多个，例如三个或四个或更多。此外，半导体封装可以包括图17中所示的分离的部件，还可以包括如图16所示的安装在不同的接合引线30上的一整个部件。根据说明性的实施例，部件200可以包括半导体晶粒或例如电容器、电阻器或电感器的无源器件。部件200可以通过接合引线31引线接合到载体基板10和/或半导体晶粒20。模塑料50形成在载体基板10的上表面10a上以封装接合引线30、31、绝缘材料41、部件200和半导体晶粒20。
本领域的技术人员将容易地观察到，在保持本发明教导的同时，可以做出许多该装置和方法的修改和改变。因此，上述公开内容应被解释为仅由所附权利要求书的界限和范围所限制。

Claims (16)

1.一种半导体封装，其特征在于，包括：
载体基底，具有上表面；
半导体晶粒，安装在所述上表面上；
多个接合引线，将所述半导体晶粒的主动面连接至所述载体基板的上表面；
绝缘材料，封装所述多个接合引线；
部件，安装在所述绝缘材料上；以及
模塑料，覆盖所述载体基板的上表面并封装所述半导体晶粒、多个接合引线、部件和绝缘材料。
2.根据权利要求1所述的半导体封装，其特征在于，所述部件包括虚设硅晶粒、金属片或散热片。
3.根据权利要求1所述的半导体封装，其特征在于，所述部件通过粘合层附着到所述绝缘材料。
4.根据权利要求1所述的半导体封装，其特征在于，所述部件具有细长形状并且所述部件的长轴沿着所述半导体封装的对角线方向延伸。
5.根据权利要求1所述的半导体封装，其特征在于，所述部件的长边与所述半导体封装的长边平行或不平行。
6.根据权利要求1所述的半导体封装，其特征在于，所述绝缘材料围绕所述半导体晶粒，形状为矩形环状。
7.根据权利要求6所述的半导体封装，其特征在于，所述矩形环状的绝缘材料为连续的或不连续的。
8.根据权利要求1所述的半导体封装，其特征在于，所述绝缘材料和所述模塑料具有不同的成分。
9.根据权利要求1所述的半导体封装，其特征在于，所述绝缘材料完全覆盖所述接合引线并且与所述主动面的周边区域直接接触。
10.根据权利要求1所述的半导体封装，其特征在于，所述载体基板包括封装基板或中间层基板或引线框架基板。
11.一种半导体封装，其特征在于，包括：
载体基底，具有上表面；
半导体晶粒，安装在所述上表面上；
多个第一接合引线，将所述半导体晶粒连接至所述载体基板；
绝缘材料，封装所述多个第一接合引线；
部件，安装在所述绝缘材料上；
多个第二接合引线，将所述部件连接至所述载体基板；以及
模塑料，覆盖所述载体基板的上表面并且封装所述半导体晶粒、部件、多个第一接合引线、多个第二接合引线和绝缘材料。
12.根据权利要求11所述的半导体封装，其特征在于，所述部件包括半导体晶粒或无源器件。
13.根据权利要求11所述的半导体封装，其特征在于，还包括位于所述部件的边缘和所述部件与所述绝缘材料之间的接触点之间的悬挂部。
14.根据权利要求13所述的半导体封装，其特征在于，所述部件的长边的长度为L，并且所述悬挂部的长度为t，其中t大于1/3L且小于1/2L。
15.一种半导体封装，其特征在于，包括：
载体基底，具有上表面；
第一半导体晶粒，安装在所述上表面上；
多个第一接合引线，将所述第一半导体晶粒连接至所述载体基板；
第一绝缘材料，封装所述多个第一接合引线；
第二半导体晶粒，安装在所述第一绝缘材料上；
多个第二接合引线，将所述第二半导体晶粒连接至所述载体基板；
第二绝缘材料，封装所述多个第二接合引线；
部件，安装在所述第二绝缘材料上；以及
模塑料，覆盖所述载体基板的上表面并且封装所述部件、第一半导体晶粒、第二半导体晶粒、多个第一接合引线、多个第二接合引线、第一绝缘材料和第二绝缘材料。
16.根据权利要求15所述的半导体封装，其特征在于，还包括将所述部件连接到所述载体基板的多个第三接合引线。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111668104A (zh) * 2019-03-07 2020-09-15 无锡华润安盛科技有限公司 一种芯片封装结构及芯片封装方法
CN112397498A (zh) * 2019-08-01 2021-02-23 联发科技股份有限公司 半导体封装

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11264309B2 (en) * 2019-06-24 2022-03-01 Mediatek Inc. Multi-row QFN semiconductor package

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030042615A1 (en) * 2001-08-30 2003-03-06 Tongbi Jiang Stacked microelectronic devices and methods of fabricating same
US20120241979A1 (en) * 2011-03-21 2012-09-27 Daesik Choi Integrated circuit packaging system with step mold and method of manufacture thereof
CN103367366A (zh) * 2012-03-31 2013-10-23 南亚科技股份有限公司 半导体封装构件

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100164083A1 (en) * 2008-12-29 2010-07-01 Numonyx B.V. Protective thin film coating in chip packaging
US8680686B2 (en) * 2010-06-29 2014-03-25 Spansion Llc Method and system for thin multi chip stack package with film on wire and copper wire
US8853708B2 (en) * 2010-09-16 2014-10-07 Tessera, Inc. Stacked multi-die packages with impedance control
US8536717B2 (en) * 2012-01-10 2013-09-17 Xilinx, Inc. Integrated circuit package and method of assembling an integrated circuit package
KR102247916B1 (ko) * 2014-01-16 2021-05-04 삼성전자주식회사 계단식 적층 구조를 갖는 반도체 패키지

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030042615A1 (en) * 2001-08-30 2003-03-06 Tongbi Jiang Stacked microelectronic devices and methods of fabricating same
US20120241979A1 (en) * 2011-03-21 2012-09-27 Daesik Choi Integrated circuit packaging system with step mold and method of manufacture thereof
CN103367366A (zh) * 2012-03-31 2013-10-23 南亚科技股份有限公司 半导体封装构件

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111668104A (zh) * 2019-03-07 2020-09-15 无锡华润安盛科技有限公司 一种芯片封装结构及芯片封装方法
CN111668104B (zh) * 2019-03-07 2022-07-01 无锡华润安盛科技有限公司 一种芯片封装结构及芯片封装方法
CN112397498A (zh) * 2019-08-01 2021-02-23 联发科技股份有限公司 半导体封装

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