CN109216293A - The bonded structure and adhering method of chip and electronic circuit - Google Patents
The bonded structure and adhering method of chip and electronic circuit Download PDFInfo
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- CN109216293A CN109216293A CN201710532536.1A CN201710532536A CN109216293A CN 109216293 A CN109216293 A CN 109216293A CN 201710532536 A CN201710532536 A CN 201710532536A CN 109216293 A CN109216293 A CN 109216293A
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- chip
- electronic circuit
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000000463 material Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000005253 cladding Methods 0.000 claims abstract description 3
- 239000003822 epoxy resin Substances 0.000 claims description 10
- 229920000647 polyepoxide Polymers 0.000 claims description 10
- 229920006254 polymer film Polymers 0.000 claims description 10
- 238000012545 processing Methods 0.000 claims description 9
- 239000004033 plastic Substances 0.000 claims description 8
- 229920003023 plastic Polymers 0.000 claims description 8
- 239000003292 glue Substances 0.000 claims description 7
- 241000218202 Coptis Species 0.000 claims description 6
- 235000002991 Coptis groenlandica Nutrition 0.000 claims description 6
- 210000003850 cellular structure Anatomy 0.000 claims description 4
- 238000004132 cross linking Methods 0.000 claims description 4
- 229920000642 polymer Polymers 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 4
- RSWGJHLUYNHPMX-UHFFFAOYSA-N 1,4a-dimethyl-7-propan-2-yl-2,3,4,4b,5,6,10,10a-octahydrophenanthrene-1-carboxylic acid Chemical compound C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 claims description 3
- SMZOUWXMTYCWNB-UHFFFAOYSA-N 2-(2-methoxy-5-methylphenyl)ethanamine Chemical compound COC1=CC=C(C)C=C1CCN SMZOUWXMTYCWNB-UHFFFAOYSA-N 0.000 claims description 3
- NIXOWILDQLNWCW-UHFFFAOYSA-N 2-Propenoic acid Natural products OC(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 claims description 3
- 229910010293 ceramic material Inorganic materials 0.000 claims description 3
- 238000003780 insertion Methods 0.000 claims description 3
- 230000037431 insertion Effects 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 claims description 2
- 239000010426 asphalt Substances 0.000 claims 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 238000003466 welding Methods 0.000 abstract description 8
- 230000008595 infiltration Effects 0.000 abstract description 2
- 238000001764 infiltration Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 11
- 238000012360 testing method Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- 230000005855 radiation Effects 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 229910021389 graphene Inorganic materials 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000011469 building brick Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 238000007711 solidification Methods 0.000 description 2
- 230000008023 solidification Effects 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000003113 alkalizing effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000011231 conductive filler Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 231100000331 toxic Toxicity 0.000 description 1
- 230000002588 toxic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/63—Connectors not provided for in any of the groups H01L24/10 - H01L24/50 and subgroups; Manufacturing methods related thereto
- H01L24/64—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
The present invention provides the bonded structure and adhering method of a kind of chip and electronic circuit, wherein chip is fixed on chip carrier, chip is electrically connected pin, and the chip and pin for being fixed on chip carrier are packaged material cladding together, and a part of encapsulating material that exposes of pin becomes outer pin；Electronic circuit includes porosity substrate and the circuit for being attached to porosity substrate, wherein circuit is formed by conductive ink and is penetrated into porosity substrate, the outer pin of encapsulating structure is inserted directly into circuit by mechanical force and is electrically connected, outer pin directly can be directly electrically connected with the circuit in infiltration porosity substrate, area in electrical contact can be increased, compared to traditional welding and surface adhering technical, bonded structure of the invention and adhering method have the advantages that quick, simple and save cost.
Description
Technical field
The present invention relates to the electrical bonded structures and method of a kind of chip of integrated circuit and electronic circuit, especially a kind of
It is directly inserted into the bonded structure and adhering method that electronic circuit is electrically connected.
Background technique
Integrated circuit (integrated circuit, abridge IC) mainly passes through semiconductor processing technology for many electronics
Component (main includes semiconductor subassembly and passive component) minimizes and then manufactures a kind of electronic building brick completed, the manufacture of IC
Journey specifically includes that IC design, manufacture of semiconductor and encapsulation (packaging), and manufacture is completed through the above steps
Integrated circuit package is commonly referred to as IC component or chip (chip).The crystal grain (die) manufactured by manufacture of semiconductor contains
The electronic building brick (mainly including semiconductor subassembly and passive component) of many microminiaturizations, then by crystal grain and is led by encapsulation step
Coil holder (lead frame) is coated among a kind of shell being made of encapsulating material, is protected crystal grain using this shell and is mentioned
For the heat dissipation path of crystal grain, current common encapsulating material mainly includes plastics and ceramics, wherein being again large with plastics.
The chip that manufacture is completed, which needs to be installed to circuit board again or is electrically adhered to electronic circuit, could become finally
The electrical bonding way of circuit unit or electronic product, chip and circuit board or electronic circuit can be distinguished are as follows: pin insert type
(Pin-Through-Hole, PTH) and surface adhesion type (Surface Mount Technology, SMT) two major classes, PTH group
The pin of part is usually fine acicular or sheet metal, in the through hole (Via) of insertion pedestal (Socket) or circuit board
It is welded and fixed；SMT component is first pasted on circuit board again to be welded and fixed.
The pin of chip is mainly electrically bonded in electronic circuit using conductive solder by welding technique used at present, is welded
The mode connect is that solder is first heated to fusing point, enables the solder attachment of melting in the pin of chip and the surface of electronic circuit,
Electrically bonding is completed after solder cooling and solidifying.However this welding technique, in the European patent EP 2833393A1 having disclosed
Just it is stated that, the thermal stress generated in welding process because of high temperature may will affect the performance of chip.In order to solve this problem,
A kind of conductive conducting resinl (such as the elargol being commonly called as) is completed by exploitation and is applied to the electricity of chip and electronic circuit
Property bonding processing procedure, although conducting resinl can reduce electrically bonding needed for temperature, there may be skies for the conducting resinl after solidifying
Gap, not only production capacity is lower, but also the noble metal powder contained in conducting resinl also will increase the cost of manufacture.
General common conducting resinl further include: anisotropy conductive film (Anisotropic Conductive Film,
ACF), anisotropic conductive elargol (Anisotropic conductive adhesives, ACA) and anisotropic conductive adhesive paste
(Anisotropic conductive paste, ACP)；Although these conducting resinls are free of lead and other toxic metals, and
Bonding process can be carried out in the point of very little, but it is then further in published Chinese invention patent publication No. CN104993041A
Indicating that this kind of conducting resinl still has some problems, the problem includes the performance of this kind of conducting resinl and unstable, due to
Metal migration under electric field, and over time, the oxidation of the metal packing contained in conducting resinl can all lead to conductivity
Decaying, and longer problem when and solidification unstable for the adhesive effect between different substrate materials.
Therefore, current die bonding technology there is a problem of following, and welding temperature is high in (1) welding or solidification process,
The thermal stress of generation may will affect the performance of chip；(2) curing time of anisotropic conductive elargol (ACA) is longer；(3) different
The bonding production capacity of side's property conducting resinl (ACP)；And the higher cost of the conducting resinl of (4) containing noble metal filler.
Summary of the invention
In order to improve above-mentioned known technology there are the problem of, the invention proposes the bonding knots of a kind of chip and electronic circuit
Structure and adhering method.
A kind of embodiment of the bonded structure of chip and electronic circuit of the present invention, comprising: chip carrier is fixed on chip carrier
The pin and electronic circuit that chip and chip are electrically connected；The chip and pin for being wherein fixed on chip carrier are packaged together
The a part of encapsulating material that exposes of material cladding, pin becomes outer pin；Electronic circuit includes porosity substrate and is attached to more
The circuit of permeability substrate, wherein circuit is formed by conductive ink and is penetrated among porosity substrate, and outer pin passes through machinery
Power is inserted directly into circuit and is electrically connected.
Preferably, the bonded structure of chip of the present invention and electronic circuit further comprises fixed glue, the fixed glue coating
In the bonding location of outer pin and circuit, to fix and prevent from falling off.
Preferably, wherein chip is RFID chip, the circuit is RFID antenna.
An aspect of of the present present invention includes the adhering method of a kind of chip and electronic circuit, comprising: chip is fixed on chip
Seat；Chip and pin are electrically connected；The chip and pin of chip carrier, some of pin are coated and fixed on using encapsulating material
Exposing encapsulating material becomes outer pin；In the circuit forming surface of porosity substrate, wherein circuit is formed simultaneously by conductive ink
And it penetrates among porosity substrate and constitutes electronic circuit；And outer pin is inserted directly into circuit and is electrically connected.
Preferably, the adhering method of chip of the present invention and electronic circuit further comprises: in the viscous of outer pin insertion circuit
It connects position and outer pin is fixed on to the bonding location using epoxy resin.
Wherein chip is electrically connected by gold thread and by routing processing procedure and pin.
Wherein chip is to be fixed on chip carrier by epoxy resin.
Wherein the material of porosity substrate includes: paper and thin polymer film are therein any, and wherein thin polymer film passes through
Surfaction processing is crossed so that the crosslinking of polymer and organic ring structure are broken into a kind of material with cellular structure.
Wherein thin polymer film includes that PET and PI film is therein any.
Wherein encapsulating material includes that ceramic material and plastic material are therein any.
The beneficial effects of the present invention are outer pin of the invention can be directly straight with the circuit in infiltration porosity substrate
It connects and is electrically connected, area in electrical contact can be increased, compared to traditional welding and surface adhering technical, core of the present invention
The bonded structure and adhering method of piece and electronic circuit have the advantages that quick, simple and save cost.
The detailed content of other effects and embodiment for the present invention, cooperation schema are described as follows.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The some embodiments recorded in application, for those of ordinary skill in the art, without creative efforts,
It can also be obtained according to these attached drawings other attached drawings.
Fig. 1 is a kind of structure profile diagram of embodiment of the bonded structure of chip and electronic circuit of the present invention；
Fig. 2 is the vertical view structural map of Fig. 1；
Fig. 3 is a kind of step flow chart of embodiment of the adhering method of chip and electronic circuit of the present invention；
Fig. 4 is the structure profile diagram of another embodiment of the bonded structure of chip and electronic circuit of the present invention.
Symbol description
10 chip carrier, 20 chip
21 gold thread, 30 pin
31 outer pin, 40 electronic circuit
41 porosity substrate, 42 circuit
50 encapsulating materials 60 fix glue
Specific embodiment
It is a kind of construction of embodiment of the bonded structure of chip and electronic circuit of the present invention referring initially to Fig. 1 and Fig. 2
Cross-section diagram and vertical view structural map.Wherein in order to be conducive to identification, the encapsulating material 50 in Fig. 2 is represented by dotted lines, and remaining each group
Part is indicated with solid line.
A kind of embodiment of the bonded structure of chip and electronic circuit of the present invention, comprising: chip carrier 10 is fixed on chip carrier
The pin 30 and electronic circuit 40 that 10 chip 20 and chip 20 is electrically connected；Wherein it is fixed on the chip 20 of chip carrier 10
It is packaged material 50 together with pin 30 to coat, a part of encapsulating material 50 that exposes of pin 30 becomes outer pin 31；Electronics electricity
Road 40 includes porosity substrate 41 and the circuit 42 for being attached to porosity substrate 41, and wherein circuit 42 is formed simultaneously by conductive ink
And it penetrates among porosity substrate 41.The direction that wherein outer pin 31 is directed to circuit 42 extends, preferably, the end of outer pin 31
End is spine shape, is inserted directly into circuit 42 by mechanical force convenient for outer pin 31 and is electrically connected.
An aspect of of the present present invention includes the adhering method of a kind of chip and electronic circuit, referring to Fig. 3, being chip of the present invention
With a kind of step flow chart of embodiment of the adhering method of electronic circuit, including the following steps:
Chip is fixed on chip carrier；
Chip and pin are electrically connected；
The chip and pin of chip carrier are coated and fixed on using encapsulating material, a part of encapsulating material that exposes of pin becomes
Outer pin；
In the circuit forming surface of porosity substrate, wherein circuit is to be formed by conductive ink and penetrated into porosity substrate
Among constitute the electronic circuit；And
Outer pin is inserted directly into circuit to be electrically connected.
Wherein chip 20 is to be fixed on chip carrier 10 using technology known to field of semiconductor package, such as use epoxy
Chip 20 is pasted on chip carrier 10 by resin (the insulation elargol being commonly called as), is fixed on the chip 20 of chip carrier 10 again by gold thread 21
And it is electrically connected by routing (wire bonding) processing procedure and pin 30, wherein encapsulating material 50 includes ceramic material and modeling
Expect that material is therein any, the plastic material includes: epoxy resin (Epoxy), and resin and acrylic acid are therein any
Kind；In other embodiments, the material of chip carrier 10 is also possible to metal such as copper.In chip of the present invention and electronic circuit
A kind of better embodiment of bonded structure can further reduce the encapsulation of chip without using lead frame (lead frame)
The size of structure；Preferably, chip 20 therein is wireless radio-frequency identification chip (abbreviation RFID chip), the electronic circuit
40 be the radio frequency identifying antenna (abbreviation RFID antenna) being electrically connected with wireless radio-frequency identification chip.
Wherein the embodiment of porosity substrate 41 is paper, and the conductive ink to form circuit 42 can penetrate into porous
Property substrate 41 among, then deeper conductive region is formed in porosity substrate 41, compared to tradition in circuit board surface with gold
Belong to the circuit that foil is formed, circuit 42 of the invention can form a kind of circuit 42 with deeper conductive region, outer pin 31
After being inserted directly into circuit 42 by mechanical force, biggish contact area can be obtained between outer pin 31 and circuit 42, and
Obtain more reliable electric connection effect.Wherein a kind of embodiment of conductive ink is containing graphene, graphite flake and metal
The conductive ink of powder (such as silver powder) any one of them conductive filler.
Preferably, porosity substrate 41 can be thin polymer film, thin polymer film includes that PET and PI film is therein any
Kind, wherein thin polymer film is handled by surfaction, such as by alkalizing, at ultraviolet light/ozone any one of them surface
Reason, so that the crosslinking of polymer and organic ring structure are broken into a kind of material with cellular structure, therefore, to be formed
The conductive ink of circuit 42 can penetrate among porosity substrate 41, and deeper conduction region is then formed in porosity substrate 41
Domain, and outer pin 31 can be allowed to penetrate or be pierced into.
In general, tradition is about with the circuit thickness that metal foil is formed in circuit board surfaceIn the present invention
A kind of better embodiment, the thickness by penetrating into the circuit 42 that conductive ink among porosity substrate 41 is formed can be with
ReachIt can be with after outer pin 31 is inserted directly into circuit 42 by mechanical force, between outer pin 31 and circuit 42
Biggish contact area is obtained, therefore in the case of no use welding or cured processing procedure, still can be obtained reliable
It is electrically connected effect.
According to different applications, outer pin 31 can be applied with the porosity substrate 41 of penetrating electrons circuit 40 in others,
The development length of outer pin 31 can also be controlled among the circuit 42 that can only be pierced into electronic circuit 40, preferably, outer pin
31 Design of length is within the thickness of circuit 42.
Referring to Fig. 4, preferably, the bonded structure of chip of the present invention and electronic circuit another embodiment, into one
Step includes fixed glue 60, and the fixed glue 60 is coated on the bonding location of outer pin 31 and circuit 42, to fix and prevent core
Piece 20 (including encapsulating material 50 and pin 30) falls off from the porosity substrate 41 of electronic circuit 40.
[embodiment one]
In a kind of embodiment of the bonded structure of chip of the present invention and electronic circuit, chip 20 uses epoxy resin (custom
The insulation elargol of title) it pastes and is fixed on chip carrier 10, the chip 20 of chip carrier 10 is fixed on again by 0.8 mil (mi l) gold thread
It 21 and is electrically connected by routing processing procedure and pin 30, chip carrier will be fixed on by reusing epoxy resin as encapsulating material 50
10 chip 20 and pin 30 is coated on wherein, and a part of encapsulating material 50 that exposes of pin 30 becomes outer pin 31, outer pin
31 are having 0.5 millimeter (mm) lower than the development length below of encapsulating material 50；Chip 20 therein is RFID chip, the electricity
Sub-circuit 40 is the RFID antenna being electrically connected with RFID chip.
It is paper in the material of the porosity substrate 41 of the electronic circuit 40 of the present embodiment one, circuit 42 is by containing graphene
(Graphene) conductive ink, which is formed and penetrated into, constitutes the electronic circuit 40 among porosity substrate 41, wherein porous
Property substrate 41 and 42 overall thickness of circuit be 0.2 millimeter (mm)；Outer pin 31 can be inserted directly into electricity by mechanical force or manually
Sub-circuit 40 and porosity substrate 41 is penetrated, is then electrically connected with circuit 42.
[contrast sample]
In order to carry out performance comparison, we have manufactured another RFID tag (hereafter by traditional electrical adhering method
Referred to as contrast sample), the electronic circuit 40 in the RFID antenna and previous embodiment one of contrast sample as RFID antenna is identical,
And using anisotropic conductive adhesive paste (ACP) bonding RFID chip and RFID antenna, then solidifying 30 seconds at 180 DEG C makes RFID core
Piece and RFID antenna are completed to be electrically connected.Then the bonded structure of chip of the present invention and electronic circuit and contrast sample are carried out down
The comparison of column illustrates the bonded structure performance of chip and electronic circuit of the present invention.
Table 1 is please referred to, is the test result for reading distance, both is compared in the test result for reading distance, it is of the invention
Read the reading distance that distance is greater than contrast sample.
Table 1
| Read distance (cm) | Equivalent radiation power EIRP (dBm) | |
| Embodiment one | 64 | -15 |
| Contrast sample | 47 | -15 |
Table 2 is please referred to, is the test result that distance is written, both compares the test result in write-in distance, it is of the invention
Write-in distance is about twice of contrast sample.
Table 2
| Write-in distance (cm) | Equivalent radiation power EIRP (dBm) | |
| Embodiment one | 41 | -15 |
| Contrast sample | 21 | -15 |
Table 3 is please referred to, is the test result of write time, the two is compared under conditions of identical data length is written and is existed
The test result of write time, writing speed of the invention are about twice of contrast sample.
Table 3
| Time (ms) | Equivalent radiation power EIRP (dBm) | |
| Embodiment one | 2.767 | -15 |
| Contrast sample | 4.042 | -15 |
Table 4 is please referred to, is multiple radiant power test results to angle, compares the two and is surveyed multiple to the radiant power at angle
Test result, it can be found that the two generally have it is consistent as a result, and sensitivity in each gap to angle also without too big
Difference (in the range of 1dam).
Table 4
Embodiment one
| To angle (degree) | 0 | 45 | 90 | 135 | 180 |
| Equivalent radiation power EIRP (dBm) | -30 | -30 | -29 | -28 | -29 |
Contrast sample
| To angle (degree) | 0 | 45 | 90 | 135 | 180 |
| Equivalent radiation power EIRP (dBm) | -32 | -33 | -32 | -31 | -32 |
Therefore, it will be seen that by above test and comparison result, according to the present invention the bonded structure of chip and electronic circuit
The RFID label manufactured with adhering method, in contrast to the RFID label manufactured using traditional electrical adhering method, above-mentioned each
The test result of performance show, according to the present invention manufacture RFID volumes of the bonded structure and adhering method of chip and electronic circuit
The above-mentioned properties of target, can't be inferior to the RFID label of traditional technology manufacture, or even be better than traditional skill in certain performances
The RFID label of art manufacture.On the other hand, the bonded structure and adhering method of chip and electronic circuit proposed by the present invention, is not required to
The heating stepses for wanting any time-consuming, will not influence the performance of chip.
Embodiment described above and/or embodiment are only the preferred embodiments to illustrate to realize the technology of the present invention
And/or embodiment, not the embodiment of the technology of the present invention is made any form of restriction, any those skilled in the art
Member changes or is modified to other equivalent when can make a little in the range for not departing from technological means disclosed in the content of present invention
Embodiment, but still should be regarded as and the substantially identical technology or embodiment of the present invention.
Claims (17)
1. the bonded structure of a kind of chip and electronic circuit characterized by comprising chip carrier, the core for being fixed on the chip carrier
The pin and electronic circuit that piece and the chip are electrically connected；The chip and the pin for being wherein fixed on the chip carrier are together
Packed material cladding, some of the pin expose the encapsulating material as outer pin；The electronic circuit includes porosity base
Plate and the circuit for being attached to the porosity substrate, which formed by conductive ink and penetrated among the porosity substrate,
The outer pin is inserted directly into the circuit and is electrically connected.
2. the bonded structure of chip as described in claim 1 and electronic circuit, which is characterized in that the chip is RFID chip, should
Electronic circuit is RFID antenna.
3. the bonded structure of chip as described in claim 1 and electronic circuit, which is characterized in that the chip be by gold thread and
It is electrically connected by routing processing procedure and the pin.
4. the bonded structure of chip as described in claim 1 and electronic circuit, which is characterized in that the chip is to pass through epoxy resin
It is fixed on the chip carrier.
5. the bonded structure of chip as described in claim 1 and electronic circuit, which is characterized in that the porosity substrate includes: paper
Therein any with thin polymer film, which is handled by surfaction so that the crosslinking of polymer and organic ring
Structural break becomes a kind of material with cellular structure.
6. the bonded structure of chip as claimed in claim 5 and electronic circuit, which is characterized in that the thin polymer film includes PET
It is therein any with PI film.
7. the bonded structure of chip as described in claim 1 and electronic circuit, which is characterized in that the encapsulating material includes ceramic material
Material and plastic material are therein any.
8. the bonded structure of chip as claimed in claim 7 and electronic circuit, which is characterized in that the plastic material includes: epoxy
Resin, resin and acrylic acid are therein any.
9. the bonded structure of chip as described in claim 1 and electronic circuit, which is characterized in that including fixed glue, the fixation glue
It is coated on the bonding location of the outer pin He the circuit.
10. the adhering method of a kind of chip and electronic circuit characterized by comprising
Chip is fixed on chip carrier；
The chip and pin are electrically connected；
The chip and the pin of the chip carrier are coated and fixed on using encapsulating material, some of the pin exposes the package material
Material becomes outer pin；
In the circuit forming surface of porosity substrate, which formed by conductive ink and penetrated among the porosity substrate
Constitute the electronic circuit；And
The outer pin is inserted directly into the circuit to be electrically connected.
11. the adhering method of chip as claimed in claim 10 and electronic circuit, which is characterized in that the chip is to pass through asphalt mixtures modified by epoxy resin
Rouge is fixed on the chip carrier.
12. the adhering method of chip as claimed in claim 10 and electronic circuit, which is characterized in that the chip be using gold thread simultaneously
And it is electrically connected by routing processing procedure and the pin.
13. the adhering method of chip as claimed in claim 10 and electronic circuit, which is characterized in that the porosity substrate includes:
Paper and thin polymer film are therein any, which handles by surfaction so that the crosslinking of polymer and organic
Ring structure is broken into a kind of material with cellular structure.
14. the adhering method of chip as claimed in claim 13 and electronic circuit, which is characterized in that the thin polymer film includes
PET and PI film is therein any.
15. the adhering method of chip as claimed in claim 10 and electronic circuit, which is characterized in that the encapsulating material includes ceramics
Material and plastic material are therein any.
16. the adhering method of chip as claimed in claim 15 and electronic circuit, which is characterized in that the plastic material includes: ring
Oxygen resin, resin and acrylic acid are therein any.
17. the adhering method of chip as claimed in claim 10 and electronic circuit, which is characterized in that be included in outer pin insertion
The outer pin is fixed on the bonding location using epoxy resin by the bonding location of the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710532536.1A CN109216293A (en) | 2017-07-03 | 2017-07-03 | The bonded structure and adhering method of chip and electronic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710532536.1A CN109216293A (en) | 2017-07-03 | 2017-07-03 | The bonded structure and adhering method of chip and electronic circuit |
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| Publication Number | Publication Date |
|---|---|
| CN109216293A true CN109216293A (en) | 2019-01-15 |
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| CN201710532536.1A Pending CN109216293A (en) | 2017-07-03 | 2017-07-03 | The bonded structure and adhering method of chip and electronic circuit |
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|---|---|---|---|---|
| CN1463414A (en) * | 2001-06-14 | 2003-12-24 | A·S·K·股份有限公司 | Method for connecting chip to antenna of radio frequency identification device of contactless chip card variety |
| CN102403239A (en) * | 2010-09-13 | 2012-04-04 | 新科金朋有限公司 | Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in fo-wlcsp |
| CN203967239U (en) * | 2013-10-08 | 2014-11-26 | 北京北印中源科技有限公司 | A kind of full papery ultrahigh frequency RFID antenna of ink jet printing |
| CN204375740U (en) * | 2015-01-27 | 2015-06-03 | 深圳市梦工厂科技有限公司 | High-density integrated circuit package structure |
| CN105733367A (en) * | 2014-12-10 | 2016-07-06 | 赖中平 | Radio frequency identification tag conductive ink composition, antenna structure, and antenna manufacturing method |
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2017
- 2017-07-03 CN CN201710532536.1A patent/CN109216293A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1463414A (en) * | 2001-06-14 | 2003-12-24 | A·S·K·股份有限公司 | Method for connecting chip to antenna of radio frequency identification device of contactless chip card variety |
| CN102403239A (en) * | 2010-09-13 | 2012-04-04 | 新科金朋有限公司 | Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in fo-wlcsp |
| CN203967239U (en) * | 2013-10-08 | 2014-11-26 | 北京北印中源科技有限公司 | A kind of full papery ultrahigh frequency RFID antenna of ink jet printing |
| CN105733367A (en) * | 2014-12-10 | 2016-07-06 | 赖中平 | Radio frequency identification tag conductive ink composition, antenna structure, and antenna manufacturing method |
| CN204375740U (en) * | 2015-01-27 | 2015-06-03 | 深圳市梦工厂科技有限公司 | High-density integrated circuit package structure |
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