CN109216171A - A method of reducing wide band gap semiconductor device ohmic contact resistance - Google Patents

A method of reducing wide band gap semiconductor device ohmic contact resistance Download PDF

Info

Publication number
CN109216171A
CN109216171A CN201710527475.XA CN201710527475A CN109216171A CN 109216171 A CN109216171 A CN 109216171A CN 201710527475 A CN201710527475 A CN 201710527475A CN 109216171 A CN109216171 A CN 109216171A
Authority
CN
China
Prior art keywords
photoresist
layer
metal
nanosphere
passivation layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710527475.XA
Other languages
Chinese (zh)
Inventor
孙瑞泽
梁永齐
赵策洲
蔡宇韬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Industrial Park Xin Guo Great Research Institute
Xian Jiaotong Liverpool University
National University of Singapore
Original Assignee
Suzhou Industrial Park Xin Guo Great Research Institute
Xian Jiaotong Liverpool University
National University of Singapore
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Industrial Park Xin Guo Great Research Institute, Xian Jiaotong Liverpool University, National University of Singapore filed Critical Suzhou Industrial Park Xin Guo Great Research Institute
Priority to CN201710527475.XA priority Critical patent/CN109216171A/en
Publication of CN109216171A publication Critical patent/CN109216171A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00Manufacture or treatment of nanostructures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/452Ohmic electrodes on AIII-BV compounds

Abstract

The invention discloses a kind of methods for reducing wide band gap semiconductor device ohmic contact resistance, wherein, the material of the wide band gap semiconductor device is iii-v semiconductor material with wide forbidden band, the material successively includes substrate, buffer layer, channel layer and alloy barrier layer from the bottom to top, it the described method comprises the following steps: step 1, deposit passivation layer;Step 2 coats photoresist, and forms photoresist window;Step 3, Etch Passivation, and form passivation layer window;Step 4, coated with nano ball;Step 5 forms nano grooves;Step 6 coats photoresist, and forms photoresist window;Step 7, electron beam evaporation or magnetron sputtering multiple layer metal;Step 8, the removing of multiple layer metal;Step 9, rapid thermal annealing form Ohmic contact.The contact area of electrode metal and wide bandgap semiconductor is significantly greatly increased in method of the invention, reduces the ohmic contact resistance of wide band gap semiconductor device, enhances device performance, improves process efficiency, reduces process costs.

Description

A method of reducing wide band gap semiconductor device ohmic contact resistance
Technical field
The present invention relates to Wide Bandgap Semiconductor Technology fields, are carved more particularly to one kind based on nanosphere lithography and plasma The method of the reduction iii-v wide band gap semiconductor device ohmic contact resistance of erosion technology.
Background technique
Iii-v wide band gap semiconductor device have wide direct band gap, high electronics saturation drift velocity, high breakdown field strength, The advantages that anticorrosive and radiation hardness.Compared with silicon-based devices, the switching speed of wide band gap semiconductor device is high, and conducting resistance is small, Power density greatly promotes, and can work in hot environment.The quality of the Ohmic contact of wide band gap semiconductor device is largely On determine the working performance of device.Realize that the common method of the Ohmic contact of wide-bandgap power devices is included in 850- at present Fast speed heat is carried out to multiple layer metal at 900 DEG C (usually Ti/Al/X/Au, wherein X is barrier metal, including Ni, Pt or Mo) Annealing.Main deficiency existing for the production method of the type Ohmic contact is: multiple layer metal and semiconductor material with wide forbidden band connect Contacting surface product is same or less with ohmic contact regions area, and the optimization of ohmic contact resistance rate is mainly adjusted by multiple layer metal Thickness combination is realized with annealing conditions, but this method generates ohmic contact resistance and is typically greater than 0.5 Ω mm.
Summary of the invention
To solve the above-mentioned problems, the invention discloses a kind of sides for reducing wide band gap semiconductor device ohmic contact resistance Method, this method utilize nanosphere lithography technology, can be primary in device Ohm contact electrode region without using electron beam exposure A large amount of nanometer scale lithography windows are formed, and form groove using plasma etching, electrode metal and broad stopband is significantly greatly increased The contact area of semiconductor reduces the ohmic contact resistance of device.
Present invention technical solution used for the above purpose is:
A method of reducing wide band gap semiconductor device ohmic contact resistance, which is characterized in that partly lead the broad stopband The material of body device is iii-v semiconductor material with wide forbidden band, which successively includes substrate, buffer layer, channel from the bottom to top Layer and alloy barrier layer, the described method comprises the following steps:
Step 1, deposit passivation layer
Si is deposited on the alloy barrier layer3N4Or SiO2Passivation layer;
Step 2 coats photoresist, and forms photoresist window
Photoresist is coated on the passivation layer that step 1 is deposited, and Ohm contact electrode region is removed by photoetching development Photoresist, formed photoresist window;
Step 3, Etch Passivation, and form passivation layer window
Etch Passivation completely removes the passivation layer in Ohm contact electrode region, forms passivation layer window, then removes Photoresist;
Step 4, coated with nano ball
With the suspension of nanosphere the surface of the resulting iii-v semiconductor material with wide forbidden band of step 3 coat single layer or Double-layer nanometer ball;
Step 5 forms nano grooves
The surface of the iii-v semiconductor material with wide forbidden band obtained of etch step four forms nano grooves, wherein by institute Single or double layer nanosphere is stated as etch mask plate, plasma passes through the III- obtained of nanometer sphere gap etch step four The surface of V race semiconductor material with wide forbidden band, to form a large amount of nano grooves in the Ohm contact electrode region etch, then Remove the nanosphere on surface;
Step 6 coats photoresist, and forms photoresist window
Photoresist is coated on the surface of step 5 iii-v semiconductor material with wide forbidden band obtained, and passes through photoetching Photoresist in development removal Ohm contact electrode region, forms photoresist window;
Step 7, electron beam evaporation or magnetron sputtering multiple layer metal
On the surface of the resulting iii-v semiconductor material with wide forbidden band of step 6, splashed using electron beam evaporation or magnetic control Multiple layer metal is penetrated, in Ohm contact electrode region, the multiple layer metal is directly contacted with the alloy barrier layer;
Step 8, the removing of multiple layer metal
By the photoresist and multilayer outside the Ohm contact electrode region of iii-v semiconductor material with wide forbidden band obtained by step 7 Metal-stripping;
Step 9, rapid thermal annealing form Ohmic contact
Using rapid thermal annealing, the rapid thermal annealing 30-60s under 600-900 DEG C of nitrogen atmosphere forms Ohmic contact.Root According to some embodiments of the present invention, the deposit passivation layer of step 1 is by plasma enhanced chemical vapor deposition or induction coupling Close what plasma chemical vapor deposition carried out, the passivation layer thickness is 20~100nm.
According to some embodiments of the present invention, the material of the nanosphere be polyphenyl hexene, silica or silicon, it is a diameter of 20~100nm, the suspension mass percent of the nanosphere are 5% to 40%, and solvent is water or ethyl alcohol.
According to some embodiments of the present invention, the diameter of the nanosphere is equal to passivation layer thickness.
According to some embodiments of the present invention, spin-coating method coated with nano ball is used in step 4, revolving speed is 1000 to 8000 Rpm.
According to some embodiments of the present invention, step 2 is with photoresist described in step 6 with a thickness of 0.5-1.5 μm.
According to some embodiments of the present invention, the fast speed heat under 800 DEG C of nitrogen atmospheres of the rapid thermal annealing in step 9 is moved back Fiery 30s.
According to some embodiments of the present invention, the depth of the resulting nano grooves of step 5 is less than, greater than or equal to institute The thickness of barrier layer is stated, the depth of preferred nano grooves is the half of the thickness of the barrier layer.
According to some embodiments of the present invention, the etching using plasma etching in step 5, including for etching width Gaseous plasma etching of the chloro of bandgap semiconductor material containing chlorine and the oxygroup for modifying nanosphere diameter dimension are oxygen-containing Or fluorine-based fluorine-containing plasma etching.
According to some embodiments of the present invention, multiple layer metal described in step 7 is Ti/Al/Ni/Au or Ti/Al/Ni/ Four layers of metal of TiN, thickness are followed successively by 30/120/50/50nm, and wherein Ni metal can be replaced Ti, Mo or Pt;Or it is described Multiple layer metal may be three layers of Ti/Al/TiN metal, and thickness is followed successively by 30/120/50nm.
According to some embodiments of the present invention, the material of the substrate is SiC, Al2O3Or Si, the buffer layer and channel The material of layer is AlN, GaN or AlGaN etc., and the material of the barrier layer is AlGaN, AlN, InAlN or InAlGaN.
The invention has the benefit that
A kind of method of reduction wide band gap semiconductor device ohmic contact resistance of the invention, utilizes single or double layer nanometer Ball can be in device Ohm contact electrode region without using electron beam exposure by photoetching and plasma etching as exposure mask A large amount of nanoscale grooves are once formed, the contact area of electrode metal and wide bandgap semiconductor is significantly greatly increased, reduce broad stopband The ohmic contact resistance of semiconductor devices enhances device performance, improves process efficiency, reduces process costs.
A kind of method of reduction wide band gap semiconductor device ohmic contact resistance of the invention, is widely portable to various pipes The manufacture of modern age semiconductor devices, and with traditional silicon technology, LED technique and high electron mobility transistor process compatible. This method can also be applied on silicon-based devices or other devices, equally because of the work that Ohmic contact area is significantly greatly increased that it has With the ohmic contact resistance of silicon-based devices can be reduced.
Detailed description of the invention
With reference to the accompanying drawings and specific embodiment the present invention is described in further detail:
Fig. 1 is a kind of process flow chart of the method for reduction wide band gap semiconductor device ohmic contact resistance of the invention.
Fig. 2 is a kind of semiconductor material with wide forbidden band, including material is SiC, Al2O3Or the substrate 1 of Si, material be GaN or The buffer layer and channel layer 2 of AlGaN etc., the III-V group semi-conductor materials such as material AlGaN, AlN, InAlN or InAlGaN Alloy barrier layer 3.
Fig. 3 is deposition Si3N4Or SiO2Schematic diagram after passivation layer, including Si3N4Or SiO2Passivation layer 4.
Fig. 4 is the schematic diagram coated after photoresist and the photoresist in photoetching development removal Ohm contact electrode region, including Photoresist 5, Ohm contact electrode region 6.
Fig. 5 is the schematic diagram after the passivation layer in etching removal Ohm contact electrode region.
Fig. 6 is the schematic diagram coated after single layer nanosphere, including material is polyphenyl hexene (PS), silica (SiO2) or silicon (Si) nanosphere 7.
Fig. 7 is the top view after coating single layer nanosphere in Ohm contact electrode region.
Fig. 8 is the top view in gap between ball after coating single layer nanosphere in Ohm contact electrode region, including signal Gap 8 between ball.
Fig. 9 is the schematic diagram coated after double-layer nanometer ball.
Figure 10 is the top view after coating double-layer nanometer ball in Ohm contact electrode region.
Figure 11 is the top view in gap between ball after coating double-layer nanometer ball in Ohm contact electrode region.
Figure 12 is the schematic diagram of formation nano grooves after structure shown in plasma etching Fig. 6, including nano grooves 9.
Figure 13 is the schematic diagram of formation nano grooves after structure shown in plasma etching Fig. 9.
Figure 14 is the schematic diagram removed after nanosphere.
Figure 15 is to coat the schematic diagram after photoresist again.
Figure 16 is the schematic diagram after the photoresist in photoetching development removal Ohm contact electrode region.
Figure 17 is the schematic diagram after electron beam evaporation or magnetron sputtering multiple layer metal, including material is Ti/Al/Ni/Au, Four layers of metal 10 of Ti/Al/Ni/TiN, wherein Ni metal can be replaced Ti, Mo or Pt;Or Ti/Al/TiN three-layer metal 10。
Figure 18 is the schematic diagram after metal-stripping.
Specific embodiment
The present invention is described in further details below in conjunction with specific embodiments and the drawings.
Embodiment 1
Step 1, deposit passivation layer, material Si3N4
One layer is deposited on semiconductor material with wide forbidden band surface using PECVD (plasma enhanced chemical vapor deposition) The Si of 100nm3N4Passivation layer;
Step 2 coats photoresist, and the photoresist in photoetching development removal Ohm contact electrode region
Photoresist AZ5214E is coated on the passivation layer that step 1 is deposited, and is exposed by 90 DEG C of front baking 90s, ultraviolet light 6s Light, 2.38% tetramethyl ammonium hydroxide solution 45s development, removes the photoresist in Ohm contact electrode region, forms photoresist Window, and 30s is dried after 110 DEG C;
Step 3, Etch Passivation remove the passivation layer in Ohm contact electrode region, remove photoresist
Using RIE (reactive ion etching) Etch Passivation, working gas CF4With O2, radio-frequency power 100W, the time 60s completely removes the Si that step 2 is formed by photoetching window3N4Passivation layer forms passivation layer window, hereafter substrate exists Ultrasound removal photoresist in acetone;
Step 4, coated with nano ball, material are silica (SiO2)
Use the silica (SiO of diameter 100nm2) nanosphere suspension, solvent is water, mass ratio 20%.Using Spin-coating method, 30s under 8000 rpms of revolving speeds, step 3 substrate surface coat mono-layer oxidized silicon nanosphere;
Step 5 etches wide bandgap semiconductor surface, forms nano grooves
Using the substrate obtained of RIE (reactive ion etching) etch step four.By single layer nanosphere as etch mask Plate, working gas Cl2With BCl3, radio-frequency power 50W, time 60s.Plasma can etch broad stopband by nanometer sphere gap Semiconductor material surface forms a large amount of nano grooves in Ohm contact electrode region etch.Hereafter using ultrasonic cleaning removal table Face nanosphere;
Step 6 coats photoresist, and the photoresist in photoetching development removal Ohm contact electrode region
Photoresist is coated on step 5 substrate obtained, by front baking identical with step 2 condition, exposure, is shown Shadow, rear baking, remove the photoresist in Ohm contact electrode region, form photoresist window;
Step 7, electron beam evaporation deposition multiple layer metal
Using four layers of Ti/Al/Ni/Au metal of electron beam evaporation deposition, Ohm contact electrode region directly and broad stopband Semiconductor material surface contact;
Step 8, the removing of multiple layer metal
Substrate obtained by step 7 is sequentially placed into acetone and impregnates 30min, acetone ultrasound 2min, isopropanol ultrasound 2min, Deionized water cleaning removes the photoresist outside Ohm contact electrode region with multiple layer metal;
Step 9, rapid thermal annealing form Ohmic contact
Using rapid thermal annealing, the rapid thermal annealing 45s under 850 DEG C of nitrogen atmospheres forms wide band gap semiconductor device Europe Nurse contact.
Embodiment 2
Step 1, deposit passivation layer, material SiO2
One is deposited on semiconductor material with wide forbidden band surface using ICPCVD (inductively coupled plasma chemical vapor deposition) The SiO of layer 50nm2Passivation layer;
Step 2 coats photoresist, and the photoresist in photoetching development removal Ohm contact electrode region
Photoresist AZ5214E is coated on the passivation layer that step 1 is deposited, and is exposed by 90 DEG C of front baking 90s, ultraviolet light 6s Light, 2.38% tetramethyl ammonium hydroxide solution 45s development, removes the photoresist in Ohm contact electrode region, forms photoresist Window, and 30s is dried after 110 DEG C;
Step 3, Etch Passivation remove the passivation layer in Ohm contact electrode region, remove photoresist
Using ICPRIE (sense coupling) Etch Passivation, working gas SF6With O2, radio-frequency power 120W, time 60s completely remove the SiO that step 2 is formed by photoetching window2Passivation layer forms passivation layer window, hereafter By substrate, ultrasound removes photoresist in acetone;
Step 4, coated with nano ball, material are polyphenyl hexene (PS)
Using the suspension of polyphenyl hexene (PS) nanosphere of diameter 50nm, solvent is ethyl alcohol, mass ratio 10%.Using Spin-coating method, 45s under 3000 rpms of revolving speeds, step 3 substrate surface coat the double-deck polyphenyl hexene nanosphere;
Step 5, plasma etching adjust polyphenyl hexene nanometer bulb diameter, plasma etching wide bandgap semiconductor table Face forms nano grooves
Use RIE (reactive ion etching) working gas for O2, radio-frequency power 50W, time 2min, by polyphenyl hexene Nanosphere is etched to diameter 30nm, and nanometer sphere gap increases at this time.It is etched using ICPRIE (sense coupling) Step 4 substrate obtained.By double-layer nanometer ball as etch mask plate, plasma etching working gas is Cl2With BCl3, penetrate Frequency power 100W, time 60s.Plasma can etch semiconductor material with wide forbidden band surface by nanometer sphere gap, connect in ohm Touched electrode region etch forms a large amount of nano grooves.To the adjustable nanometer bulb diameter of the plasma etching treatment of nanosphere with Spacing, and then adjust the width dimensions of nano grooves.Hereafter using ultrasonic cleaning removal nano surface ball;
Step 6 coats photoresist, and the photoresist in photoetching development removal Ohm contact electrode region
Photoresist is coated on step 5 substrate obtained, by front baking identical with step 2 condition, exposure, is shown Shadow, rear baking, remove the photoresist in Ohm contact electrode region, form photoresist window;
Step 7, multiple layer metal
Using four layers of Ti/Al/Ni/TiN metal of magnetron sputtering plating, Ohm contact electrode region directly with broad stopband half Conductor material surface contact;
Step 8, the removing of multiple layer metal
Substrate obtained by step 7 is sequentially placed into acetone and impregnates 30min, acetone ultrasound 2min, isopropanol ultrasound 2min, Deionized water cleaning, by the photoresist and metal-stripping outside Ohm contact electrode region;
Step 9, rapid thermal annealing form Ohmic contact
Using rapid thermal annealing, the rapid thermal annealing 30s under 800 DEG C of nitrogen atmospheres forms wide band gap semiconductor device Europe Nurse contact.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously Limitations on the scope of the patent of the present invention therefore cannot be interpreted as.It should be pointed out that for those of ordinary skill in the art For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to guarantor of the invention Protect range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.

Claims (10)

1. a kind of method for reducing wide band gap semiconductor device ohmic contact resistance, which is characterized in that the wide bandgap semiconductor The material of device is iii-v semiconductor material with wide forbidden band, which successively includes substrate, buffer layer, channel layer from the bottom to top With alloy barrier layer, the described method comprises the following steps:
Step 1, deposit passivation layer
Si is deposited on the alloy barrier layer3N4Or SiO2Passivation layer;
Step 2 coats photoresist, and forms photoresist window
Photoresist is coated on the passivation layer that step 1 is deposited, and the light in Ohm contact electrode region is removed by photoetching development Photoresist forms photoresist window;
Step 3, Etch Passivation, and form passivation layer window
Etch Passivation completely removes the passivation layer in Ohm contact electrode region, forms passivation layer window, then removes photoetching Glue;
Step 4, coated with nano ball
Single or double layer is coated on the surface of the resulting iii-v semiconductor material with wide forbidden band of step 3 with the suspension of nanosphere Nanosphere;
Step 5 forms nano grooves
The surface of the iii-v semiconductor material with wide forbidden band obtained of etch step four forms nano grooves, wherein by the list As etch mask plate, plasma passes through the iii-v obtained of nanometer sphere gap etch step four for layer or double-layer nanometer ball Then the surface of semiconductor material with wide forbidden band is gone to form a large amount of nano grooves in the Ohm contact electrode region etch Except the nanosphere on surface;
Step 6 coats photoresist, and forms photoresist window
Photoresist is coated on the surface of step 5 iii-v semiconductor material with wide forbidden band obtained, and passes through photoetching development The photoresist in Ohm contact electrode region is removed, photoresist window is formed;
Step 7, electron beam evaporation or magnetron sputtering multiple layer metal
It is more using electron beam evaporation or magnetron sputtering on the surface of the resulting iii-v semiconductor material with wide forbidden band of step 6 Layer metal, in Ohm contact electrode region, the multiple layer metal is directly contacted with the alloy barrier layer;
Step 8, the removing of multiple layer metal
By the photoresist and multiple layer metal outside the Ohm contact electrode region of iii-v semiconductor material with wide forbidden band obtained by step 7 Removing;
Step 9, rapid thermal annealing form Ohmic contact
Using rapid thermal annealing, the rapid thermal annealing 30-60s under 600-900 DEG C of nitrogen atmosphere forms Ohmic contact.
2. the method according to claim 1, wherein the deposit passivation layer of step 1 is to pass through plasma enhancing What chemical vapor deposition or inductive couple plasma chemical vapor deposition carried out, the passivation layer thickness is 20~100nm.
3. the method according to claim 1, wherein the material of the nanosphere be polyphenyl hexene, silica or Silicon, a diameter of 20~100nm, the suspension mass percent of the nanosphere are 5% to 40%, and solvent is water or second Alcohol.
4. according to the method described in claim 3, it is characterized in that, the diameter of the nanosphere is equal to passivation layer thickness.
5. revolving speed is the method according to claim 1, wherein using spin-coating method coated with nano ball in step 4 1000 to 8000 rpms.
6. the method according to claim 1, wherein step 2 is with photoresist described in step 6 with a thickness of 0.5- 1.5μm。
7. the method according to claim 1, wherein the rapid thermal annealing in step 9 is in 800 DEG C of nitrogen atmospheres Lower rapid thermal annealing 30s.
8. the method according to claim 1, wherein the depth of the resulting nano grooves of step 5 be less than, etc. In or greater than the barrier layer thickness or the nano grooves depth be the barrier layer thickness half.
9. the method according to claim 1, wherein the etching using plasma in step 5 etches, including For etching gaseous plasma etching of the chloro of semiconductor material with wide forbidden band containing chlorine and being used to modify nanosphere diameter dimension Oxygroup is oxygen-containing or fluorine-based fluorine-containing plasma etching.
10. the method according to claim 1, wherein multiple layer metal described in step 7 be Ti/Al/Ni/Au or Four layers of metal of Ti/Al/Ni/TiN, thickness are followed successively by 30/120/50/50nm, wherein Ni metal can be replaced Ti, Mo or Pt;Or the multiple layer metal may be three layers of Ti/Al/TiN metal, thickness is followed successively by 30/120/50nm.
CN201710527475.XA 2017-06-30 2017-06-30 A method of reducing wide band gap semiconductor device ohmic contact resistance Pending CN109216171A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710527475.XA CN109216171A (en) 2017-06-30 2017-06-30 A method of reducing wide band gap semiconductor device ohmic contact resistance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710527475.XA CN109216171A (en) 2017-06-30 2017-06-30 A method of reducing wide band gap semiconductor device ohmic contact resistance

Publications (1)

Publication Number Publication Date
CN109216171A true CN109216171A (en) 2019-01-15

Family

ID=64992137

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710527475.XA Pending CN109216171A (en) 2017-06-30 2017-06-30 A method of reducing wide band gap semiconductor device ohmic contact resistance

Country Status (1)

Country Link
CN (1) CN109216171A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109994568A (en) * 2019-04-22 2019-07-09 中国工程物理研究院流体物理研究所 A kind of laser triggering high-power half insulation AlGaN/GaN switch of stack architecture
CN110047976A (en) * 2019-04-30 2019-07-23 吉林建筑大学 A kind of preparation method of the quick transistor of solar blind UV
CN111128709A (en) * 2020-01-15 2020-05-08 桂林理工大学 Preparation method of Cu-based GaN HEMT gold-free ohmic contact electrode
CN112379574A (en) * 2020-11-23 2021-02-19 福建中科光芯光电科技有限公司 Low-cost manufacturing method of terahertz photoconductive antenna with nano electrode
CN113284948A (en) * 2020-12-30 2021-08-20 南方科技大学 GaN device and preparation method thereof
CN114188213A (en) * 2021-12-06 2022-03-15 上海稷以科技有限公司 Method for solving problem of transmission failure of silicon carbide wafer
CN114388614A (en) * 2022-03-22 2022-04-22 江苏第三代半导体研究院有限公司 Ohmic contact structure and preparation method and application thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100218815A1 (en) * 2009-11-18 2010-09-02 International Business Machines Corporation Holey electrode grids for photovoltaic cells with subwavelength and superwavelength feature sizes
US20120119760A1 (en) * 2010-11-15 2012-05-17 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Perforated contact electrode on vertical nanowire array
WO2012091325A2 (en) * 2010-12-30 2012-07-05 포항공과대학교 산학협력단 Method for manufacturing light-emitting diode using nano-structures and light-emitting diode manufactured thereby
US20150053929A1 (en) * 2013-08-22 2015-02-26 Board Of Regents. The University Of Texas System Vertical iii-v nanowire field-effect transistor using nanosphere lithography
CN105118780A (en) * 2015-07-30 2015-12-02 中国电子科技集团公司第五十五研究所 Method of reducing GaN HEMT device ohm contact resistance

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100218815A1 (en) * 2009-11-18 2010-09-02 International Business Machines Corporation Holey electrode grids for photovoltaic cells with subwavelength and superwavelength feature sizes
US20120119760A1 (en) * 2010-11-15 2012-05-17 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Perforated contact electrode on vertical nanowire array
WO2012091325A2 (en) * 2010-12-30 2012-07-05 포항공과대학교 산학협력단 Method for manufacturing light-emitting diode using nano-structures and light-emitting diode manufactured thereby
US20150053929A1 (en) * 2013-08-22 2015-02-26 Board Of Regents. The University Of Texas System Vertical iii-v nanowire field-effect transistor using nanosphere lithography
CN105118780A (en) * 2015-07-30 2015-12-02 中国电子科技集团公司第五十五研究所 Method of reducing GaN HEMT device ohm contact resistance

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109994568A (en) * 2019-04-22 2019-07-09 中国工程物理研究院流体物理研究所 A kind of laser triggering high-power half insulation AlGaN/GaN switch of stack architecture
CN110047976A (en) * 2019-04-30 2019-07-23 吉林建筑大学 A kind of preparation method of the quick transistor of solar blind UV
CN110047976B (en) * 2019-04-30 2020-11-06 吉林建筑大学 Preparation method of solar blind ultraviolet photosensitive transistor
CN111128709A (en) * 2020-01-15 2020-05-08 桂林理工大学 Preparation method of Cu-based GaN HEMT gold-free ohmic contact electrode
CN112379574A (en) * 2020-11-23 2021-02-19 福建中科光芯光电科技有限公司 Low-cost manufacturing method of terahertz photoconductive antenna with nano electrode
CN113284948A (en) * 2020-12-30 2021-08-20 南方科技大学 GaN device and preparation method thereof
CN113284948B (en) * 2020-12-30 2022-10-04 南方科技大学 GaN device and preparation method thereof
CN114188213A (en) * 2021-12-06 2022-03-15 上海稷以科技有限公司 Method for solving problem of transmission failure of silicon carbide wafer
CN114188213B (en) * 2021-12-06 2023-04-07 上海稷以科技有限公司 Method for solving problem of transmission failure of silicon carbide wafer
CN114388614A (en) * 2022-03-22 2022-04-22 江苏第三代半导体研究院有限公司 Ohmic contact structure and preparation method and application thereof
CN114388614B (en) * 2022-03-22 2022-06-14 江苏第三代半导体研究院有限公司 Ohmic contact structure and preparation method and application thereof

Similar Documents

Publication Publication Date Title
CN109216171A (en) A method of reducing wide band gap semiconductor device ohmic contact resistance
CN105118780B (en) A method of reducing GaN HEMT device ohmic contact resistances
CN105762078B (en) GaN base nano-channel high electron mobility transistor and production method
CN108122749B (en) A kind of SiC base GaN_HEMT back process based on graphical slide glass
CN104979388B (en) A kind of semiconductor device and its manufacture method
CN103296991A (en) Graphene high-frequency nanomechanical resonator based on flexible substrate and preparing technology of graphene high-frequency nanomechanical resonator
CN105047562B (en) Half deflocculated graphite alkene field effect transistor tube preparation method
CN109872945A (en) A kind of compound substrate, semiconductor devices and its manufacturing method
CN109004029A (en) With metal oxide/silica gatestack GaN base MOS-HEMT device and preparation method thereof
CN105762194B (en) A kind of graphene field effect transistor and its manufacturing method
CN108183151A (en) A kind of LED chip and preparation method thereof
CN106298450B (en) A kind of nano patterned Sapphire Substrate and its preparation method and application
CN103346088A (en) Method for reducing parasitic resistance of graphene top gate FET device
CN104167362B (en) The notched gates gallium nitride base enhancement device preparation method of gallium nitride block layer mask
CN206441733U (en) A kind of high threshold voltage high mobility notched gates MOSFET structure
CN105632900B (en) A kind of preparation method of graphene autoregistration top-gated FET device
CN105810607B (en) Pass through the method and system in situ for etching monitoring and realizing the enhanced HEMT of p-type nitride
CN208368513U (en) Based on metal oxide/silica gatestack GaN base MOS-HEMT device
CN104319237B (en) The method that graphene top gate FET device is prepared by self-registered technology
CN203165903U (en) Semiconductor detector
CN103258739B (en) The preparation method of notched gates nitridation gallio enhancement device based on self-stopping technology etching
CN110911485A (en) Enhanced bidirectional blocking power GaN-based device based on P-type layer and manufacturing method
CN104701137B (en) AlN buffer layers and with the buffer layer chip preparation method
CN209418533U (en) A kind of LED chip
CN103413839A (en) AlGaN based ultraviolet detector with double layers of passive films and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20190115

WD01 Invention patent application deemed withdrawn after publication