CN109166928B - 栅极抽取和注入场效应晶体管及其沟道载流子控制方法 - Google Patents

栅极抽取和注入场效应晶体管及其沟道载流子控制方法 Download PDF

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CN109166928B
CN109166928B CN201810771577.0A CN201810771577A CN109166928B CN 109166928 B CN109166928 B CN 109166928B CN 201810771577 A CN201810771577 A CN 201810771577A CN 109166928 B CN109166928 B CN 109166928B
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廖永波
李平
曾荣周
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李夏
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University of Electronic Science and Technology of China
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Abstract

栅极抽取和注入场效应晶体管及其沟道载流子控制方法，涉及微电子技术和半导体技术。本发明的栅极抽取和注入场效应晶体管在绝缘层上设置有源极、漏极、栅极和沟道半导体区，栅极与沟道半导体区之间设置有栅介质层，其特征在于，所述栅介质层为电阻值为103～1016Ω的薄膜材料；所述沟道半导体区的材质为二维半导体，或者具有二维半导体材料特点的三维半导体。本发明的有益效果是，器件和集成电路的功耗成数量级显著降低。

Description

栅极抽取和注入场效应晶体管及其沟道载流子控制方法
技术领域
本发明涉及微电子技术和半导体技术。
背景技术
采用硅为半导体材料的CMOS集成电路，几十年来其发展一直遵循摩尔定律。工艺尺寸不断地按比例缩小，目前7nm工艺己达量产[1]，正在处于开发5nm[2]，甚至3nm工艺技术的阶段[3]。硅集成电路的衬底厚度日益减薄,逐渐向二维半导体方向发展。
首个采用单原子层半导体石墨烯的石墨烯晶体管(GFET)于2004年诞生[4]。由于石墨烯带隙为零，在本专利对应的中国发明专利公布之前，尚未有采用大面积单原子层石墨烯制造的石墨烯GFET被关断的报道。在本专利对应的中国发明专利的实施例中，首次实现了大面积单原子层石墨烯GFET的理想关断，其开关比达到了5*107。
单原子层石墨烯场效应晶体管(GFET)的发明给石墨烯带来了新一代半导体的希望，但是，进一步的研究表明，GFET在数字逻辑开关中的应用受到严重限制[5]。由于石墨烯的零带隙，GFET不能很好地关断。为了解决这一问题，石墨烯纳米带(GNR)的最大开/关比为1×107[6]。然而，GNR的主要问题是石墨烯的载流子迁移率较低，这是由于引入附加载流子散射的结果。传统的关断GFET的方法是先打开石墨烯的带隙[7]。还尝试了其它方法来解决这个问题，包括场效应隧道晶体管(开/关比1×105)[8]和石墨烯基真空晶体管(GVT，开/关比1×106)[9].GFET不能关断的问题被诺贝尔奖获得者，Geim爵士预言解决时间要到2025年[10]。总之，传统的石墨烯场效应晶体管(GFET)没有栅电极电流对栅极抽取/注入效应，不能通过控制栅极电流的大小使沟道半导体材料中的载流子数n成数量级减小。传统GFET开关比很低，无法实现理想关断，因而其功耗很高。
传统的Si-MOSFET也没有栅电极电流对栅极抽取/注入场效应，不能通过控制栅极电流的大小使沟道半导体材料中的载流子数n减小，因而功耗高，只能通过按比例缩小的原则，降低其功耗。
在硅MOS器件与IC方面，据报道人们已经在研究最小尺寸为3nm的FINFET[3]。由FINFET结构[11]可知：在FIN的尺寸2nm的FINFET中，单面栅极所控制的半导体沟道的尺度为1nm，约两个硅原子层。所以硅半导体正在二维化，在栅极抽取和注入场效应晶体管(GEIT)发现的规律，可以适用于未来的硅器件和IC。从摩尔定律诞生[12]开始，几十年来，硅集成电路一直遵循按比例缩小原则[13]，随着关键尺寸的进一步减小，在小于22nm以后，器件的工作电压不能按比例缩小，由此带来器件的功耗降低的效果愈来愈差[14]。
传统的MOS晶体管中，栅介质是具有绝缘体特征的介质薄膜材料，栅介质层的电阻值为无穷大，如SiO2，MOS晶体管的栅极通过栅极电容对半导体沟道的导电程度进行控制[15]。
历史上，由于数字CMOS电路工艺占统治地位，模拟集成电路工程师不得不接受愈来愈低的工作电压。然而，较低的工作电压对模拟集成电路信噪比和抗干扰能力的提高是非常不利的。
参考文献：
[1]R.Xie,et al.“A7nm FinFET technology featuring EUV patterning anddual strained high mobility channels.”IEDM,p.47,2016
[2]ED Kurniawan,et al,Effect of fin shape of tapered FinFETs on thedevice performance in 5-nm node CMOS technology,Microelectronics Reliability,Aug.2017
[3]Thirunavukkarasu V,Jhan Y R,Liu Y B,et al.Performance ofInversion,Accumulation,and Junctionless Mode n-Type and p-Type Bulk SiliconFinFETs With 3-nm Gate Length[J].IEEE Electron Device Letters,2015,36(7):645-647.
[4]Novoselov,K.S.et al."Room-temperature electric field effect andcarrier-type inversion in graphene films".Submitted to Nature on 5February2004.
[5]F.Schwierz,Graphene transistors:status,prospects,and problems[J].Peoceeding of the IEEE.2013,101:1567-1584
[6]X.Li,et al.“Chemically derived,ultrasmooth graphene nanoribbonsemiconductors.”Science,p.1229,2008
[7]G.Iannaccone,et al.,“Perspectives of graphene nanoelectronics:probing technological options with modeling.”IEDM,p246,2009
[8]L.Britnell,et al.“Field-effect tunneling transistor based onvertical graphene heterostructures.”Science,p.947,2012
[9]G.Wu,et al.“A graphene-based vacuum transistor with a high on/offcurrent ratio.”Adv.Funct.Mater.,p.5972,2015
[10].K.S.Novoselov,V.I.Fal’ko,L.Colombo,P.R.Gellert,M.G.Schwab,K.Kim,A roadmap for graphene.Nature.490,192-200(2012)
[11]Wen-Chin Lee，Kedzierski,J.，Takeuchi,H.，Asano,K.，Kuo,C.，Anderson,E.，Tsu-Jae King，Bokor,J.，Chenming Hu.FinFET-a self-aligned double-gate MOSFETscalable to 20nm：IEEE Transactions on Electron Devices，2000：2320–2325.
[12]Moore,Gordon E."Cramming more components onto integratedcircuits".Electronics.Retrieved 2016-07-01.
[13]Thompson S,Packan P,Bohr M.MOS scaling:transistor challenges forthe 21st century.Intel Technology Journal,1998；pp 1～18.
[14]Anantha P.Chandrakasan,Samuel Sheng,and Robert W.Brodersen,Low-Power Cmos digital design[J].IEEE J Sol Sta Cire.1992,27(4)
[15]Simon M·Sze,Physics of Semiconductor Devices,Second Edition，Wiley Interscience,New York，1996
发明内容
本发明所要解决的技术问题是：提供一种栅极抽取和注入场效应晶体管，实现器件和集成电路的功耗成数量级的显著降低，以及实现器件和集成电路的工作电压的提高，而器件和集成电路的功耗仍比传统的器件和集成电路的功耗低。这是因为，P＝I*V，当I能显著降低时，V可适当提高。
本发明解决所述技术问题采用的技术方案是：栅极抽取和注入场效应晶体管，在绝缘层上设置有源极、漏极、栅极和沟道半导体区，栅极与沟道半导体区之间设置有栅介质层，其特征在于，
所述栅介质层为电阻值为103～1016Ω的薄膜材料；
所述沟道半导体区的材质为二维半导体，或者具有二维半导体材料特点的三维半导体。
所述栅介质层的材质为下述薄膜材料之一，或者两种及两种以上的组合：
SIPOS、氧化铝、非晶硅、多晶硅、非晶SiC、多晶SiC、非晶GaN、多晶GaN、非晶金刚石、多晶金刚石、非晶GaAs、多晶GaAs。
氧化铝可以采用天然氧化铝。
所述沟道半导体区的材质为下述二维半导体材料之一：
石墨烯、黑磷、MoS2、MoSe2、WSe2。
所述具有二维半导体材料特点的三维半导体为：
厚度小于或等于10个原子层的下述半导体之一：硅、砷化镓、氮化镓、SiC、金刚石。
进一步的，所述沟道半导体区的材质为本征半导体，所述源极和漏极为金属电极；在器件开启时，所述沟道半导体区与金属电极之间为欧姆接触；在器件关断时,所述沟道半导体区与金属电极之间为肖特基接触。
所述沟道半导体区包括两个第一导电类型区和一个第二导电类型区，一个第一导电类型区设置于源极和第二导电类型区之间，另一个第一导电类型区设置于漏极和第二导电类型区之间；
第一导电类型区的材质为N型半导体，第二导电类型区的材质为P型半导体；或者，第一导电类型区的材质为P型半导体，第二导电类型区的材质为N型半导体；或者，第一导电类型区的材质为N型半导体，第二导电类型区的材质为N型半导体；或者，第一导电类型区的材质为P型半导体，第二导电类型区的材质为P型半导体。
或者，所述沟道半导体区包括两个第一导电类型区和一个第二导电类型区，一个第一导电类型区设置于源极和第二导电类型区之间，另一个第一导电类型区设置于漏极和第二导电类型区之间；
第一导电类型区的材质为重掺杂半导体，第二导电类型区的材质为轻掺杂半导体；或者，第一导电类型区的材质为重掺杂半导体，第二导电类型区的材质为本征半导体。
本发明还提供一种栅极抽取和注入场效应晶体管的载流子数量方法，其特征在于，包括下述步骤：
1)施加第一栅电压，完成对沟道半导体中载流子的抽取，
2)施加与第一栅电压相反极性的第二栅电压，并通过控制第二栅电压的幅度，控制注入载流子的数量，从而实现低功耗。
本发明的有益效果是：
1)器件和集成电路的功耗成数量级显著降低；由于器件工作电流Ids成数量级降低，器件工作Vds＝Vgs可不降低，仍能实现器件和电路的低功耗，由此，带来器件和电路的性噪比和抗干扰能力等模拟性能的改善；
2)对于由石墨烯这样的Eg＝0的半导体GFET，可实现小电流低功耗模拟放大；
3)因载流子数目减少，载流子间的碰撞散射减少,导致器件工作频率提高；
4)本发明的原理用于硅器件，可突破硅MOSFET必须用绝缘栅介质的传统观念，将会使得硅MOSFET器件功耗成数量级显著降低。
5)本发明可用于逻辑开关、存储器、可编程器件、小信号放大等，可十分有效的降低电路的功耗、提高电路的工作频率或开关速度。
附图说明
图1是本发明的晶体管的正常工作状态示意图，表现了在较低栅压下没有栅极抽取/注入载流子的情况。
图2是本发明的晶体管抽取载流子的工作状态示意图，表现了在较高栅压下抽取载流子的情况。
图3是本发明的晶体管抽出完载流子后的状态示意图，表现了当栅压高达一定值时载流子被栅极抽出后沟道中没有载流子的情况。
图4是本发明的晶体管注入载流子的工作状态示意图，表现了在较低负栅压下载流子从栅极被注入到沟道中的情况。
图5是本发明的晶体管注入载流子后的状态示意图，表现了当负栅压达一定值时更多的载流子从栅极被注入到沟道中的情况。
图6是本发明的制备方法第一步的示意图：在衬底上转移石墨烯或沟道半导电材料，并图形化。
图7是本发明的制备方法第二步的示意图：光刻定义源漏电极。
图8是本发明的制备方法第三步的示意图：沉积源漏金属，去除光刻胶形成源漏电极。
图9是本发明的制备方法第四步的示意图：光刻定义栅电极。
图10是本发明的制备方法第五步的示意图：在沟道材料上沉积轻微导电介质材料(沉积薄层铝自氧化后形成的介质或是其他的轻微导电介质(如半绝缘的非晶硅等))。
图11是本发明的制备方法第六步的示意图：沉积栅电极金属。
图12是本发明的制备方法第七步的示意图：去除光刻胶，完成栅极抽取/注入场效应晶体管的制备。
图13是本发明的实施例2的沟道半导体区在制备过程中的掺杂示意图：对与源漏电极接触部分的石墨烯或其他沟道半导体材料做掺杂等处理,改变石墨烯或其他沟道半导体材料与源漏电极的接触。
图14是本发明的实施例4的示意图：埋栅结构，即栅介质和栅电极在沟道半导体区的下面。
图15是本发明的晶体管在正栅压下关断的输出曲线图。
图16是本发明的晶体管在正栅压下关断后用负栅压开启的输出曲线图。
图17是本发明的晶体管获得的具有开、关特性的转移曲线图。
图18是本发明的晶体管构建的电路以及输出的同相波形和反相开关波形图。
图19是本发明的晶体管在栅电流驱动时的输出特性曲线图。
图20是60纳米硅NMOSFET在栅电流驱动时的输出特性曲线图，栅电流测试条件为0～10pA。
图21是60纳米硅NMOSFET在栅电流驱动时的输出特性曲线图，栅电流测试条件为0～18pA。
各图标号：101基底层，102绝缘层，103沟道半导体区，104、105、106定义源漏电极的光刻胶图形层，107源极金属层，108漏极金属层，109、110定义栅电极光刻胶图形层，111栅介质层，112栅极金属层，113掺杂处理的与源电极接触的半导体材料，114掺杂处理的与漏电极接触的半导体材料。
具体实施方式
栅极抽取和注入场效应晶体管，在绝缘层上设置有源极、漏极、栅极和沟道半导体区，栅极与沟道半导体区之间设置有栅介质层，
所述栅介质层为电阻值为103～1016Ω的薄膜材料；
所述沟道半导体区的材质为二维半导体，或者具有二维半导体材料特点的三维半导体。
所述栅介质层的材质为下述薄膜材料之一，或者两种，或者两种以上的组合：
SIPOS、氧化铝、非晶硅、多晶硅、非晶SiC、多晶SiC、非晶GaN、多晶GaN、非晶金刚石、多晶金刚石、非晶GaAs、多晶GaAs。
例如：非晶硅与多晶SiC的组合，
例如：非晶GaN、多晶GaN、非晶金刚石、非晶GaAs、多晶GaAs的组合。
所述沟道半导体区的材质为下述二维半导体材料之一：
石墨烯、黑磷、MoS2、MoSe2、WSe2。
所述具有二维半导体材料特点的三维半导体为：
厚度小于或等于10个原子层的下述半导体之一：硅、砷化镓、氮化镓、SiC、金刚石。
所述沟道半导体区的材质为本征半导体，所述源极和漏极为金属电极；在器件开启时，所述沟道半导体区与金属电极之间为欧姆接触；在器件关断时,所述沟道半导体区与金属电极之间为肖特基接触。
参见图1～图5。
实施例1：具有肖特基接触的实施例。
栅极抽取/注入石墨烯场效应晶体管(简称为GEIT)，在绝缘层(标记为Substrate)上设置有栅极(标记为G)、源极(标记为S)、漏极(标记为D)和单原子层石墨烯沟道半导体区，栅极与沟道半导体区之间设置有栅介质层，所述栅介质层的电阻值为109～1012Ω，所述沟道半导体区的厚度为1个原子层。所述栅介质层的介电常数为7.5。所述沟道单原子层石墨烯沟道半导体区的材质为本征半导体，所述源极和漏极为金属电极，所述沟道半导体区与金属电极之间，在器件关断时，为肖特基接触,在器件导通时，为欧姆接触。所述栅介质层的材质为氧化铝其介电常数为7.5。
图15是本发明的晶体管在正栅压下关断的输出曲线图。当栅电压比较高时，Vgs>7V，器件显示了良好的关断特性，器件关断以后漏极电流由原来的400微安变成了5.8皮安，Ids开关比达到了创纪录的5×107。有效地克服了石墨烯晶体管不能关断的缺陷。
图16是本发明的晶体管在正栅压下关断后用负栅压开启的输出曲线图。栅压从0V开始向负电压方向扫描，当栅压小于-4V时，晶体管开启。此性能说明本发明的晶体管不仅可以关断，而且可以开启。当器件关断以后，如果不施加负栅压，器件将不会开启，此性能有可能构成一种新型不挥发半导体存储器。
图17是本发明的晶体管获得的具有开、关特性的转移曲线图。这是首次发现半导体器件具有如此形状的转移曲线。从图中可以看出，在正向扫描时(-6V至+10V)当Vgs＝8.5V时Ids骤然减小，在Vgs＝9.6V时Ids几乎为零(只有8pA)，GEIT被理想关断。从紧接着的反向扫描(+10V至-6V)曲线中可以看出，在Vgs＝+10V到Vgs＝-4.5V过程中GEIT都处于关断状态，Vgs＝-5V时，Ids陡然增大，关断的GEIT又被开启了。从图中还可以发现，在BC段和DE段的跨导很大，这个现象说明器件在栅极导电的情况下，不仅可以正常工作，而且可以实现比一般GFET(与图6中FA和AB段相比较)更高的Gm增益。
图18是本发明晶体管构建的电路以及输出的同相和反相开关波形图。此性能表明本发明的晶体管可以实现开关电路。
图19是本发明的晶体管在栅电流驱动时的输出特性曲线图。图20和21是60纳米硅NMOSFET在栅电流驱动时的输出特性曲线图，栅电流测试条件分别为0～10pA和0～18pA。从图19的输出特性可以看出，本发明的晶体管在Igs＝0.5～4pA范围已能正常工作，而60nm硅NMOSFET在Igs＝8pA以下不能正常工作，其器件正常工作的栅极电流为12～18pA。石墨烯和硅器件的面积分别为，Sg(石墨烯)＝8um*4um，Sg/(硅)＝60nm*120nm。石墨烯器件的电流密度为Jgs(石墨烯)＝Igs(石墨烯)/Sg(石墨烯)＝0.125(pA/um2)。硅器件的电流密度为Jgs(硅)＝Igs(硅)/Sg(硅)＝2500(pA/um2)。可以看出石墨烯器件的电流密度远远小于硅器件。根据功耗密度公式，Pgs＝Jgs*Vgs，可得，Pgs(硅)/Pgs(石墨烯)＝5200。即，本发明晶体管的栅极驱动功耗密度比60纳米硅NMOSFET小约5200倍。
本发明(GEIT)具有栅电极通过轻微导电栅介质抽出载流子实现器件关断和注入载流子实现器件导通的特性，获得了如图17所示的马鞍形的转移曲线，而传统的GFET(石墨烯场效应晶体管)只能获得V形的转移曲线(如图17所示的FAB段)。从如图17所示的GEIT转移曲线可以得知，在CD段，GEIT的Ids为pA量级。因此，根据器件功耗P＝Ids 2R，将GEIT应用在开关电路或数字逻辑电路，从而使器件或电路的功耗显著降低。
图19示例了栅长为4um栅宽为8um的GEIT在恒定栅电流驱动下的Ids-Vds曲线，图21示例了栅长为60nm栅宽为120nm的60nm-Si-MOSFET在恒定栅电流驱动下的Ids-Vds曲线。对比图19和图21，根据公式Jgs＝Igs/Sg(Sg为栅面积)和Pgs＝Jgs*Vgs，GEIT的栅驱动功耗密度比60nm-Si-MOSFET小5200倍。
实施例2：具有PN结的实施例。
栅极抽取和注入场效应晶体管，在绝缘层上设置有栅极、源极、漏极和沟道半导体区，栅极与沟道半导体区之间设置有栅介质层，所述栅介质层的电阻值为103～1016Ω，所述沟道半导体区的厚度为1～10个原子层。所述源极和漏极为金属电极，所述沟道半导体区与金属电极之间为欧姆接触。
所述沟道半导体区5包括两个第一导电类型区和一个第二导电类型区，一个第一导电类型区设置于源极和第二导电类型区之间，另一个第一导电类型区设置于漏极和第二导电类型区之间；
第一导电类型区的材质为N型半导体，第二导电类型区的材质为P型半导体；或者，第一导电类型区的材质为P型半导体，第二导电类型区的材质为N型半导体。
所述栅介质层4的材质为为氧化铝、非晶硅、半绝缘多晶硅或其它半绝缘材料。
实施例3：具有高低结的实施例。
栅极抽取和注入场效应晶体管，在绝缘层上设置有栅极、源极、漏极和沟道半导体区，栅极与沟道半导体区之间设置有栅介质层，所述栅介质层的电阻值为103～1016Ω，所述沟道半导体区的厚度为1～10个原子层。所述源极和漏极为金属电极，所述沟道半导体区与金属电极之间为欧姆接触。
第一导电类型区的材质为轻掺杂半导体，第二导电类型区的材质为重掺杂半导体；
或者，第一导电类型区的材质为重掺杂半导体，第二导电类型区的材质为轻掺杂半导体。
实施例4：具有埋栅结构的实施例。
参见图14。
本实施例与实施例1的区别是，本实施例为埋栅结构，即栅介质和栅电极在沟道半导体区的下面。
实施例5：制备方法的实施例(肖特基接触)。
参见图6～图12。
本发明的制备方法包括下述步骤：
1)在绝缘层上形成沟道半导体材料层(例如石墨烯)103，如图6所示。
2)通过光刻胶图形104、105、106定义源漏电极，如图7所示。
3)沉积形成源极金属层107和漏极金属层108，如图8所示。
4)通过光刻胶图形109、110定义栅电极，如图9所示。
5)形成栅介质层111，如图10所示。
6)沉积栅电极金属层112，如图11所示。
7)去除光刻胶完成栅极抽取和注入场效应晶体管制备，如图12所示。
实施例6：制备方法的实施例(PN结)。
参见图6～图13。
本发明的制备方法包括下述步骤：
1)在绝缘层上形成沟道半导体材料层(例如石墨烯)103，如图6所示。
2)通过光刻胶图形104、105、106定义源漏电极，如图7所示。
3)对与源漏电极接触的沟道半导体材料作掺杂等处理,改变石墨烯或沟道半导体材料与源漏电极的接触,如图13所示。
4)沉积形成源极金属层107和漏极金属层108，如图8所示。
5)通过光刻胶图形109、110定义栅电极，如图9所示。
6)形成栅介质层111，如图10所示。
7)沉积栅电极金属层112，如图11所示。
8)去除光刻胶完成栅极抽取和注入场效应晶体管制备，如图12所示。
实施例7：开关器件。
本实施例系采用实施例1、2或3的晶体管结构形成的开关器件。通过控制栅极电流的大小使沟道半导体材料中的载流子数n成数量级减小，根据Ids＝qvnS,(q为电子电量，v为电子速度，n为电子浓度，S是电子流过的面积)和器件功耗P＝Ids 2R，进行开关电路或数字逻辑应用，从而使器件或电路的功耗显著降低。
实施例8：放大器件。
本实施例系采用实施例1、2或3的晶体管结构形成的放大器件。通过控制栅极电流的大小使沟道半导体材料中的载流子数n成数量级减小，使器件工作在较少载流子的状态，进行模拟信号放大，从而实现高增益、高速、高频和良好饱等特性。
实施例9：存储器件。
本实施例系采用实施例1、2或3的晶体管结构形成的不挥发半导体存储器。即通过对器件栅极施加足够高的正电压(或负电压)，使器件关断，此后，只要不再施加负栅压(或正电压)，器件将长时间或永久保持在Ids为零的关态，从而实现对信息的存储。
取图17中C点为存储状态，即通过施加正栅压，器件工作点由B点变到C点，此后，只要不再施加负栅压，器件将长时间或永久保持在Ids为零的关态。

Claims (5)

1.栅极抽取和注入场效应晶体管，在绝缘层上设置有源极、漏极、栅极和沟道半导体区，栅极与沟道半导体区之间设置有栅介质层，其特征在于，
所述栅介质层为电阻值为103～1016Ω的薄膜材料；
所述沟道半导体区的材质为二维半导体，或者具有二维半导体材料特点的三维半导体；
所述沟道半导体区为下述AB两种之一：
A、沟道半导体区包括两个第一导电类型区和一个第二导电类型区，一个第一导电类型区设置于源极和第二导电类型区之间，另一个第一导电类型区设置于漏极和第二导电类型区之间；第一导电类型区的材质为N型半导体，第二导电类型区的材质为P型半导体；或者，第一导电类型区的材质为P型半导体，第二导电类型区的材质为N型半导体；或者，第一导电类型区的材质为N型半导体，第二导电类型区的材质为N型半导体；或者，第一导电类型区的材质为P型半导体，第二导电类型区的材质为P型半导体；
B、沟道半导体区包括两个第一导电类型区和一个第二导电类型区，一个第一导电类型区设置于源极和第二导电类型区之间，另一个第一导电类型区设置于漏极和第二导电类型区之间；第一导电类型区的材质为重掺杂半导体，第二导电类型区的材质为轻掺杂半导体；或者，第一导电类型区的材质为重掺杂半导体，第二导电类型区的材质为本征半导体。
2.如权利要求1所述的栅极抽取和注入场效应晶体管，其特征在于，所述栅介质层的材质为下述薄膜材料之一，或者两种及两种以上的组合：
SIPOS、氧化铝、非晶硅、多晶硅、非晶SiC、多晶SiC、非晶GaN、多晶GaN、非晶金刚石、多晶金刚石、非晶GaAs、多晶GaAs。
3.如权利要求1所述的栅极抽取和注入场效应晶体管，其特征在于，所述沟道半导体区的材质为下述二维半导体材料之一：
石墨烯、黑磷、MoS2、MoSe2、WSe2。
4.如权利要求1所述的栅极抽取和注入场效应晶体管，其特征在于，所述具有二维半导体材料特点的三维半导体为：
厚度小于或等于10个原子层的下述半导体之一：硅、砷化镓、氮化镓、SiC、金刚石。
5.如权利要求1所述的栅极抽取和注入场效应晶体管，其特征在于，所述沟道半导体区的材质为本征半导体，所述源极和漏极为金属电极。
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