CN109166914B - 场阻型igbt结构及其制作方法 - Google Patents
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- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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Abstract
本发明公开的场阻型IGBT结构，包括一N漂移区域，该N漂移区域具有相对的正面结构和背面结构，所述正面结构中包含发射极和栅极，其特征在于，所述背面结构具有一层N型缓冲层和一层集电极层，所述集电极层覆盖在所述N型缓冲层上。本发明还公开了该穿通型IGBT结构的制作方法。本发明与现有技术相比，具有如下优点:(1)不再需要传统的高能离子注入和激光退火；(2)N型Ge和P型Ge的掺杂由材料工厂制作，不再需要掺杂工艺以及退火工艺；(3)掺杂浓度可以按照要求来调整；(4)N型Ge层和P型Ge层可以在同一台蒸发设备或者溅射设备里完成。
Description
技术领域
本发明涉及半导体器件制备技术领域,特别涉及场阻型IGBT结构及其制作方法。
背景技术
通常IGBT有三种结构：穿通型IGBT、非穿通型IGBT和场阻型IGBT。
参见图1，穿通型IGBT是在P型Si衬底上外延N型Si缓冲层和N-高阻层(漂移区)；这种结构的主要缺点是：1.对于高压IGBT，厚外延是非常困难且花费很高；2.由于背面P型Si衬底在器件导通时大量的空穴会注入到N-漂移区，使得器件的关断时间很长，故通常会采用电子辐射等手段来降低少子寿命，这势必进一步会增加制造成本。
参见图2，非穿通型IGBT采用FZ单晶硅片，在完成IGBT正面工艺后，硅片减薄，然后背面硼离子注入，然后退火。这种结构的主要缺点是：1.非穿通结构，漂移区厚度要比传统型的更厚，使得器件的饱和压降更高，关断时间更长；2.此结构与后面介绍的场阻型IGBT相比，静态和动态的功率损耗仍然较高。
参见图3，场阻型IGBT采用FZ单晶硅片，在完成IGBT正面工艺后，硅片减薄，然后背面高能磷离子注入和硼离子注入，然后退火。此结构的主要缺点：1.为降低背面注入效率，背面硼离子注入剂量也不会太高，带来的结果就是集电极的接触电阻会大；2.高能离子注入及背面注入之后的激光退火等制程，设备昂贵。
发明内容
本发明所要解决的技术问题之一在于针对现有场阻型IGBT结构上所存在的上述技术问题而提供一种制备工艺简单、成本低的场阻型IGBT结构。
本发明所要解决的技术问题之二在于提供上述场阻型IGBT结构的制作方法。
作为本发明第一方面的场阻型IGBT结构，包括一N漂移区域，该N漂移区域具有相对的正面结构和背面结构，所述正面结构中包含发射极和栅极，其特征在于，所述背面结构具有一层N型缓冲层和一层集电极层，所述集电极层覆盖在所述N型缓冲层上。
在本发明的一个优选实施例中，所述N型缓冲层为N型Ge层，所述集电极层为P型Ge层。
在本发明的一个优选实施例中，所述N型缓冲层用N型掺杂Ge材料蒸发或者溅射形成。
在本发明的一个优选实施例中，所述集电极采用P型掺杂Ge材料蒸发或者溅射形成。
在本发明的一个优选实施例中，所述N漂移区域采用一次或多次不同掺杂浓度的材料蒸发或者溅射形成。
作为本发明第二方面的穿通型IGBT结构的制作方法，包括如下步骤：
(1)正面结构成型步骤；
(2)减薄步骤；
(3)背面N型Ge层蒸发或者溅射步骤；
(4)背面P型Ge层蒸发或者溅射步骤。
在本发明一个优选实施例中，所述正面结构成型步骤包括如下步骤：
(1.1)P-body和N+注入推进步骤；
(1.2)Trench刻蚀步骤；
(1.3)Gate氧化和多晶硅淀积步骤；
(1.4)SiO2等介质淀积步骤；
(1.5)接触孔刻蚀步骤；
(1.6)正面金属化步骤；
(1.7)硅片正面钝化步骤。
由于采用了如上的技术方案，本发明与现有技术相比，具有如下优点:
(1)不再需要传统的高能离子注入和激光退火；
(2)N型Ge和P型Ge的掺杂由材料工厂制作，不再需要掺杂工艺以及退火工艺；
(3)掺杂浓度可以按照要求来调整；
(4)N型Ge层和P型Ge层可以在同一台蒸发设备或者溅射设备里完成。
附图说明
图1为现有穿通型IGBT的结构示意图。
图2为现有非穿通型IGBT的结构示意图。
图3为场阻型IGBT的结构示意图。
图4为本发明场阻型IGBT的结构示意图。
图5为本发明正面结构成型步骤地状态示意图。
图6为本发明减薄后的状态示意图。
图7为本发明背面N型Ge层蒸发或者溅射的示意图。
图8为本发明背面P型Ge层蒸发或者溅射的示意图。
具体实施方式
以下结合附图和具体实施方式来进一步描述本发明
参见图4，图中所示的场阻型IGBT结构，包括一N漂移区域10，该N漂移区域具有相对的正面结构20和背面结构，正面结构20中包含发射极和栅极，背面结构具有一层N型缓冲层31和一层集电极层32，集电极层32覆盖在N型缓冲层31上。
N型缓冲层31为N型Ge层，N型缓冲层用N型掺杂Ge材料蒸发或者溅射形成。集电极层32为P型Ge层。集电极采用P型掺杂Ge材料蒸发或者溅射形成。
N漂移区域10采用一次或多次不同掺杂浓度的材料蒸发或者溅射形成。
上述穿通型IGBT结构的制作方法，包括如下步骤：
(1)正面结构成型步骤，该步骤形成图5所示结构，具体如下：
(1.1)P-body和N+注入推进步骤；
(1.2)Trench刻蚀步骤；
(1.3)Gate氧化和多晶硅淀积步骤；
(1.4)SiO2等介质淀积步骤；
(1.5)接触孔刻蚀步骤；
(1.6)正面金属化步骤；
(1.7)硅片正面钝化步骤。
(2)减薄步骤，该步骤形成图6所示的结构
(3)背面N型Ge层蒸发或者溅射步骤，该步骤形成图7所示结构。
(4)背面P型Ge层蒸发或者溅射步骤。该步骤形成图8所示结构。
Claims (1)
1.场阻型IGBT结构的制作方法，其特征在于，该场阻型IGBT结构具有N漂移区域，所述N漂移区域具有相对的正面结构和背面结构，包括如下步骤：
(1)正面结构成型步骤；
(2)减薄步骤；
(3)背面用蒸发或者溅射的方法覆盖一N型Ge层或者N型Si层，以在背面形成一N型缓冲层，所述N型缓冲层为N型Ge层或者N型Si层，用N型掺杂Ge材料或者N型掺杂Si材料蒸发或者溅射形成；
(4)背面用蒸发或者溅射的方法覆盖一P型Ge层或者P型Si层，以在所述N型缓冲层上形成一集电极层，所述集电层为P型Ge层或者P型Si层，用P型掺杂Ge材料或者P型掺杂Si材料蒸发或者溅射形成；
所述正面结构成型步骤包括如下步骤：
(1.1)P-body和N+注入推进步骤；
(1.2)Trench刻蚀步骤；
(1.3)Gate氧化和多晶硅淀积步骤；
(1.4)SiO2介质淀积步骤；
(1.5)接触孔刻蚀步骤；
(1.6)正面金属化步骤；
(1.7)硅片正面钝化步骤。
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101908485A (zh) * | 2010-06-11 | 2010-12-08 | 上海宏力半导体制造有限公司 | 利用三块掩模板制作垂直双极性晶体管的方法 |
| US20120049902A1 (en) * | 2010-08-30 | 2012-03-01 | Stmicroelectronics S.R.L. | Integrated electronic device and method for manufacturing thereof |
| CN103943671A (zh) * | 2013-01-23 | 2014-07-23 | 中国科学院微电子研究所 | 一种功率半导体器件及其形成方法 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101908485A (zh) * | 2010-06-11 | 2010-12-08 | 上海宏力半导体制造有限公司 | 利用三块掩模板制作垂直双极性晶体管的方法 |
| US20120049902A1 (en) * | 2010-08-30 | 2012-03-01 | Stmicroelectronics S.R.L. | Integrated electronic device and method for manufacturing thereof |
| CN103943671A (zh) * | 2013-01-23 | 2014-07-23 | 中国科学院微电子研究所 | 一种功率半导体器件及其形成方法 |
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