CN109155635A

CN109155635A - A kind of method, transmitting terminal and the receiving end of signal transmission

Info

Publication number: CN109155635A
Application number: CN201680085716.3A
Authority: CN
Inventors: 马亮; 魏岳军
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2016-06-14
Filing date: 2016-06-14
Publication date: 2019-01-04
Also published as: WO2017214851A1

Abstract

The present embodiments relate to method, transmitting terminal and the receiving ends of a kind of transmission of signal, which comprises carries out low density parity check code LDPC to information sequence according to the code rate of the second code word and the second matrix and encodes to obtain the second code word；Second code word is sent to receiving end；Wherein, after the corresponding mother matrix of information sequence is is carried out row union operation at least once by the second matrix, and delete what an at least column check bit obtained.In the present invention, carrying out punching to the corresponding check matrix of LDPC code can be improved transmission code word code rate, when punching causes performance decline more, carries out row union operation, deletes a part of check bit to obtain high code rate.Alternatively, by the corresponding check matrix of LDPC code is extended and line splitting operation increase check bit code word, to realize reduction code rate.By the above method, the code rate of low density parity check code can be flexibly adjusted, constructs the LDPC code of rate flexibility and changeability in a big way.

Description

Signal transmission method, transmitting terminal and receiving terminal

Technical Field

The embodiment of the invention relates to the technical field of mobile communication, in particular to a signal transmission method, a transmitting end and a receiving end.

Background

The channel coding requirement of the wireless network has flexible and variable code rate so as to meet the requirement of realizing Hybrid Automatic Repeat request (HARQ for short). Rate matching of Low density parity check codes (LDPC) is generally achieved by puncturing (puncturing) and expanding (extended) methods. Both the two methods need to construct a mother matrix of a code word before implementation, and a series of high-code-rate codes are obtained by punching and removing bits in part of mother code words in the sending process; and expanding, namely constructing a code word with a lower code rate from the high-code-rate mother code by adding more parity check equations. Generally, puncturing and spreading are required to support a wide range of rate matching requirements, respectively, on the basis of the mother matrix. The method is widely applied to the fields of microwave, optical network, WiFi and the like. However, in the prior art, research on Rate compatible Low density parity check codes (RC-LDPC codes for short) is not mature, and the performance of LDPC codes applied by simple methods such as random puncturing and direct expansion is poor, so how to construct an LDPC code with a flexible and variable Rate in a large range is an urgent technical problem to be solved.

Disclosure of Invention

The embodiment of the invention provides a signal transmission method, a transmitting end and a receiving end, wherein the transmitting end respectively carries out corresponding deformation processing on a check matrix corresponding to an LDPC code according to the requirement of the receiving end, and the deformation processing comprises row merging operation and punching operation; or performing line splitting operation, expanding operation and the like. And then coding is carried out according to the processed check matrix and the information sequence sent by the information source, and a code word is generated and then sent to a receiving end for decoding. When the performance is reduced more due to punching, the row merging operation is carried out, and high code rate can be obtained. Or, the code word of the check bit is added by carrying out expansion and row splitting operation on the check matrix, so that the code rate can be reduced. By the method, the code rate of the low-density parity check code can be flexibly adjusted, and the LDPC code with flexible and variable rate is constructed in a larger range. Meanwhile, the receiving end can decode the LDPC code more conveniently.

In a first aspect, the present invention provides a method for signal transmission, the method comprising: performing low-density parity check (LDPC) coding on the information sequence according to the code rate of the second code word and the second matrix to obtain a second code word; sending the second code word to a receiving end; and the second matrix is obtained by performing at least one row merging operation on the mother matrix corresponding to the information sequence and deleting at least one column of check bits.

With reference to the first aspect, in a first possible implementation manner of the first aspect, the method further includes: receiving a negative response of a receiving end to the second code word decoding; if the code rate of the third code word is greater than the code rate of the mother matrix corresponding to the information sequence, obtaining the third code word according to the code rate of the third code word and the third matrix; sending the third code word to a receiving end; wherein the code rate of the third codeword is less than or equal to the code rate of the second codeword; the third matrix is obtained by performing at least one expansion and at least one row splitting operation on the second matrix.

With reference to the first aspect, in a second possible implementation manner of the first aspect, a negative acknowledgement of the receiving end to decode the second codeword is received; if the code rate of the third code word is less than or equal to the code rate of the mother matrix corresponding to the information sequence, obtaining the third code word according to the mother matrix corresponding to the information sequence; and sending the third code word to a receiving end.

With reference to any one of the first aspect to the second possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, the second matrix is specifically: performing at least one row merging operation on all row elements of a mother matrix corresponding to the information sequence to obtain a fourth matrix, wherein the fourth matrix comprises information bits and check bits; and deleting at least one row of check bits in all rows of check bits in the fourth matrix, wherein the total row number of the check bits of the fourth matrix is greater than or equal to two, and all elements of the deleted at least one row of check bits are less than zero.

In a second aspect, an embodiment of the present invention provides another signal transmission method, where the method includes: receiving a second codeword; performing Low Density Parity Check (LDPC) decoding on the second code word according to the second matrix to obtain an information sequence; and the second matrix is obtained by performing at least one row merging operation on the mother matrix corresponding to the information sequence and deleting at least one column of check bits.

With reference to the second aspect, in a first possible implementation manner of the second aspect, if LDPC decoding fails on the second codeword according to the second matrix, a negative response of the decoding failure of the second codeword is sent to the transmitting end; receiving a third codeword; if the code rate of the third code word is greater than the code rate of the corresponding mother matrix of the information sequence, determining a third matrix according to the code rate of the third code word and the second matrix; performing LDPC decoding on the third codeword according to the third matrix; wherein the code rate of the third codeword is less than or equal to the code rate of the second codeword; the third matrix is obtained by performing at least one expansion and at least one row splitting operation on the second matrix.

With reference to the second aspect, in a second possible implementation manner of the second aspect, if LDPC decoding fails on the second codeword according to the second matrix, a negative response of the decoding failure of the second codeword is sent to the transmitting end; receiving a third codeword; and if the code rate of the third code word is less than or equal to the code rate of the mother matrix corresponding to the information sequence, performing LDPC decoding on the third code word according to the mother matrix corresponding to the information sequence.

With reference to any one of the second possible implementation manners of the second aspect to the second aspect, in a third possible implementation manner of the second aspect, the second matrix is specifically: performing at least one row merging operation on all row elements of a mother matrix corresponding to the information sequence to obtain a fourth matrix, wherein the fourth matrix comprises information bits and check bits; and deleting at least one row of check bits in all rows of check bits in the fourth matrix, wherein the total row number of the check bits of the fourth matrix is greater than or equal to two, and all elements of the deleted at least one row of check bits are less than zero.

In a third aspect, an embodiment of the present invention provides a transmitting end, where the transmitting end includes: the coding unit is used for carrying out low-density parity check (LDPC) coding on the information sequence according to the code rate of the second code word and the second matrix to obtain the second code word; the processing unit is used for performing at least one row merging operation on the mother matrix corresponding to the information sequence, deleting at least one column of check bits and acquiring a second matrix; and the sending unit is used for sending the second code word to the receiving end.

With reference to the third aspect, in a first possible implementation manner of the third aspect, the transmitting end further includes: a receiving unit, configured to receive a negative acknowledgement of decoding the second codeword by a receiving end;

the encoding unit is further configured to, when it is determined that the code rate of the third codeword is greater than the code rate of the mother matrix corresponding to the information sequence, obtain the third codeword according to the code rate of the third codeword and the third matrix; the sending unit is further used for sending the third code word to the receiving end;

wherein the code rate of the third codeword is less than or equal to the code rate of the second codeword; the third matrix is obtained by the processing unit performing at least one expansion and at least one row splitting operation on the second matrix.

With reference to the third aspect, in a second possible implementation manner of the third aspect, the transmitting end further includes: a receiving unit, configured to receive a negative acknowledgement of decoding the second codeword by the receiving end; the coding unit is further used for obtaining a third code word according to the mother matrix corresponding to the information sequence when the code rate of the third code word is determined to be smaller than or equal to the code rate of the mother matrix corresponding to the information sequence; the sending unit is further configured to send the third codeword to the receiving end.

With reference to any one of the third aspect to the second possible implementation manner of the third aspect, in a third possible implementation manner of the third aspect, the processing unit is specifically configured to: performing at least one row merging operation on all row elements of a mother matrix corresponding to the information sequence to obtain a fourth matrix, wherein the fourth matrix comprises information bits and check bits; and deleting at least one row of check bits in all rows of check bits in the fourth matrix, wherein the total row number of the check bits of the fourth matrix is greater than or equal to two, and all elements of the deleted at least one row of check bits are less than zero.

In a fourth aspect, an embodiment of the present invention provides a receiving end, where the receiving end includes: a receiving unit, configured to receive a second codeword; the processing unit is used for carrying out at least one row merging operation on the mother matrix corresponding to the information sequence, deleting at least one column of check bits and acquiring a second matrix; and the decoding unit is used for carrying out low-density parity check (LDPC) decoding on the second code word according to the second matrix to obtain an information sequence.

With reference to the fourth aspect, in a first possible implementation manner of the fourth aspect, the receiving end further includes:

a transmission unit: the negative response is used for sending the decoding failure of the second code word to the transmitting terminal when the decoding unit fails to perform LDPC decoding on the second code word according to the second matrix; the receiving unit is further configured to receive a third codeword; the decoding unit is further configured to perform LDPC decoding on the third codeword according to the third matrix when the code rate of the third codeword is greater than the code rate of the corresponding mother matrix of the information sequence; wherein the code rate of the third codeword is less than or equal to the code rate of the second codeword; the third matrix is obtained by the processing unit performing at least one expansion and at least one row splitting operation on the second matrix.

With reference to the fourth aspect, in a second possible implementation manner of the fourth aspect, the receiving end further includes: the sending unit is used for sending a negative response of the second code word decoding failure to the transmitting terminal when the decoding unit fails to perform LDPC decoding on the second code word according to the second matrix; the receiving unit is further configured to receive a third codeword; and the decoding unit is also used for performing LDPC decoding on the third code word according to the mother matrix corresponding to the information sequence when the code rate of the third code word is less than or equal to the code rate of the mother matrix corresponding to the information sequence.

With reference to any one of the second possible implementation manners of the fourth aspect to the fourth aspect, in a third possible implementation manner of the fourth aspect, the processing unit is specifically configured to perform at least one row merging operation on all row elements of a mother matrix corresponding to the information sequence to obtain a fourth matrix, where the fourth matrix includes information bits and check bits; and deleting at least one row of check bits in all rows of check bits in the fourth matrix, wherein the total row number of the check bits of the fourth matrix is greater than or equal to two, and all elements of the deleted at least one row of check bits are less than zero.

Based on the above technical solution, in the method for signal transmission provided in the embodiments of the present invention, the code rate of the transmitted codeword can be improved by puncturing the check matrix corresponding to the LDPC code, and when the performance is reduced more due to puncturing, row merging operation is performed, and a part of check bits is deleted to obtain a high code rate. Or, the code words of the check bits are added by performing expansion and row splitting operation on the check matrix corresponding to the LDPC code, thereby realizing the reduction of the code rate. By the method, the code rate of the low-density parity check code can be flexibly adjusted, and the LDPC code with flexible and variable rate is constructed in a larger range.

Drawings

Fig. 1 is a schematic flowchart 100 of a signal transmission method according to an embodiment of the present invention;

fig. 2 is a block diagram of a structure for expanding a mother matrix downward according to an embodiment of the present invention;

fig. 3 is a flowchart 300 of another signal transmission method according to a second embodiment of the present invention;

FIG. 4 is a flow chart diagram 400 of a method of LDPC code encoding;

FIG. 5 is a flow chart 500 of a decoding method of LDPC codes;

FIG. 6 is a diagram illustrating a comparison of simulation results of a plurality of parity check code rate matching methods according to an embodiment;

fig. 7 is a schematic structural diagram 700 of a signal transmission apparatus according to a third embodiment of the present invention;

fig. 8 is a schematic structural diagram 800 of another signal transmission apparatus according to a fourth embodiment of the present invention;

fig. 9 is a schematic structural diagram 900 of a signal transmission system according to a fifth embodiment of the present invention;

fig. 10 is a schematic structural diagram 1000 of a transmitting end according to a sixth embodiment of the present invention;

fig. 11 is a schematic structural diagram 1100 of a receiving end according to a seventh embodiment of the present invention.

Detailed Description

The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.

In the embodiment of the present application, it should be noted that the transmitting end and the receiving end may be a base station, a terminal, and other network devices that need to perform data transmission in a wireless transmission manner, respectively. For example, when the transmitting end is a base station, the corresponding receiving end is a terminal; on the contrary, when the transmitting end is a terminal, the receiving end is a base station. It is mainly distinguished whether the transmitting end is a base station or a terminal, depending on whether the data transmission is an uplink transmission or a downlink transmission. In the case of uplink transmission, the transmitting end is the terminal, and the corresponding receiving end is the base station. On the contrary, if it is downlink, the transmitting end is the base station and the receiving end is the terminal. In the following embodiments, data transmission via downlink is only used as an example for explanation, that is, in the embodiments, the transmitting end refers to a base station, and the receiving end refers to a terminal. Since the technology related to the present invention is similar in uplink and downlink embodiments, it will not be described in detail.

In the prior art, when the LDPC code realizes high-rate matching, one scheme adopted is to perform random puncturing on a mother matrix. For the LDPC code with the dual diagonal structure, in this embodiment, the check bits of the codeword are divided into 1 iteration recoverable codeword and 2 iteration recoverable codewords according to the recovery sequence of information in the decoding iteration process until k iteration recoverable codewords, and according to the actually required number of punches, the successive punches are started from a column with a smaller k value. In the decoding process, all the information of the punched 1-time iteration recoverable code words can be recovered after one iteration, and similarly, the information of the k-time iteration recoverable code words can be recovered by k iterations.

The puncturing refers to that in the wireless transmission process, the sending end selects the code words of partial check bits in the encoded code words not to be sent, and the receiving end sets the channel confidence corresponding to the code words not to be sent to be 0 when decoding.

For example: a mother matrix of LDPC codes is:

the composition of the matrix is briefly introduced first: the matrix is a 16 x 8 matrix with a spreading factor z₀The spreading factor means that each element in the matrix represents a square matrix, and when the spreading factor is 12, the square matrix is a 12 × 12 square matrix. Matrix H_cThe elements in (a) may include-1, 0, and positive integers greater than 0. Wherein, when the element is-1, the representative square matrix is a 12 × 12 all-0 matrix. When the element is 0, the representative square matrix is a 12 × 12 identity matrix. When the element is a positive integer greater than 1, the square matrix is obtained by cyclic shifting a 12 × 12 identity matrix. For example, if the element in the matrix is 49, it means that each element in a 12 × 12 identity matrix needs to be cyclically shifted by 49 bits, and finally the obtained square matrix is obtained. Since the spreading factor is 12, which means that an identity matrix will return to the original position of the element after being shifted by 12 bits, for 49 bits in the loop, the remainder can be divided by 49 by 12, and then the remainder is used as the number of bits for calculating the actual shift of the element. That is, when the matrix element is 49, it is sufficient to only cyclically shift each element in the square matrix. Of course, the remainder obtaining to obtain the final number of cyclic shifts is only a specific implementation method in this embodiment, and the number of final cyclic shifts may also be obtained by other methods, which is not limited herein. And the code rate of the matrix is 1/2. I.e. 8 columns of information bits and 8 columns of check bits. The ratio of the number of columns occupied by the information bits to the total number of columns is the code rate.

During puncturing, for example, in 8 columns of the matrix corresponding to the parity bit part, a puncturing scheme is executed from the second column, and every other column is punctured, so that only one zero element in each row participates in puncturing (because other elements in a row are all-1, that is, an all-zero matrix), so that in the decoding process, only one iteration is needed, one punctured zero element in each row is recovered, the information of the parity bit is obtained, and decoding is realized. Thus, such punctured points are divided into 1 iteration recoverable codeword. When two zero elements in each row are punctured, the punctured points are divided into 2 iterative recoverable code words, namely, in the decoding process, iteration is needed twice to realize decoding. And for K times of iteration recoverable code words, the code words need to be iterated for K times to realize a decoding process.

It can be seen that this scheme has good performance in the range of 1-iteration recoverable code word, but when the number of puncturing is large, the method has a large performance deterioration when 2-iteration recoverable code word or higher order puncturing must be started. Moreover, when the current code rate of the mother matrix is low, in order to realize high code rate, the check bit is punched for multiple times. The punctured parity bits will participate in each iteration calculation without providing any information, and thus the complexity in the decoding process is relatively high.

However, if the code rate of a mother matrix is very high and a low code rate needs to be achieved, the mother matrix is mainly extended in the prior art, but the performance of a codeword waterfall region (a region where the bit error rate decreases rapidly) can be improved (specifically, a curve portion marked in fig. 6) by using an extension algorithm alone, but a wrong platform region (a region where the bit error rate decreases slowly after the waterfall region, such as a curve portion marked in fig. 6, where positions of the codeword waterfall region and the wrong platform region are only roughly marked on one curve in fig. 6, and other curves are similar) may be deteriorated.

In order to solve the above technical problem, the present invention provides a signal transmission method. In the present invention, in order to avoid the above problems, the encoding process before the transmitting end sends the code word and the decoding process of the receiving end are already processed correspondingly. Firstly, selecting a code rate for coding the LDPC code according to channel conditions, and when a check matrix corresponding to the LDPC code to be transmitted is processed, respectively executing punching and row merging operations on the check matrix corresponding to the LDPC code to obtain a high code rate; the low code rate can also be obtained by performing row splitting operation and extension operation on a check matrix, wherein the check matrix comprises an initial mother matrix of the LDPC code and a matrix after corresponding processing. In the decoding process, firstly, the code word with the highest code rate is received, if the receiving end fails to perform decoding operation according to the code word with the highest code rate, a negative response of decoding failure can be sent to the transmitting end, so that the transmitting end can send the code word with low code rate to the receiving end according to the negative response of decoding failure. Of course, the high code rate and the low code rate are both referred to herein as the code rate of the codeword previously transmitted by the transmitting end. Correspondingly, the embodiment of the invention comprises two signal transmission methods, and the specific method steps are as follows. .

First, a signal transmission method is introduced below, where the method is mainly applied to a transmitting end, specifically as shown in fig. 1, fig. 1 is a schematic flow chart 100 of a signal transmission method provided in an embodiment of the present invention, and the method includes:

and step 110, performing LDPC coding on the information sequence according to the code rate of the second code word and the second matrix to obtain a second code word.

Specifically, the obtaining of the code rate of the second codeword is that the receiving end (in this embodiment, referred to as a terminal device) selects a suitable code length and a suitable code rate according to the channel estimation information, and sends parameters such as the corresponding code length and the corresponding code rate to the transmitting end (in this embodiment, referred to as a base station) through the signal transmission control signaling. Of course, the code rate is the second code rate. And the base station firstly obtains the code length and the code rate through the signal transmission control signaling, and deletes at least one column of check bits after carrying out at least one row merging operation on a preset LDPC code mother matrix according to the difference of the code length and the code rate to obtain a second matrix. And then obtaining a second code word according to the second matrix and the code rate of the second code word.

It should be noted that the mother matrix of the LDPC code is also the check matrix with the lowest code rate corresponding to the information sequence. At a transmitting end, an information sequence is first encoded, wherein the information sequence is information source bits which are received by the transmitting end and transmitted by an information source.

The mother matrix is predetermined between the base station and the terminal device, that is, in the base station and the terminal device, there is a mother matrix with m rows and n columns. A mother matrix may include m rows and n-m columns of information bits and m rows and m columns of check bits. The code rate is calculated as the ratio of the number of columns of information bits of a mother matrix to the total number of columns of the mother matrix.

For example, the LDPC code is a mother matrix H (m, n) of a Quasi-cyclic LDPC code (QC-LDPC code) with a dual diagonal structure, the spreading factor is z, and the code rate can be expressed by formula 1-1:

let Ri denote the ith row of the mother matrix and Ci denote the ith column of the mother matrix. d (ci) indicates the column weight of the ith column (after the check matrix is expanded, the number of non-zero elements in each row is referred to as row weight, and the number of non-zero elements in each column is referred to as column weight). Wherein the first column C in the check bits of the matrix H_n-mColumn weight d (C) of_n-m) 3, the other check bits form a set Cset₀＝{C_n-m+1,C_n-m+2,┈┈C_nIn any column C of the set_iColumn weight d (C) of_i) Where n and m are both positive integers, and n is greater than or equal to m, and i is a positive integer greater than or equal to n-m and less than or equal to n.

The process of specifically acquiring the second matrix is as follows:

and 110a, performing at least one row combination operation on all row elements of the mother matrix corresponding to the information sequence to obtain a fourth matrix.

In particular, the mother matrix includes m rows and n columns of elements. When row merging is performed, the elements in m rows may be divided into multiple groups, each group including at least two rows of elements. When the row combination is carried out, the modulo-2 addition operation is carried out on the elements of at least two rows in a one-to-one correspondence mode. And then acquiring a corresponding fourth matrix, wherein the fourth matrix is i rows and n columns, and i is a positive integer smaller than m.

In a special case, the m-row elements may be directly subjected to a row merging operation, that is, all row elements are subjected to modulo-2 addition in a one-to-one correspondence manner, so as to obtain the fourth matrix. Wherein, the fourth matrix is 1 row and n columns.

It should be noted that each row element in the mother matrix of m rows and n columns only participates in one row merging operation, but cannot participate in multiple operations. The modulo-2 addition is only a specific method in this embodiment, and other methods are not limited in this embodiment. Likewise, the acquired fourth matrix includes information bits and check bits.

And 110b, deleting at least one row of check bits in all rows of the fourth matrix to obtain the second matrix.

Specifically, a fourth matrix is obtained after row merging operation, and the fourth matrix may include information bits in i rows and m columns and check bits in i rows and n-m columns. There may be at least one column of elements in the check bits that are all less than zero. As can be seen from the above, the element less than zero represents an all-zero sub-matrix. A column of such elements may be deleted to obtain the second matrix.

Optionally, before step 110a, the method may further include: step 110 c:

and punching at least one column in m rows and m columns of check bits of the mother matrix.

Wherein, the check bits of at least one row of the punched holes are not adjacent to each other pairwise. In other words, the selected punctured columns are separated by at least one column in the m columns of check bits. Of course, in order to maximize the number of punctures in the mother matrix, two columns to be punctured are generally separated by only one column.

Specifically, the punctured columns first select the set Cset described above₀The set Cset is combined as required₀One or more rows of the holes are punched. In the puncturing process, in order to avoid the code words which can be recovered by more than 2 iterations, the number of punctured columns is maximized. Thus, in this embodiment, a principle may be followed that all columns of perforations are not adjacent. I.e. for arbitrarily punctured columns C_iAnd C_jAll belong to the set Cset₀And, j-i ≠ 1. In this way, when the puncturing condition is satisfied in the matrix H, the maximum number of punctured columns is denoted as H, and H is m/2. This is because a matrix comprises n columns and the informationThe number of columns of bits is n-m columns, so the number of columns of parity bits is m columns, and puncturing is performed every other column, so the number of columns punctured at most is m/2 columns.

The puncturing itself is a method for increasing the code rate. However, under certain conditions, the simple puncturing method may not meet the actual requirements, and may also result in performance degradation. Therefore, if the required code rate is high and even if all columns satisfying the condition are punctured, the requirement of the required high code rate is still not satisfied, the punctured matrixes are combined to obtain a new matrix, and then the new matrix is punctured to obtain a higher code rate and reduce the decoding complexity by the steps described below.

Further, the mother matrix of the m rows and n columns of the low density parity check code described above may be a matrix with a dual diagonal structure, or other forms of matrices. And are not intended to be limiting.

When the mother matrix of the constructed m rows and n columns of the low density parity check code is a matrix of a dual diagonal structure,

specifically, after the punctured columns are punctured according to the principle described in step 110c, performing at least one row merging operation on the mother matrices of m rows and n columns to obtain the mother matrices corresponding to the information sequences of i rows and n columns may specifically include:

suppose that the number of required punctures is i_nColumn, and i_nLarger than h in step 110c, the number of the holes in step 110c is determined to be h, which means that the number of the holes needed to be punched is f ═ i_n-h columns.

Because the parity bits of at least one column to be punctured have been determined in step 110c, the row in which the two zero elements included in each of the parity bits of the at least one column to be punctured are located can be determined. And respectively carrying out row merging operation on the rows where the two zero elements contained in each row of check bits are located to obtain a fourth matrix of i rows and n columns.

Then, the second matrix is obtained according to the deleting of the parity bits with at least one column of elements smaller than zero in the fourth matrix in the step 110 b.Puncturing is performed in the second matrix according to the method described in step 110c so that the number of punctures is f columns. Until the number of columns i to be punched is satisfied_n. Thus, the number of columns in the second matrix H' is n-i_n. The code rate is the same, and the code rate is greatly improved.

If the right side of the fourth matrix is a dual diagonal structure, the right side of the second matrix obtained by combining in the step 110a and deleting at least one row of check bits in the step 110b is still the dual diagonal structure, and if the number of the punctured bits does not meet the requirement, the steps can be repeatedly executed on the second matrix under the condition that the situation allows. Until the code rate of the finally obtained check matrix meets the required position.

In one specific example, the mother matrix H (8,16) of an LDPC code, for example, is represented by equations 1-2:

the matrix is a matrix with a dual diagonal structure, the spreading factor is 12, and the code rate is 1/2. And the actually required code rate is 4/5. To ensure a code rate of 4/5, therefore, the column i to be punctured can be calculated_n6. According to the puncturing rule described in step 110C, the punctured column can be determined as C₁₀、C₁₂、C₁₄、C₁₆And 4 columns are waited. Thus, the number of columns to be punched is also 2.

Therefore, the following steps need to be performed:

specifically, for C respectively₁₀、C₁₂、C₁₄、C₁₆The row in which the elements greater than or equal to zero are present is row merged, including, for column C₁₀The two rows in which the elements greater than or equal to zero are present are the first row and the second row. Therefore, the first and second rows are row merged. And C₁₂The two rows in which there are elements greater than or equal to zero are the third and fourth rows. Therefore, the third and fourth rows are row-merged. And by parity of reasoning, respectively carrying out row combination on the fifth row and the sixth row, and carrying out row combination on the seventh row and the eighth row. The matrix obtained after row merging is:

after the row merge operation is performed, it can be seen that C₁₀、C₁₂、C₁₄、C₁₆The medium elements all become-1 elements of the all-zero matrix and so these columns can be deleted. The new matrix is obtained as follows:

in the acquired new matrix, the columns to be punctured in H' are re-determined according to the puncturing rule of step 140, for example, C in the new matrix H₁₀And C₁₂. After puncturing, the code rate then becomes:

thus, the code rate is changed from 1/2 to 4/5 which is needed.

The low-density parity check code with high code rate is obtained by combining the punching and row merging algorithms, the code rate is ensured to be improved, meanwhile, the check matrix becomes smaller, the complexity of coding and decoding is reduced, and the convergence speed of iterative decoding is increased.

It should be noted that, in the embodiment of the present invention, the check matrix H of the low density parity check code is a quasi-cyclic LDPC code check matrix with a dual-diagonal structure, and therefore, the process of obtaining the high code rate is as described above. The invention is not only directed to the check matrix corresponding to the quasi-cyclic LDPC code with the dual diagonal structure. The check matrix may be a double diagonal check matrix of any configuration, and the code rate is not converted from 1/2 to 4/5 as exemplified in the present embodiment.

And step 120, sending the second code word to a receiving end.

Specifically, the LDPC code to be transmitted may be composed of a retransmission bit segment and an initial transmission bit segment. In the first transmission of an LDPC code, the base station will typically first transmit only the initial codeword, referred to herein as the second codeword.

In addition, when the base station sends the LDPC code to be transmitted to the terminal device, the information bit length and the total code length of the second matrix, whether the mother matrix is subjected to the operation processing, a specific implementation manner of the operation processing, and the like may also be sent.

After receiving the second codeword transmitted this time, the terminal device sends a negative response to the base station for decoding the second codeword if the decoding fails during the decoding process. At this time, when receiving a negative acknowledgement of decoding the second codeword sent by the terminal device, the base station transmits a retransmission bit segment, where the retransmission bit segment may be composed of at least one retransmission sub-bit segment. The retransmission bit segment is the code word corresponding to the deleted column when the mother matrix is sequentially processed in step 110. And the last deleted codeword will be sent to the terminal device first. And the code rate of the retransmitted code word is greater than that of the first code word and is less than or equal to that of the second code word.

For example, the retransmitted codeword is a third codeword, and the third codeword is obtained according to the code rate of the third codeword and a third matrix. The third matrix is obtained by performing at least one expansion and at least one row splitting operation according to the second matrix.

In order to describe how to perform at least one expansion and at least one row splitting operation on a matrix more simply and conveniently, for the convenience of the reader to understand, in this embodiment, at least one expansion and at least one row splitting operation on the mother matrix of the LDPC code described in step 110 are taken as an example for description:

and performing at least one expansion and at least one row splitting operation on the mother matrix of the m rows and the n columns to obtain a third matrix.

Specifically, in the process of performing at least one expansion and at least one row split operation on the mother matrix of the m rows and n columns of the low density parity check code, the expansion operation is performed first or the row split operation is performed first, which is not limited in this application.

Therefore, the process that can be performed may include two ways, in the first way, the mother matrix of the low density parity check code of m rows and n columns is expanded at least once to obtain the fifth matrix of h rows and j columns, where h and j are both positive integers, and h is greater than m, j is greater than n, and h-m is equal to j-n, i.e. the number of rows and columns of expansion is equal.

Specifically, the matrix is expanded on the basis of the mother matrix. In order to facilitate quick coding, a lower triangle or an approximate lower triangle structure can be adopted; the upper right of the extended check matrix adopts a full 0 structure, so that the check bits with higher code rate are nested in the check bits with lower code rate; the matrix at the lower left part can be calculated by a density evolution theory to obtain column redistribution, and values of elements in the matrix and specific positions of element distribution are constructed by a PEG algorithm. The lower right portion may be padded with a unit array. The whole expansion matrix obtained in the way meets the structure of a lower triangle, column transformation is not needed in the process of obtaining a generating matrix by a Gaussian elimination method, and the expansion row does not influence the original matrix structure.

A specific schematic diagram of downward expansion is shown in fig. 2, and fig. 2 is a structural block diagram of matrix expansion performed twice. Wherein the number of rows and columns of each expansion is equal. For example, at the first expansion, the expansion is Δ₁Rows, then the number of columns expanded is likewise Δ₁Columns, i.e. expanded matrix, m + delta₁Line, n + Δ₁And (4) columns. Similarly, in the second expansion, if the number of rows expanded is Δ₂Rows, then the extended column count would likewise be Δ₂And (4) columns. The final acquired matrix is then m + Δ₁+Δ₂Line, n + Δ₁+Δ₂And (4) columns.

The disadvantages exhibited by the matrix after spreading have been described above, and in order to realize rate matching with low code rate, the disadvantages of the matrix should be avoided. Therefore, the step of splitting the line needs to be performed as follows:

performing at least one row splitting operation on a second matrix of h rows and j columns to obtain h_fLine j_fAnd a mother matrix corresponding to the information sequence of the column, wherein f is the number of times of performing row splitting on the fifth matrix, and f is a positive integer greater than or equal to 1.

The row splitting algorithm is actually an inverse operation of the row merging algorithm in the first embodiment.

The specific algorithm is as follows: and splitting elements in the same row in the mother matrix into two rows, and adding the same check bit to the two rows.

Specifically, when the line splitting is performed, only one line may be split at a time, or a plurality of lines may be split. Whenever a row is split, a corresponding column of check bits with an element of-1 is added. Alternatively, the mother matrix of the m rows and n columns of the low density parity check code may be a matrix of a double diagonal structure.

For example, if the mother matrix of the m rows and n columns of the low density parity check code is a dual diagonal structure, the fifth matrix of h rows and j columns is subjected to the row splitting operation, and the obtained third matrix is h_fLine j_fAnd (4) the column.

Specifically, after splitting the elements on the check bits in the row to be split into two elements, the two elements are respectively placed in the two rows after splitting, and then the same new check bits are added to connect the two rows after splitting, so that the right side of the matrix after splitting still keeps the double diagonal structure unchanged.

In one particular embodiment, it is assumed that each row participates in row splitting, e.g., the matrix is represented by:

when performing row splitting, the parity check matrix H is now₁The two rows of elements in the system are respectively disassembled, in the disassembling process, after the elements on the information bit and the check bit are disassembled into two elements, the two elements are respectively placed in the two rows after the disassembly, and the disassembly is carried out according to the equipartition principle. The matrix after the specific splitting is shown as the formula 1-6:

then, each column (check matrix H) in the corresponding column of check bits₂Column 9 and column 10) are followed by a column of identical new parity bits, respectively, and the parity bit elements are all-1. The check matrix after the new check bits are added is shown as the formula 1-7:

the last step of the row splitting is to replace the element with a certain two of-1 in the added new check bits with 0 element, so as to ensure that the right side of the split check matrix still keeps the dual diagonal structure unchanged. According to the check matrix shown in the above formulas 1 to 7, it is necessary to replace-1 elements in the first row, the tenth column and the tenth column of the second row with 0 elements, and replace-1 elements in the third row, the twelfth column and the twelfth column of the fourth row with 0 elements, so as to satisfy that the right side of the check matrix still keeps the dual diagonal structure unchanged, and the specific check formula is shown in the formulas 1 to 8:

according to the LDPC construction theory, the short loops in the check matrix deteriorate the decoding performance, and the line splitting process does not generate a new short loop, thereby not causing deterioration of the decoding performance.

In this embodiment, the example of splitting a row once, where all rows participate in splitting each time is described, and the way of splitting a row once and splitting a row only, and the way of splitting multiple times are similar to one time, and are not described again here.

In a second specific implementation, the splitting may be performed first, and then the expansion operation may be performed.

Specifically, at least one row splitting operation is performed on a mother matrix of the low density parity check code with m rows and n columns to obtain m rows and n columns_fLine n_fA sixth matrix of columns, where f is the number of times the parent matrix is row split, and f is a positive integer greater than or equal to 1;

to m_fLine n_fThe sixth matrix of the column is expanded at least once to obtain a third matrix of i rows and l columns, wherein i is greater than m_fIs a positive integer of greater than n_fPositive integer of (1), i-m_fIs equal to l-n_f。

The specific process of the row splitting and the process of the expanding are similar to those of the first embodiment, and are not described again here.

It should be noted that, through continuously using the extension method and the line splitting method in the method of the present invention to perform testing, it is found that if the extension method is used alone to achieve rate matching of low code rate, although the performance of the code word waterfall region can be improved, the performance of the error platform region is deteriorated; in contrast, if the line splitting method is used alone to achieve rate matching at a low code rate, the performance of the false floor region may be improved, but the performance of the waterfall region may be deteriorated. Therefore, in the present application, the expansion method and the row splitting method are combined, the ratio of the single column number to the dual column number is flexibly adjusted according to the requirement of the operating point, and the single column number and the dual column number are kept at an appropriate ratio, so that the performance of a code waterfall region (a region where the bit error rate decreases very fast) can be improved, and the performance of an error platform region can be improved. So that the overall performance is optimized.

The single column weight is a column with the column weight of 1, an identity matrix is introduced in the downward expansion process, and the column weight of each column of the identity matrix is 1; the double-column double column is a column with the column weight of 2, the column weight of each column of the double diagonal structure is 2, the line splitting is the inverse operation of the line merging, and one column with the column weight of 2 is added once per splitting.

In another optional manner, if a negative response to decoding the second codeword sent by the receiving end is received, if a code rate of the third codeword is less than or equal to a code rate of the first codeword, the third codeword should be a codeword equal to the first codeword, and at this time, the third codeword is sent to the receiving end.

It should be noted that, by combining the expansion algorithm and the row splitting algorithm, when the number of the single-column double-column columns and the number of the double-column columns are ensured to be in a proper proportion, the performance of the waterfall area and the performance of the error platform area can be effectively improved at the same time. In addition, the low-code-rate LDPC codes in a larger range can be flexibly obtained.

The embodiment of the invention provides a signal transmission method, a device and a system, a transmitting end carries out corresponding deformation processing on a check matrix corresponding to an LDPC code according to the requirement of a receiving end, wherein the deformation processing comprises row merging operation and punching operation; or performing line splitting operation, expanding operation and the like. And then coding is carried out according to the processed check matrix and the information sequence sent by the information source, and a code word is generated and then sent to a receiving end for decoding. When the performance is reduced more due to punching, the row merging operation is carried out, and high code rate can be obtained. Or, the code word of the check bit is added by carrying out expansion and row splitting operation on the check matrix, so that the code rate can be reduced. By the method, the code rate of the low-density parity check code can be flexibly adjusted, and the LDPC code with flexible and variable rate is constructed in a larger range. Meanwhile, the receiving end can decode the LDPC code more conveniently.

Another signal transmission method is provided in the second embodiment of the present invention, as shown in fig. 3, fig. 3 is a flowchart of another signal transmission method provided in the second embodiment of the present invention. The method is mainly executed by a receiving end, and comprises the following steps,

at step 310, a second codeword is received.

Specifically, in the first embodiment, it can be known that the second codeword is a second codeword sent by the sending end and generated according to the code rate of the second codeword and the second matrix.

And after the receiving end receives the second code word, the receiving end needs to decode the second code word.

The specific method is as follows.

And 320, performing LDPC decoding on the second code word according to the second matrix to obtain an information sequence.

Specifically, the second matrix is obtained by performing at least one row merging operation on a mother matrix corresponding to the information sequence and deleting at least one column of check bits.

The step of obtaining the second matrix is: performing at least one row merging operation on all row elements of a mother matrix corresponding to the information sequence to obtain a fourth matrix, wherein the fourth matrix comprises information bits and check bits; and deleting at least one row of check bits in all rows of check bits in the fourth matrix, wherein the total row number of the check bits of the fourth matrix is greater than or equal to two, and all elements of the deleted at least one row of check bits are less than zero.

The more detailed method steps for obtaining the second matrix are already introduced in step 110 of the first embodiment, and the reader may refer to step 110 of the first embodiment, which is not described herein again.

It should be noted that the mother matrix corresponding to the information sequence is the mother matrix of the LDPC code, that is, the check matrix with the lowest code rate. At a transmitting end, an information sequence is first encoded, wherein the information sequence is information source bits which are received by the transmitting end and transmitted by an information source.

For example, the LDPC code is a mother matrix H (m, n) of a QC-LDPC code of a dual diagonal structure, the spreading factor is z, and the code rate can be expressed by equation 3-1:

let R be_iDenotes the ith row, C of the mother matrix_iRepresenting the ith column of the mother matrix. d (C)_i) The column weight of the ith column is shown (after the check matrix is expanded, the number of non-zero elements in each row is referred to as row weight, and the number of non-zero elements in each column is referred to as column weight). Wherein the first column C in the check bits of the matrix H_n-mColumn weight d (C) of_n-m) 3, the other check bits form a set Cset₀＝{C_n-m+1,C_n-m+2,┈┈C_nIn any column C of the set_iColumn weight d (C) of_i) Where n and m are both positive integers, and n is greater than or equal to m, and i is a positive integer greater than or equal to n-m and less than or equal to n.

Of course, during the decoding process, there is a possibility that the receiving end fails to decode the second codeword according to the second matrix. At this time, the receiving end will send a negative response of the second codeword decoding failure to the transmitting end. And when the transmitting end receives the negative response of the second code word decoding failure, the transmitting end sends a third code word to the receiving end. The receiving end receives the third codeword.

In one case, if the code rate of the third codeword is greater than the code rate of the mother matrix corresponding to the information sequence, the third matrix is determined according to the code rate of the third codeword and the second matrix. Also, the code rate of the third codeword is less than or equal to the code rate of the second codeword.

And the specific third matrix acquisition mode is obtained by performing at least one expansion and at least one row splitting operation according to the second matrix. The method for obtaining the third matrix by performing at least one expansion and at least one row splitting operation on the second matrix has been described in detail in the first embodiment, and is not described herein again for simplicity and convenience of description.

In another case, if the code rate of the third codeword is less than or equal to the code rate of the mother matrix corresponding to the information sequence, the third matrix is equal to the mother matrix corresponding to the information sequence. The receiving end can perform LDPC decoding on the third codeword according to the mother matrix corresponding to the information sequence.

And finally, the receiving end performs LDPC decoding on the third code word according to the third matrix.

In the present embodiment, how to encode the LDPC code and how to decode the LDPC code have been described separately in detail, and the details are referred to as a method flow of encoding the LDPC code and a method flow of decoding the LDPC code in the following.

FIG. 4 is a flow chart 400 of a method of LDPC code encoding. Specifically, as shown in fig. 4:

at step 410, LDPC encoding is performed on the input information bits.

After the structure of the initial matrix and the method for implementing puncturing and row merging (for example, the method for puncturing and row merging in the first embodiment) are determined, the transmitting end may perform coding according to the lowest code rate supported by the rate matching scheme (where the lowest code rate refers to the lowest code rate obtained after the initial matrix is subjected to the processes of spreading, row splitting, and the like), and the coding algorithm may adopt a general gaussian elimination coding method, or a simplified coding method for a double-diagonal structure or other corresponding simplified coding structures, without any limitation on the specific coding algorithm of the transmitting end in the present scheme.

Then, according to the sequence of the mother matrix expanding to the low code rate, marking the corresponding part in the code word as a redundant code word m as the total times of matrix expanding or row splitting operation; marking the corresponding part in the code word as a redundant code word n according to the sequence of the parent matrix deformation to the high code rate as the total times of matrix punching or row merging operation; the remaining encoded codeword portions are labeled as the base codeword, and since the LDPC code is a systematic code, all information bits to be encoded and redundant bits other than the redundant codeword and the redundant codeword should be included in the base codeword. The redundant code words and the redundant code words form rate matching redundant bits

It should be noted that, when the transmitting end transmits a codeword with a high code rate to the receiving end, the initially transmitted codeword must be a codeword with a preset highest code rate. And the code word with the highest code rate is the code word processed by puncturing and row combination. In the decoding process of the receiving end, if the decoding fails according to the codeword with the highest code rate, the transmitting end needs to reissue the deleted codeword. The deleted code words are sent in reverse order to the deleted code words. Namely, the last deleted code word is sent to the receiving end first. Thus, the elements in the redundant codeword are in reverse order. Similarly, the purpose of combining the redundant code words and the redundant code words into rate matching redundant bits is also to determine the order of the deletion code words which are retransmitted from the transmitting end to the receiving end. The specific operation process is as described in step 420.

Step 420, the LDPC coded codeword is transmitted.

After the coding is finished, according to a preset initial transmission code rate and the sequence of the vectors, a certain number of redundant code words are selected from the redundant code words, and the redundant code words and the basic code words are combined to form an initial transmission code word to ensure that the initial transmission code word meets the preset initial transmission code rate. After that, the sending device may send the code word after LDPC encoding, and the specific sending process is not described herein again.

Fig. 5 is a flowchart 500 of an LDPC code decoding method, which is specifically shown in fig. 5:

and 510, decoding the initially transmitted LDPC code word according to the initial code rate.

After receiving the code word, the receiving end needs to calculate the LDPC code matrix corresponding to the code rate according to the predetermined initial transmission code rate, and perform corresponding deformation on the initial mother matrix according to the redundant code word and the number of the redundant code word portions included therein. The specific process is as follows:

for example, assume that redundant bits deleted after the k-th row merging constitute a set D_kWhen the initial transmission code word does not contain the redundant code word (the initial transmission code word is not expanded), it is assumed that the redundant code word contained in the initial transmission code word does not contain D_kIf all the elements in the matrix include all or part of the elements, the receiving end needs to perform k row merging operations on the mother matrix for k times, where k is greater than or equal to 0. Then, if the redundant code word contained in the initial transmission only contains the elements in the part, the elements not contained in the redundant code word are the punctured elements, the receiving end needs to set the channel soft values of the punctured bits to 0,and decoding by taking the mother matrix after row combination as a decoding matrix.

For example, when the initial codeword includes both redundant codewords and redundant codewords, if there are elements in the redundant codewords that can be obtained by performing the row splitting operation k times, the receiving end performs the row splitting operation k times on the mother matrix, where k is greater than or equal to 0. If the redundant code words contained in the initial transmission also contain elements which can be obtained only by m times of matrix expansion, m times of matrix expansion is needed to be carried out on the mother matrix, and after m is larger than or equal to 0, the matrix after row splitting and expansion is used as a decoding matrix for decoding.

The decoding algorithm can adopt a reverse belief propagation algorithm, a minimum sum algorithm, a layered minimum sum algorithm or other existing LDPC decoding algorithms, and the scheme does not limit the specific decoding algorithm of the receiving end.

And step 520, if the decoding of the initial transmission code word has errors, decoding the combined code word with the code rate lower than the initial code rate, and acquiring the information to be transmitted from the decoding result.

And if the receiving end uses the initial code rate for decoding and has errors, returning a decoding error mark to the transmitting end. The sending end selects a certain number of residual redundant bits from the redundant bits to send according to the predetermined retransmission code rate. After the receiving end combines the reissued redundant bits and the initial transmission code word, the combined code word is decoded according to the method described in step 510.

Step 530, if the decoding is wrong again after retransmission, the redundant bits are continuously sent again until the decoding is correct or the maximum retransmission times is reached.

And if the receiving end decodes the code words combined after the retransmission once again, the error decoding mark is returned to the sending end again. The transmitting end continuously selects a certain number of residual redundant bits from the redundant bits to transmit, and if no redundant bits which are not transmitted yet exist, the transmitting end repeatedly transmits the previously transmitted parts according to the sequence from the beginning to the end. After the receiving end combines the reissued redundant bits and the initial transmission code word, the combined code word is decoded according to the method described in step 510.

Step 530 is repeated until correct decoding is achieved or a predetermined maximum number of retransmissions is reached.

Fig. 6 is a schematic diagram illustrating comparison of simulation results of a plurality of parity check code rate matching methods according to an embodiment of the present invention. Compared with the existing method that the samsung company singly uses K times of iterative recoverable code words, the LTE Turbo method and the method provided by the invention have the performance that the information bit length n is 1152, an AWGN channel and BPSK modulation; the code rate of the method and the Turbo code is changed from 0.33 to 0.88; the middle point of the curve in the figure is a blank circle, the simulation curve is realized by a K-SR method, and the code rate change range of the K-SR method is from 0.5 to 0.8 (as shown in the figure, the simulation curve realized by the K-SR method is represented from left to right, and the code rates are 0.5, 0.6, 0.67 and 0.8 in sequence); the middle point of the curve is a solid circle, the simulation curve is realized by the LTE Turbo method, the code rate of the Turbo code ranges from 0.33 to 0.88 (as shown in the figure, the simulation curve realized by the LTE Turbo method is represented by the code rates of 0.33, 0.4, 0.5, 0.6, 0.67, 0.8 and 0.88 from left to right in sequence); the point of the curve in the figure is a prismatic simulation curve realized by the method (as shown in the figure, the simulation curve realized by the method is represented as the code rate from left to right, and the code rate is 0.33, 0.4, 0.5, 0.6, 0.67, 0.8 and 0.88 in sequence). As can be seen from the comparison of the figures, the method is superior to the performance of direct k-SR punching in the range of 0.5 to 0.8; the code rate range of 0.66 to 0.88 is better than that of LTE Turbo, the code rate range of 0.4 to 0.6 is close to that of LTE Turbo performance, and the code rate range of 0.33 is slightly worse than that of LTE Turbo.

In addition, corresponding to the method for transmitting a signal provided in the first embodiment of the present invention, a transmitting end is provided in the third embodiment of the present invention, as shown in fig. 7, fig. 7 is a schematic diagram of an apparatus structure of the transmitting end provided in the first embodiment of the present invention, where the transmitting end includes: encoding section 701, processing section 702, and transmitting section 703.

And an encoding unit 701, configured to perform LDPC encoding on the information sequence according to the code rate of the second codeword and the second matrix to obtain the second codeword.

The processing unit 702 is configured to perform at least one row merging operation on the mother matrix corresponding to the information sequence, delete at least one column of check bits, and obtain a second matrix.

The method comprises the following specific steps:

the processing unit 702 performs at least one row merging operation on all row elements of the mother matrix corresponding to the information sequence to obtain a fourth matrix, where the fourth matrix includes information bits and check bits, and deletes at least one column of check bits in all columns of the check bits in the fourth matrix, where a total number of columns of the check bits of the fourth matrix is greater than or equal to two, and all elements of the deleted at least one column of the check bits are less than zero.

A sending unit 703 is configured to send the second codeword to the receiving end.

Optionally, the transmitting end may further include: a receiving unit 704, configured to receive a negative acknowledgement of the receiving end for decoding the second codeword.

In one case, the encoding unit 701 is further configured to, when the code rate of the third codeword is greater than the code rate of the mother matrix corresponding to the information sequence, obtain the third codeword according to the code rate of the third codeword and the third matrix, where the code rate of the third codeword is less than or equal to the code rate of the second codeword. The third matrix is obtained by the processing unit 702 performing at least one expansion and at least one row splitting operation on the second matrix.

In another case, the encoding unit is further configured to obtain the third codeword according to the mother matrix corresponding to the information sequence when the code rate of the third codeword is less than or equal to the code rate of the mother matrix corresponding to the information sequence.

Finally, the sending unit 702 is further configured to send the third codeword to a receiving end.

The functions of each component of the transmitting end in the embodiments of the present application can be implemented by the method steps in the first embodiment, and therefore, the specific working process of the transmitting end provided by the present application is not repeated herein.

Corresponding to another signal transmission method provided in the second embodiment of the present invention, a receiving end is provided in the fourth embodiment of the present invention, as shown in fig. 8, fig. 8 is a schematic diagram of an apparatus structure of a receiving end provided in the second embodiment of the present invention, where the receiving end includes: a receiving unit 801, a processing unit 802, and a decoding unit 803.

A receiving unit 801 is configured to receive the second codeword.

The processing unit 802 performs at least one row merging operation on the mother matrix corresponding to the information sequence, and deletes at least one column of check bits to obtain a second matrix.

The method comprises the following specific steps: the processing unit 802 performs at least one row merging operation on all row elements of the mother matrix corresponding to the information sequence to obtain a fourth matrix, where the fourth matrix includes information bits and check bits, and deletes at least one column of check bits in all columns of the check bits in the fourth matrix, where a total number of columns of the check bits of the fourth matrix is greater than or equal to two, and all elements of the deleted at least one column of the check bits are less than zero.

A decoding unit 803, configured to perform LDPC decoding on the second codeword according to the second matrix to obtain an information sequence.

Optionally, the receiving end further includes: a sending unit 804.

The sending unit 804 is configured to send a negative response of the decoding failure of the second codeword to the transmitting end when the decoding unit fails to perform LDPC decoding on the second codeword according to the second matrix.

At this time, the transmitting end will send the third codeword to the receiving end after receiving the negative response of the second codeword decoding failure.

Therefore, the receiving unit 801 is also configured to receive a third codeword.

In one case, when the code rate of the third codeword is greater than the code rate of the corresponding mother matrix of the information sequence, the decoding unit 803 is further configured to LDPC-decode the third codeword according to the third matrix. The code rate of the third codeword is less than or equal to the code rate of the second codeword, and the third matrix is obtained by the processing unit 802 performing at least one expansion and at least one row splitting operation on the second matrix.

In another case, when the code rate of the third codeword is less than or equal to the code rate of the mother matrix corresponding to the information sequence, the decoding unit 803 is further configured to perform LDPC decoding on the third codeword according to the mother matrix corresponding to the information sequence.

The functions of each component of the receiving end in the embodiment of the present application can be implemented by the method steps in the second embodiment, and therefore, the specific working process of the receiving end provided by the present application is not repeated herein.

Finally, an embodiment of the present invention further provides a signal transmission system, specifically as shown in fig. 9, the signal transmission system includes, for example, a transmitting end and a receiving end. As already described in the initial part of the description of the present invention, the transmitting end and the receiving end may be a network device such as a base station and a terminal that need to perform data transmission in a wireless transmission manner, respectively. For example, when the transmitting end is a base station, the corresponding receiving end is a terminal; on the contrary, when the transmitting end is a terminal, the receiving end is a base station.

Fig. 10 is a schematic structural diagram 1000 of a transmitting end according to a sixth embodiment of the present invention, as shown in fig. 10, the transmitting end includes a processor 1001 and a transmitter 1002.

The processor is configured to perform LDPC encoding on the information sequence according to the code rate of the second codeword and the second matrix to obtain the second codeword.

The second matrix is obtained by the processor 1001 performing at least one row merging operation on the mother matrix corresponding to the information sequence and deleting at least one column of check bits.

The process of specifically acquiring the second matrix is as follows: and performing at least one row combination operation on all row elements of the mother matrix corresponding to the information sequence to obtain a fourth matrix, wherein the fourth matrix comprises information bits and check bits, and deleting at least one column of check bits in all columns of check bits in the fourth matrix, the total column number of the check bits of the fourth matrix is greater than or equal to two, and all elements of the deleted at least one column of check bits are less than zero.

Optionally, the transmitting end may further include a receiver 1003, which receives a negative acknowledgement of the second codeword from the receiving end.

When the transmitting end receives the negative response sent by the receiving end, the code word with low code rate needs to be sent to the receiving end again.

Therefore, in an embodiment, when the code rate of the third codeword is greater than the code rate of the mother matrix corresponding to the information sequence, the processor 1001 is further configured to obtain the third codeword according to the code rate of the third codeword and the third matrix, where the code rate of the third codeword is less than or equal to the code rate of the second codeword. The third matrix is obtained by the processor 1001 performing at least one expansion and at least one row splitting operation on the second matrix.

In another case, when the code rate of the third codeword is less than or equal to the code rate of the mother matrix corresponding to the information sequence, the processor 1001 is further configured to obtain the third codeword according to the mother matrix corresponding to the information sequence.

Finally, the transmitter 1002 is configured to transmit the third codeword to the receiving end.

The functions performed by each component in the transmitting end can refer to the method described in the first embodiment, and are not described herein again. The specific processor encoding process may refer to the method flow portion of LDPC code encoding.

Fig. 11 is a schematic structural diagram 1100 of a transmitting end according to a seventh embodiment of the present invention, and as shown in fig. 11, the receiving end includes: a receiver 1101, a processor 1102.

A receiver 1101 for receiving a second codeword.

And a processor 1102, configured to perform LDPC decoding on the second codeword according to the second matrix to obtain an information sequence. The second matrix is obtained by the processor 1102 performing at least one row merging operation on the mother matrix corresponding to the information sequence and deleting at least one column of check bits.

In addition, the receiving end further includes a transmitter 1103 configured to transmit a negative acknowledgement that the decoding of the second codeword failed to the transmitting end when the processor fails to LDPC-decode the second codeword according to the second matrix.

At this time, when the transmitting end receives the negative acknowledgement of the decoding failure, the transmitting end will resend the code word with the code rate lower than the second code word to the receiving end.

Receiver 1101 is also for receiving a third codeword.

In one case, the processor 1102 is further configured to LDPC-decode the third codeword according to the third matrix when a code rate of the third codeword is greater than a code rate of a corresponding mother matrix of the information sequence. And the code rate of the third code word is less than or equal to that of the second code word. The third matrix is obtained by the processor 1102 performing at least one expansion and at least one row splitting operation on the second matrix.

In another case, when the code rate of the third codeword is less than or equal to the code rate of the mother matrix corresponding to the information sequence, the processor 1102 is further configured to perform LDPC decoding on the third codeword according to the mother matrix corresponding to the information sequence.

The functions executed by each component in the receiving end may refer to the method described in embodiment two, and are not described herein again. The specific decoding process of the processor can refer to the flow part of the LDPC code decoding method.

Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, a software module executed by a processor, or a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

A method of signal transmission, the method comprising:

performing low-density parity check (LDPC) coding on the information sequence according to the code rate of the second code word and the second matrix to obtain a second code word;

sending the second code word to a receiving end;

and the second matrix is obtained by performing at least one row merging operation on the mother matrix corresponding to the information sequence and deleting at least one column of check bits.
The method of claim 1, further comprising:

receiving a negative response of a receiving end to the second code word decoding;

if the code rate of the third code word is greater than the code rate of the mother matrix corresponding to the information sequence, obtaining the third code word according to the code rate of the third code word and the third matrix;

sending the third code word to a receiving end;

wherein a code rate of the third codeword is less than or equal to a code rate of the second codeword; and the third matrix is obtained by performing at least one expansion and at least one row splitting operation on the second matrix.
The method of claim 1,

receiving a negative response of a receiving end to the second code word decoding;

if the code rate of the third code word is less than or equal to the code rate of the mother matrix corresponding to the information sequence, obtaining the third code word according to the mother matrix corresponding to the information sequence;

and sending the third code word to a receiving end.
The method according to any of claims 1 to 3, wherein the second matrix is in particular:

performing at least one row merging operation on all row elements of a mother matrix corresponding to the information sequence to obtain a fourth matrix, wherein the fourth matrix comprises information bits and check bits;

and deleting at least one row of check bits in all rows of check bits in the fourth matrix, wherein the total row number of the check bits of the fourth matrix is greater than or equal to two, and all elements of the deleted at least one row of check bits are less than zero.
A method of signal transmission, the method comprising:

receiving a second codeword;

performing Low Density Parity Check (LDPC) decoding on the second code word according to a second matrix to obtain an information sequence;

and the second matrix is obtained by performing at least one row merging operation on the mother matrix corresponding to the information sequence and deleting at least one column of check bits.
The method of claim 5,

if the LDPC decoding of the second code word according to the second matrix fails, sending a negative response of the decoding failure of the second code word to a transmitting terminal;

receiving a third codeword;

if the code rate of the third code word is greater than the code rate of the corresponding mother matrix of the information sequence, determining a third matrix according to the code rate of the third code word and the second matrix;

LDPC decoding the third codeword according to the third matrix;

wherein a code rate of the third codeword is less than or equal to a code rate of the second codeword; and the third matrix is obtained by performing at least one expansion and at least one row splitting operation on the second matrix.
The method of claim 5,

if the LDPC decoding of the second code word according to the second matrix fails, sending a negative response of the decoding failure of the second code word to a transmitting terminal;

receiving a third codeword;

and if the code rate of the third code word is less than or equal to the code rate of the mother matrix corresponding to the information sequence, performing LDPC decoding on the third code word according to the mother matrix corresponding to the information sequence.
The method according to any of claims 5 to 7, characterized in that the second matrix is in particular:

performing at least one row merging operation on all row elements of a mother matrix corresponding to the information sequence to obtain a fourth matrix, wherein the fourth matrix comprises information bits and check bits;

and deleting at least one row of check bits in all rows of check bits in the fourth matrix, wherein the total row number of the check bits of the fourth matrix is greater than or equal to two, and all elements of the deleted at least one row of check bits are less than zero.
A transmitting end, comprising:

the coding unit is used for carrying out low-density parity check (LDPC) coding on the information sequence according to the code rate of the second code word and the second matrix to obtain the second code word;

the processing unit is used for performing at least one row merging operation on the mother matrix corresponding to the information sequence, deleting at least one column of check bits and acquiring a second matrix;

and the sending unit is used for sending the second code word to a receiving end.
The transmitting end according to claim 9, wherein the transmitting end further comprises:

a receiving unit, configured to receive a negative acknowledgement of decoding the second codeword by a receiving end;

the coding unit is further configured to, when a code rate of a third codeword is greater than a code rate of a mother matrix corresponding to the information sequence, obtain the third codeword according to the code rate of the third codeword and the third matrix;

the sending unit is further configured to send the third codeword to a receiving end;

wherein a code rate of the third codeword is less than or equal to a code rate of the second codeword; the third matrix is obtained by the processing unit performing at least one expansion and at least one row splitting operation on the second matrix.
The transmitting end according to claim 9, wherein the transmitting end further comprises:

a receiving unit, configured to receive a negative acknowledgement of decoding the second codeword by the receiving end;

the encoding unit is further configured to, when a code rate of a third codeword is less than or equal to a code rate of a mother matrix corresponding to the information sequence, obtain the third codeword according to the mother matrix corresponding to the information sequence;

the sending unit is further configured to send the third codeword to a receiving end.
The transmitting end according to any of claims 9-11, wherein the processing unit is specifically configured to:

performing at least one row merging operation on all row elements of a mother matrix corresponding to the information sequence to obtain a fourth matrix, wherein the fourth matrix comprises information bits and check bits;

and deleting at least one row of check bits in all rows of check bits in the fourth matrix, wherein the total row number of the check bits of the fourth matrix is greater than or equal to two, and all elements of the deleted at least one row of check bits are less than zero.
A receiving end, comprising:

a receiving unit, configured to receive a second codeword;

the processing unit is used for carrying out at least one row merging operation on the mother matrix corresponding to the information sequence, deleting at least one column of check bits and acquiring a second matrix;

and the decoding unit is used for carrying out low-density parity check (LDPC) decoding on the second code word according to the second matrix to obtain an information sequence.
The receiving end according to claim 13, wherein the receiving end further comprises:

a transmission unit: when the decoding unit fails to perform LDPC decoding on the second code word according to the second matrix, sending a negative response that the decoding of the second code word fails to the transmitting terminal;

the receiving unit is further configured to receive a third codeword;

the decoding unit is further configured to perform LDPC decoding on the third codeword according to the third matrix when a code rate of the third codeword is greater than a code rate of a corresponding mother matrix of the information sequence;

wherein a code rate of the third codeword is less than or equal to a code rate of the second codeword; the third matrix is obtained by the processing unit performing at least one expansion and at least one row splitting operation on the second matrix.
The receiving end according to claim 13, wherein the receiving end further comprises:

the sending unit is used for sending a negative response of the second code word decoding failure to a transmitting end when the decoding unit fails to perform LDPC decoding on the second code word according to the second matrix;

the receiving unit is further configured to receive a third codeword;

and the decoding unit is further configured to perform LDPC decoding on the third codeword according to the mother matrix corresponding to the information sequence when the code rate of the third codeword is less than or equal to the code rate of the mother matrix corresponding to the information sequence.
Receiving end according to any of claims 13-15, wherein the processing unit is specifically configured to,

performing at least one row merging operation on all row elements of a mother matrix corresponding to the information sequence to obtain a fourth matrix, wherein the fourth matrix comprises information bits and check bits;

and deleting at least one row of check bits in all rows of check bits in the fourth matrix, wherein the total row number of the check bits of the fourth matrix is greater than or equal to two, and all elements of the deleted at least one row of check bits are less than zero.