CN101572554A - Method and device for generating code-rate-compatible LDPC codes and HARQ scheme - Google Patents
Method and device for generating code-rate-compatible LDPC codes and HARQ scheme Download PDFInfo
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Abstract
The invention relates to the technical field of channel coding of mobile communication, in particular to a method and a device for generating code-rate-compatible quasi-cyclic LDPC codes. The method comprises the following steps: obtaining the low rate requirements of a system and the degree distribution of high rate quasi-cyclic LDPC codes and designing the degree distribution of low rate quasi-cyclic LDPC codes; determining check nodes needing decomposing and variation nodes needing extension in the high rate quasi-cyclic LDPC codes during constructing the low rate quasi-cyclic LDPC codes; constructing a check matrix of the low rate quasi-cyclic LDPC codes based on a construction method and the limitations of the low rate quasi-cyclic LDPC codes on the check part structure of the check matrix; weaving the obtained check bits of the quasi-cyclic LDPC codes and obtaining rate-compatible codes through deleting. The embodiment of the invention further provides a device for implementing the method, and provides a HARQ scheme based on the rate-compatible LDPC codes.
Description
Technical field
The present invention relates to the channel coding technology field of mobile communication, particularly a kind of method and device that generates code-rate-compatible LDPC codes and generate the HARQ scheme.
Background technology
Low-density parity check (LDPC, low density parity check) sign indicating number is a kind of linear block codes that Gallager proposed in 1962, because in its check matrix " 1 " number less, therefore be called as low-density parity check sign indicating number, proposed again in 1996 also to be improved by Mackay then.Except representing the LDPC sign indicating number with check matrix, can also represent the LDPC sign indicating number with Tanner figure (see figure 1), Tanner figure and check matrix are direct correspondences, are made of variable node, check-node and the limit that is connected them.Each check-node z
iCorresponding to the delegation of check matrix, each variable node xi is corresponding to row of check matrix.When a certain bit in the code word is included in a certain check equations, promptly corresponding position is 1 o'clock in the check matrix, has line between check-node among Fig. 1 and the variable node.For each node, the limit number that is attached thereto is called the number of degrees of this node.
The LDPC sign indicating number is a kind of channel coding technology that adopts more function admirable at present, and its main feature is to support iterative decoding, so decoding performance is limit near Shannon capacity.The LDPC sign indicating number has lower decoding complexity, and supports that parallel decoding improves the decoder throughput, is a kind of more excellent channel coding schemes in the high-speed communication system of future generation therefore.
Use the more quasi-cyclic LDPC code that is based on the cyclic shift matrices design at present, its check matrix H
M * nAs shown in Figure 2, n is a code length, and m is the number of check bit in the code word, and the information bit number is k=n-m.P wherein
I, jBe cyclic shift matrices or the null matrix of z * z.Check matrix H
M * nCan be regarded as by size is m
b* n
bThe biradical check matrix H
bZ expands according to spreading factor, wherein n=z * n
b, m=z * m
b, z is an integer.During the expansion of biradical matrix, the right cyclic shift matrices of element 1 usefulness z * z is replaced, and element 0 usefulness z * z zero battle array is replaced.H
M * nIn each circulating unit battle array can by its to the right the cyclic shift amount determine, can be incorporated into biradical check matrix information and circular shift information in the basic check matrix, be designated as H
BmH
BmAnd H
bDimension is identical, H
BmDirectly by H
bObtain: with H
bIn 0 change-1 into, be defined as z * z zero battle array, 1 element changes the cyclic shift amount into.By H
BmCan directly obtain H by the spreading factor expansion
M * nWhen the structure quasi-cyclic LDPC code,, construct to optimize the ring distribution by the position of definite cyclic shift matrices and the size of cyclic shift amount based on basic check matrix.
In order to support HARQ (Hybrid Automatic Repeat request mixes re-transmission automatically) scheme, employed quasi-cyclic LDPC code based on the cyclic shift matrices design is a kind of code-rate-compatible sign indicating number, be that high code check quasi-cyclic LDPC code code word bits is included in the quasi-cyclic LDPC code code word bits of low code check, only need a generating apparatus and a decoder just can realize the coding and the decoding of different code checks.
Utilize extended method structure code-rate-compatible quasi-cyclic LDPC code in the prior art, by increasing more check bit, by the low code check quasi-cyclic LDPC code of high code check quasi-cyclic LDPC code structure, adopt in the low code check quasi-cyclic LDPC code that extended method obtains corresponding to the number of degrees of the check-node of high code check quasi-cyclic LDPC code and can not adjust flexibly, the performance of quasi-cyclic LDPC code has to be optimized.Decomposition method is a kind ofly to be decomposed into the method that two low check-nodes of the number of degrees are constructed low code check quasi-cyclic LDPC code by the check-node that the number of degrees of high code check quasi-cyclic LDPC code are high, and generally can not increase becate, even also might reduce becate, improve the length of enclosing of low code check quasi-cyclic LDPC code.Adopt in the low code check quasi-cyclic LDPC code that said method obtains corresponding to the number of degrees of the variable node of high code check quasi-cyclic LDPC code and can not adjust flexibly, the performance of coding has to be optimized.
Summary of the invention
The embodiment of the invention provides a kind of generation method of code-rate-compatible quasi-cyclic low-density parity check sign indicating number, guarantee when using this method to obtain in the low code check quasi-cyclic low-density parity check sign indicating number, the number of degrees corresponding to the check-node of high code check quasi-cyclic low-density parity check sign indicating number can reduce along with the reduction of code check by decomposition method, the number of degrees corresponding to the variable node of high code check quasi-cyclic low-density parity check sign indicating number can increase along with the reduction of code check by extended method, said method comprising the steps of:
The low code check of acquisition system requires and the degree of high code check quasi-cyclic low-density parity check sign indicating number distributes, and the degree of the low code check quasi-cyclic low-density parity check sign indicating number of design distributes;
Distribute and the degree of high code check quasi-cyclic low-density parity check sign indicating number distributes variable node that need in the high code check quasi-cyclic low-density parity check sign indicating number in the basic check matrix process of the low code check quasi-cyclic low-density parity check sign indicating number of structure to determine the basic check-node that decomposes and needs to expand according to the degree of described low code check quasi-cyclic low-density parity check sign indicating number;
Based on the restriction of building method and low code check quasi-cyclic low-density parity check sign indicating number to biradical check matrix check part structure, the check matrix of the low code check quasi-cyclic low-density parity check sign indicating number of structure.
The embodiment of the invention also further provides a kind of method that generates code-rate-compatible quasi-cyclic low-density parity check sign indicating number, and described method comprises:
The low code check of acquisition system requires and the degree of high code check quasi-cyclic low-density parity check sign indicating number distributes, and the degree of the low code check quasi-cyclic low-density parity check sign indicating number of design distributes;
Distribute and the degree of high code check quasi-cyclic low-density parity check sign indicating number distributes variable node that need in the high code check quasi-cyclic low-density parity check sign indicating number in the basic check matrix process of the low code check quasi-cyclic low-density parity check sign indicating number of structure to determine the check-node that decomposes and needs to expand according to the degree of described low code check quasi-cyclic low-density parity check sign indicating number;
Based on the restriction of building method and low code check quasi-cyclic low-density parity check sign indicating number to biradical check matrix check part structure, the basic check matrix of the low code check quasi-cyclic low-density parity check sign indicating number of structure;
Obtain low code check quasi-cyclic low-density parity check sign indicating number and delete surplus operation, obtain the quasi-cyclic low-density parity check sign indicating number of code-rate-compatible.
The embodiment of the invention also provides a kind of quasi-cyclic low-density parity check code coder simultaneously, and described encoder comprises:
The test matrix generation unit is used to design the check matrix of quasi-cyclic low-density parity check sign indicating number, and wherein the check part structure of the biradical check matrix of low code check quasi-cyclic low-density parity check sign indicating number is:
Wherein, the number of degrees of first check bit correspondence are 4, h
b(0)=1, h
b(m
b'-1)=1, h
b(k)=1,0＜k＜(m
b'-1), m
b'＞m
b, m
bThe high code check quasi-cyclic low-density parity check sign indicating number of ' expression is through decomposing back corresponding check interstitial content, the number of degrees span of the check bit correspondence that remaining high code check quasi-cyclic low-density parity check sign indicating number corresponding check bit and decomposition method produce is 2≤i≤3, i represents the number of degrees value of check bit correspondence, and the number of degrees of the check bit correspondence that produces by extended method are 1.
The embodiment of the invention provides a kind of mixed automatic retransferring method based on code-rate-compatible quasi-cyclic low-density parity check sign indicating number simultaneously, and described method is:
Determine check bit to be sent original position in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word and the particular location of check bit in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word to be sent, pass through formula
F
k＝(SPID
k*L
k)mod(ParityLen)
Determine check bit to be sent original position in the check bit of whole low code check quasi-cyclic low-density parity check sign indicating number code word, wherein SPID
kExpression bag indicated value, L
kRepresent check bit number to be sent, ParityLen represents the total number of check bit in the low code check quasi-cyclic low-density parity check sign indicating number code word, and k represents number of retransmissions, passes through formula
S
k，i＝(F
k+i)mod(ParityLen)，i＝0，1，L?L
k-1
Determine check bit to be sent particular location in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word;
Send the packet that the information bit connection is formed with the check bit of determining according to above-mentioned formula.
Further, provide a kind of and mix the method for reseptance that retransmits automatically based on code-rate-compatible quasi-cyclic low-density parity check sign indicating number, described method comprises:
Determine to receive in the packet data corresponding to check bit in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word original position and corresponding to the particular location of data in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word of check bit, pass through formula
F
k＝(SPID
k*L
k)mod(ParityLen)
Determine to receive in the packet the original position of data in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word, wherein SPID corresponding to check bit
kExpression bag indicated value, L
kThe check bit number that expression sends, ParityLen are represented the total number of check bit in the low code check quasi-cyclic low-density parity check sign indicating number code word, and k represents number of retransmissions, passes through formula
S
k，i＝(F
k+i)mod(ParityLen)，i＝0，1，L?L
k-1
Determine to receive in the packet the particular location of data in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word corresponding to check bit;
The packet that receives is deciphered, if correct transmission of decoding confirmed feedback signal, if decipher incorrect then send signal unconfirmed.
Further, provide a kind of low-density parity check sign indicating number generating apparatus, described generating apparatus comprises:
Degree distribution determining unit, degree distribution situation based on high code check quasi-cyclic low-density parity check sign indicating number, the degree of the low code check quasi-cyclic low-density parity check sign indicating number of design distributes, and the check part of the biradical check matrix of described high code check quasi-cyclic low-density parity check sign indicating number has the biconjugate corner structure;
Computing unit, be used for distributing and the degree of high code check quasi-cyclic low-density parity check sign indicating number distributes variable node that need in the high code check quasi-cyclic low-density parity check sign indicating number in the basic check matrix process of the low code check quasi-cyclic low-density parity check sign indicating number of structure to determine the check-node that decomposes and needs to expand according to the degree of described low code check quasi-cyclic low-density parity check sign indicating number;
The check matrix generation unit, based on the restriction of building method and low code check quasi-cyclic low-density parity check sign indicating number to biradical check matrix check part structure, the basic check matrix of the low code check quasi-cyclic low-density parity check sign indicating number of structure.
Another kind of code-rate-compatible quasi-cyclic low-density parity check sign indicating number generating apparatus, described generating apparatus comprises:
Degree distribution determining unit, degree distribution situation based on high code check quasi-cyclic low-density parity check sign indicating number, the degree of the low code check quasi-cyclic low-density parity check sign indicating number of design distributes, and the check part of the biradical check matrix of described high code check quasi-cyclic low-density parity check sign indicating number has the biconjugate corner structure;
Computing unit, be used for distributing and the degree of high code check quasi-cyclic low-density parity check sign indicating number distributes variable node that need in the high code check quasi-cyclic low-density parity check sign indicating number in the basic check matrix process of the low code check quasi-cyclic low-density parity check sign indicating number of structure to determine the check-node that decomposes and needs to expand according to the degree of described low code check quasi-cyclic low-density parity check sign indicating number;
The check matrix generation unit, based on the restriction of building method and low code check quasi-cyclic low-density parity check sign indicating number to biradical check matrix check part structure, the basic check matrix of the low code check quasi-cyclic low-density parity check sign indicating number of structure;
Delete surplus operating unit, be used for low code check quasi-cyclic low-density parity check sign indicating number is deleted surplus operation and the different code check quasi-cyclic low-density parity check sign indicating numbers of acquisition system needs, thereby obtain the quasi-cyclic low-density parity check sign indicating number of code-rate-compatible.
The embodiment of the invention also provides a kind of transmitting terminal device, and described transmitting terminal device comprises:
Position calculation unit, it is used to pass through formula
F
k＝(SPID
k*L
k)mod(ParityLen)
Determine check bit to be sent original position in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word, wherein SPID
kExpression bag indicated value, L
kRepresent check bit number to be sent, ParityLen represents the total number of check bit in the low code check quasi-cyclic low-density parity check sign indicating number code word, and k represents number of retransmissions, passes through formula
S
k，i＝(F
k+i)mod(ParityLen)，i＝0，1，L?L
k-1
Determine check bit to be sent particular location in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word;
Transmitting element is used to the packet that sends information bit and form according to the check bit that above-mentioned formula is determined.
A kind of receiving end device further is provided, and described device comprises:
Position calculation unit, it is used to pass through formula
F
k＝(SPID
k*L
k)mod(ParityLen)
Determine to receive in the packet the original position of data in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word, wherein SPID corresponding to check bit
kExpression bag indicated value, L
kThe check bit number that expression sends, ParityLen are represented the total number of check bit in the quasi-cyclic low-density parity check sign indicating number code word of low code check, and k represents number of retransmissions, passes through formula
S
k，i＝(F
k+i)mod(ParityLen)，i＝0，1，L?L
k-1
Determine to receive in the packet the particular location of data in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word corresponding to check bit;
Decoding unit is used for the packet that receives is deciphered;
The feedback signal transmitting element is used for sending and feeds back signal to transmitting terminal, if correct transmission of decoding confirmed feedback signal, if decipher incorrect then send signal unconfirmed.
The method and apparatus that adopts the embodiment of the invention to provide, utilize associating decomposition method and extended method to construct the quasi-cyclic low-density parity check sign indicating number of code-rate-compatible, when using this method to obtain in the low code check sign indicating number, the number of degrees corresponding to the check-node of high code check quasi-cyclic low-density parity check sign indicating number can reduce along with the reduction of code check by decomposition method, can increase along with the reduction of code check by extended method corresponding to the number of degrees of the variable node of high code check quasi-cyclic low-density parity check sign indicating number; Simultaneously delete surplus mode with optimization,, and then generated the quasi-cyclic low-density parity check sign indicating number of code-rate-compatible then by deleting the surplus quasi-cyclic low-density parity check sign indicating number that obtains different code checks based on the check bit deinterleaving method.Proposed corresponding support HARQ scheme on the quasi-cyclic low-density parity check sign indicating number basis that designs based on above method, transmitting-receiving two-end control expense is less, and has improved the performance of whole system.
Description of drawings
Fig. 1 is the Tanner figure expression of LDPC sign indicating number;
Fig. 2 is the check matrix structure chart of quasi-cyclic LDPC code;
Fig. 3 generates LDPC code method flow chart for the embodiment of the invention;
Fig. 4 is the check part structure chart of the biradical check matrix of high code check quasi-cyclic LDPC code among the embodiment;
Fig. 5 is the check part structure chart of the biradical check matrix of the low code check quasi-cyclic LDPC code that constructs among the embodiment;
Fig. 6 is a low code check quasi-cyclic LDPC code codeword structure among the embodiment;
The low code check sign indicating number codeword structure that obtains after Fig. 7 interweaves;
The HARQ flow chart that Fig. 8 designs for the embodiment of the invention;
Fig. 9 provides the LDPC code coder one embodiment block diagram for the embodiment of the invention;
Figure 10 also provides LDPC sign indicating number generating apparatus another embodiment block diagram for the embodiment of the invention;
Figure 11 provides a kind of transmitting terminal device block diagram for the embodiment of the invention;
Figure 12 provides a kind of receiving end device block diagram for the embodiment of the invention.
Embodiment
The embodiment of the invention provides the method for a kind of generation quasi-cyclic low-density parity check (LDPC, low densityparity check) sign indicating number.This method is by high code check quasi-cyclic low-density parity check LDPC sign indicating number design code-rate-compatible quasi-cyclic LDPC code, at first by the basic check matrix of high code check quasi-cyclic LDPC code basic check matrix, and expand to the check matrix of low code check quasi-cyclic LDPC code by spreading factor according to the required low code check quasi-cyclic LDPC code of associating decomposition method and extended method design system; Then, it is as follows that the check bit of designed low code check quasi-cyclic code is carried out interlace operation: is that unit carries out piecemeal to designed low code check quasi-cyclic LDPC code with the spreading factor corresponding to the check bit that the check bit and the decomposition method of high code check quasi-cyclic LDPC code produces, then the check block that generates is interweaved, at last with information bit and the check bit that produces of the check block after interweaving and extended method be multiplexed into a low code check quasi-cyclic LDPC code code word; At last by the low code check quasi-cyclic LDPC code after multiplexing being deleted surplus operation, the different code check quasi-cyclic LDPC codes that the acquisition system needs, thereby the quasi-cyclic LDPC code of acquisition code-rate-compatible.
Consult Fig. 3, the embodiment of the invention generates code-rate-compatible quasi-cyclic LDPC code method flow diagram, and this method flow is as follows:
S301 obtains the low code check requirement of system and the degree of high code check quasi-cyclic LDPC code and distributes, and the degree of the low code check quasi-cyclic LDPC code of design distributes.The check part of the biradical check matrix of the high code check quasi-cyclic LDPC code of Cai Yonging has the biconjugate corner structure in the present embodiment, and the degree of first check bit correspondence is 3.Instantiation as shown in Figure 4, h wherein
b(0)=1, h
b(m
b-1)=1, h
b(k)=1,0＜k＜(m
b-1), m
bCheck-node number before expression is decomposed.
S302, distribute and the degree of high code check quasi-cyclic LDPC code distributes variable node that need in the high code check quasi-cyclic LDPC code in the basic check matrix process of the low code check quasi-cyclic LDPC code of structure to determine the check-node that decomposes and needs to expand according to the degree of described low code check quasi-cyclic LDPC code.
S303, based on the restriction of building method and low code check quasi-cyclic LDPC code to biradical check matrix check part structure, the basic check matrix of the low code check quasi-cyclic LDPC code of structure, and expand to the check matrix of low code check quasi-cyclic LDPC code by spreading factor.Building method described in the present embodiment adopts the method for progressive edge-growth.
In the process of the basic check matrix of constructing low code check quasi-cyclic LDPC code, at first consider of the restriction of low code check quasi-cyclic LDPC code to the check part structure of biradical check matrix, then based on the variable node of the check-node that needs in progressive edge-growth method and the described high code check quasi-cyclic LDPC code to decompose and needs expansion to the basic check matrix of high code check quasi-cyclic LDPC code decompose with extended operation to construct the basic check matrix that hangs down the code check quasi-cyclic LDPC code, in the operating process
Check bit corresponding variable node for low code check quasi-cyclic LDPC code, according to of the restriction of low code check quasi-cyclic LDPC code, adopt the position of progressive edge-growth method selection cyclic shift matrices and corresponding cyclic shift value to construct to optimize the ring distribution to biradical check matrix check part structure;
There are following four kinds of situations in each information bit corresponding variable node for low code check quasi-cyclic LDPC code:
If variable node needing in the basic check matrix of high code check quasi-cyclic LDPC code only to have participated in the verification of the check-node that decomposes, then select preferably is olation to distribute, and the check-node of the low code check quasi-cyclic LDPC code after guaranteeing as far as possible to decompose have the least possible different number of degrees to optimize ring with the progressive edge-growth method;
If variable node only needs expansion, then select the position and the corresponding cyclic shift value of the cyclic shift matrices of expansion to distribute, and guarantee that the check-node of the low code check quasi-cyclic LDPC code after the expansion has the least possible different number of degrees to optimize ring based on the progressive edge-growth method;
If variable node not only needs expansion, and needing in the basic check matrix of high code check quasi-cyclic LDPC code to have participated in the verification of the check-node that decomposes, the ring that then needs to adopt top two kinds of methods to optimize under the different spreading factors simultaneously distributes, and the check-node of the low code check quasi-cyclic LDPC code after guaranteeing expansion as far as possible and decomposing has the least possible different number of degrees;
If variable node neither needs expansion, needing in the basic check matrix of high code check quasi-cyclic LDPC code not participate in the verification of the check-node that decomposes yet, continue to judge other variable node;
Each variable node is all made above-mentioned judgement and corresponding operating, up to having judged all information bit corresponding variable node.
In the present embodiment, the check part structure of the biradical check matrix of low code check quasi-cyclic LDPC code as shown in Figure 5.Wherein, the number of degrees of first check bit correspondence are 4, h
b(0)=1, h
b(m
b'-1)=1, h
b(k)=1,0＜k＜(m
b'-1), m
b'＞m
b, m
bThe high code check quasi-cyclic LDPC code of ' expression is through decomposing back corresponding check interstitial content, the number of degrees span of the check bit correspondence that remaining high code check quasi-cyclic LDPC code corresponding check bit and decomposition method produce is 2≤i≤3, i represents the number of degrees value of check bit correspondence, and number of degrees value can be determined by the density Evolution Theory; The number of degrees of the check bit correspondence that produces by extended method are 1.
S304 carries out interlace operation for the check bit of the low code check quasi-cyclic LDPC code that obtains based on said method.
Check bit based on the low code check quasi-cyclic LDPC code of said method structure is made up of three parts: promptly high code check quasi-cyclic LDPC code corresponding check bit, the check bit that produces based on decomposition method and based on the check bit of extended method generation.
Unite decompose and low code check quasi-cyclic LDPC code codeword structure that the expansion back obtains as shown in Figure 6, comprise the check bit that message part, high code check quasi-cyclic LDPC code corresponding check bit and decomposition method produce, the check bit that extended method produces.
Be that unit carries out piecemeal with the spreading factor at first to high code check quasi-cyclic LDPC code corresponding check bit with based on the check bit that decomposition method produces; Then the check block that generates is interweaved, the check block that guarantees high code check quasi-cyclic LDPC code simultaneously is positioned at before the check block of decomposition method generation, the principle that interweaves is based on deletes in the surplus equivalent basic check matrix that obtains later, and the number of check-node that guarantees to have different number of degrees values is the least possible; At last with information bit and the check bit that produces of the check block after interweaving and extended method be multiplexed into a low code check quasi-cyclic LDPC code code word.
Interweave low code check quasi-cyclic code codeword structure that the back obtains as shown in Figure 7, the check bit that obtains comprising message part, the back that interweaves, the check bit that extended method produces.
S305 deletes surplus operation to the low code check quasi-cyclic LDPC code that the back that interweaves obtains, the different code check quasi-cyclic LDPC codes that the acquisition system needs, the quasi-cyclic LDPC code of acquisition code-rate-compatible.
In concrete enforcement, can low code check quasi-cyclic code not carried out interlace operation, the quasi-cyclic LDPC code that is obtained based on S301 to the S303 step is deleted surplus operation and the different code check quasi-cyclic LDPC codes of acquisition system needs, thereby obtain the quasi-cyclic LDPC code of code-rate-compatible.
Because different code lengths adopts different basic check matrixes down, can increase the memory requirement of system like this, in order to reduce the memory space of system, the general employing of quasi-cyclic LDPC code represented corresponding to the basic check matrix under the maximum code length, by the corresponding down spreading factor of different code length the cyclic shift amount is revised then, obtain the basic check matrix of correction, expand the quasi-cyclic LDPC code check matrix that obtains under the required code length by corresponding spreading factor then.
In order to obtain the basic check matrix under the different code length, behind the basic check matrix of the low code check quasi-cyclic LDPC code of above-mentioned steps S303 acquisition, use spreading factor that the cyclic shift amount is revised, obtain the basic check matrix of correction, obtain the check matrix of the low code check quasi-cyclic LDPC code under the required code length again by corresponding spreading factor expansion.
Accordingly, be applied under the situation of different code length in consideration, check bit corresponding variable node for low code check quasi-cyclic LDPC code, according to hanging down of the restriction of code check quasi-cyclic LDPC code, adopt the progressive edge-growth method to select the position of cyclic shift matrices to distribute with the ring under the optimization different code length and construct with corresponding cyclic shift value to biradical check matrix check part structure;
For being operating as of each information bit corresponding variable node of low code check quasi-cyclic LDPC code:
If variable node needing in the basic check matrix of high code check quasi-cyclic LDPC code only to have participated in the verification of the check-node that decomposes, then select is olation preferably to distribute, and guarantee that as far as possible the check-node of the low code check quasi-cyclic LDPC code after the decomposition has the least possible different number of degrees to optimize different code length ring down with the progressive edge-growth method;
If variable node only needs expansion, then select the position and the corresponding cyclic shift value of the cyclic shift matrices of expansion to distribute, and guarantee that the check-node of the low code check quasi-cyclic LDPC code after the expansion has the least possible different number of degrees with the ring of optimizing under the different code length based on the progressive edge-growth method;
If variable node not only needs expansion, and needing in the basic check matrix of high code check quasi-cyclic LDPC code to have participated in the verification of the check-node that decomposes, the ring that then needs to adopt top two kinds of methods to optimize under the different code length simultaneously distributes, and the check-node of the low code check quasi-cyclic LDPC code after guaranteeing expansion as far as possible and decomposing has the least possible different number of degrees;
If variable node neither needs expansion, needing in the basic check matrix of high code check quasi-cyclic LDPC code not participate in the verification of the check row that decomposes yet, continue to judge other variable node;
Each variable node is all made above-mentioned judgement and corresponding operating, up to having judged all information bit corresponding variable node.
According to the code-rate-compatible quasi-cyclic LDPC code of the inventive method structure, the HARQ scheme based on above-mentioned code-rate-compatible quasi-cyclic LDPC code is proposed further on this basis.
The formula of the original position of the calculating that proposes in embodiment of the invention check bit to be sent in the check bit of low code check quasi-cyclic LDPC code code word is as follows,
F
k＝(SPID
k*L
k)mod(ParityLen)(1)
SPID wherein
kExpression bag indicated value (SPID
kValue be 0,1,2 or 3), L
kThe check bit number that expression sends, ParityLen are represented the total number of check bit in the low code check quasi-cyclic LDPC code code word, and k represents number of retransmissions.
The formula that calculates each check bit to be sent particular location in the check bit in low code check quasi-cyclic LDPC code code word is as follows,
S
k，i＝(F
k+i)mod(ParityLen)，i＝0，1，L?L
k-1(2)
S wherein
K, iRepresent the particular location of each check bit to be sent in the check bit of low code check quasi-cyclic LDPC code code word.Equally, at receiving terminal, calculate the particular location of each received check bit in the check bit of low code check quasi-cyclic LDPC code code word with said method.
As can be seen, can under the position prerequisite of disobeying the check bit that sends before relying, calculate the particular location of each check bit in the check bit of low code check quasi-cyclic LDPC code code word of current transmission according to above-mentioned formula receiving terminal.
Concrete design is consulted Fig. 8, the HARQ flow chart of embodiment of the invention design,
S801 determines check bit to be sent original position in the check bit of low code check quasi-cyclic LDPC code code word and the particular location of each check bit in the check bit of low code check quasi-cyclic LDPC code code word to be sent.
When sending first, SPID
K=0=0 (k=0 represents to send first), check bit number according to the need transmission, determine check bit to be sent original position in the check bit of low code check quasi-cyclic LDPC code code word by formula (1), further determine the particular location of each check bit to be sent in the check bit of low code check quasi-cyclic LDPC code code word by formula (2) then.Information bit and the check bit of determining according to above-mentioned formula are formed packet, send described packet then, HARQ transmit beginning, writes down and once sends number of times, and promptly this sends k=1 behind the described packet.
S802, receiving terminal is deciphered, and judges whether decoding is correct, if the receiving terminal correct decoding, to transmitting terminal feeding back ACK (affirmation) signal, then transmitting terminal is carried out S803, receives described ack signal; Otherwise to transmitting terminal feedback NACK (unconfirmed) signal, then transmitting terminal is carried out S804, receives described NACK signal.
Transmitting terminal is carried out S806 after receiving ack signal, and transmitting terminal sends other new code word bits, this HARQ end of transmission; Carry out S605 after receiving the NACK signal, judge whether to reach maximum retransmission.
If reach maximum retransmission, then carry out the S806 transmitting terminal and send other new code word bits, this HARQ end of transmission.
If do not reach maximum retransmission, then carry out S607, according to SPID
kAnd L
kValue, determine check bit to be sent original position by formula (1) in low code check quasi-cyclic LDPC code code word, further determine the particular location of each check bit to be sent in the check bit of low code check quasi-cyclic LDPC code code word by formula (2) then, send the packet that corresponding bit is formed, retransmit, every re-transmission once back adds 1 to the k value.
When the corresponding packet of transmission retransmits, three kinds of schemes are arranged.Scheme one is when retransmitting, and retransmission data packet may is identical with the content of the packet of transmission first, and check bit wherein to be sent can pass through formula (1) (SPID wherein
k=0, L
k=L
0) determine, send this packet, each re-transmission all send information bit with send identical check bit first.Scheme two when retransmitting according to SPID
kAnd L
kValue, calculate check bit to be sent at the original position of low code check quasi-cyclic LDPC code code word and the particular location of each check bit in the check bit of low code check quasi-cyclic LDPC code code word to be sent by formula (1) and formula (2), form packet by check bit to be sent then, send this packet, only send selected check bit at every turn when retransmitting.Scheme three when retransmitting according to SPID
kAnd L
kValue, calculate check bit to be sent at the original position of low code check quasi-cyclic LDPC code code word and the particular location of each check bit in the check bit of low code check quasi-cyclic LDPC code code word to be sent by formula (1) and formula (2), information bit and check bit to be sent are formed packet then, send this packet, not only send selected check bit during each the re-transmission, and send information bit.
At receiving terminal, the method for its reception is:
The packet that receiving end/sending end sends, described data comprise the information of information bit and check bit, verification bit number L in the described data that receive that provide according to system control information
kValue and SPID
kValue, calculate in the received packet corresponding to the particular location of each data in the check bit of whole low code check quasi-cyclic LDPC code code word of each check bit.When receiving first the current packet that receives is deciphered, non-ly current packet that receives and the packet that receives are before merged when receiving first, be combined into a code word and decipher.Correctness according to decoding feeds back response message to transmitting terminal.If correct decoding is to transmitting terminal feeding back ACK signal; If do not have correct decoding then to transmitting terminal feedback NACK signal.
In order to implement top method, the embodiment of the invention also provides relevant apparatus so that realize said method.
As shown in Figure 9, the embodiment of the invention provides a kind of LDPC code coder 900, and described encoder 900 comprises:
Test matrix generation unit 902 is used to design the check matrix of code-rate-compatible LDPC codes, and the check part structure of the binary radix check matrix of accurate circulation low code rate LDPC code as shown in Figure 5.Wherein, the number of degrees of first check bit correspondence are 4, h
b(0)=1, h
b(m
b'-1)=1, h
b(k)=1,0＜k＜(m
b'-1), m
b'＞m
b, m
bThe high code check quasi-cyclic LDPC code of ' expression is through decomposing back corresponding check interstitial content, the number of degrees span of the check bit correspondence that remaining high code check quasi-cyclic LDPC code corresponding check bit and decomposition method produce is 2≤i≤3, i represents the number of degrees value of check bit correspondence, and the number of degrees of the check bit correspondence that produces by extended method are 1.
As shown in figure 10, the embodiment of the invention also provides a kind of generating apparatus 1000 of quasi-cyclic LDPC code, and described generating apparatus comprises:
Degree distribution determining unit 1002, degree distribution situation based on high code check quasi-cyclic LDPC code, the degree of the low code check quasi-cyclic LDPC code of design distributes, and the check part of the biradical check matrix of described high code check quasi-cyclic LDPC code has the biconjugate corner structure, and the degree of first check digit is 3; Instantiation as shown in Figure 4, h wherein
b(0)=1, h
b(m
b-1)=1, h
b(k)=1,0＜k＜(m
b-1), m
bCheck-node number before expression is decomposed.
Computing unit 1004, be used for distributing and the degree of high code check quasi-cyclic LDPC code distributes variable node that need in the high code check quasi-cyclic LDPC code in the basic check matrix process of the low code check quasi-cyclic LDPC code of structure to determine the check-node that decomposes and needs to expand according to the degree of described low code check quasi-cyclic LDPC code;
Check matrix generation unit 1006, based on the restriction of building method and low code check quasi-cyclic LDPC code to biradical check matrix check part structure, the basic check matrix of the low code check quasi-cyclic LDPC code of structure, the check part structure of the biradical check matrix of low code check quasi-cyclic LDPC code as shown in Figure 5, wherein, the number of degrees of first check bit correspondence are 4, h
b(0)=1, h
b(m
b'-1)=1, h
b(k)=1,0＜k＜(m
b'-1), m
b'＞m
b, m
bThe high code check quasi-cyclic LDPC code of ' expression is through decomposing back corresponding check interstitial content, the number of degrees span of the check bit correspondence that remaining high code check quasi-cyclic LDPC code corresponding check bit and decomposition method produce is 2≤i≤3, i represents the number of degrees value of check bit correspondence, and the number of degrees of the check bit correspondence that produces by extended method are 1;
This check matrix generation unit 1006 also comprises an expansion module, and it is used for the basic check matrix of described quasi-cyclic LDPC code is expanded to by spreading factor the check matrix of low code check quasi-cyclic LDPC code.
Delete surplus operating unit 1012, be used for low code check quasi-cyclic LDPC code is deleted surplus operation and the different code check quasi-cyclic LDPC codes of acquisition system needs, obtain the quasi-cyclic LDPC code of code-rate-compatible.
In order to realize support to many code lengths demand, this generating apparatus also comprises a code length amending unit 1014, this code length amending unit is used for using the corresponding down spreading factor of different code length that the cyclic shift amount is revised to the basic check matrix of the described low code check quasi-cyclic LDPC code that constructs, and obtains the basic check matrix of correction.
As shown in figure 11, the embodiment of the invention also provides a kind of transmitting terminal device 1100.
This transmitting terminal device 1100 comprises:
F
k＝(SPID
k*L
k)mod(ParityLen)
Determine check bit to be sent original position in the check bit of low code check quasi-cyclic LDPC code code word, wherein SPID
kExpression bag indicated value (SPID
kValue be 0,1,2 or 3), L
kThe check bit number that expression sends, ParityLen are represented the total number of check bit in the low code check quasi-cyclic LDPC code code word, and k represents number of retransmissions, passes through formula
S
k，i＝(F
k+i)mod(ParityLen)，i＝0，1，L?L
k-1
Determine the particular location of each check bit to be sent in the check bit of low code check quasi-cyclic LDPC code code word;
Transmitting element 1104 is used to send the packet that the information bit connection is formed with the check bit of determining according to above-mentioned formula.
This device also comprises receiving element 1108, is used to receive the feedback information that sends from receiving terminal; And
Judging unit 1106, the type of the feedback information that is used to judge that receiving element 1108 is received.
The embodiment of the invention also provides a kind of receiving end device 1200 as shown in figure 12, cooperates above-mentioned transmitting terminal device 1100 work.Described receiving end device comprises:
F
k＝(SPID
k*L
k)mod(ParityLen)
Determine to receive the original position of check bit in the check bit of whole low code check quasi-cyclic LDPC code code word in the packet, wherein SPID
kExpression bag indicated value (SPID
kValue be 0,1,2 or 3), L
kThe check bit number that expression sends, ParityLen are represented the total number of check bit in the quasi-cyclic LDPC code code word of low code check, and k represents number of retransmissions, passes through formula
S
k，i＝(F
k+i)mod(ParityLen)，i＝0，1，L?L
k-1
Determine to receive in the packet the particular location of each data in the check bit of low code check quasi-cyclic LDPC code code word corresponding to check bit;
Feedback signal transmitting element 1210 is used for sending and feeds back signal to transmitting terminal, sends ack signal if decoding is correct, if decipher incorrect then send the NACK signal.
Utilize associating decomposition method and extended method to construct the code-rate-compatible quasi-cyclic LDPC code, when using this method to obtain low code check quasi-cyclic LDPC code, the number of degrees corresponding to the check-node of high code check quasi-cyclic LDPC code can reduce along with the reduction of code check by decomposition method, can increase along with the reduction of code check by extended method corresponding to the number of degrees of the variable node of high code check quasi-cyclic LDPC code; Simultaneously delete surplus mode with optimization,, and then generated the quasi-cyclic LDPC code of code-rate-compatible then by deleting the surplus quasi-cyclic LDPC code that obtains different code checks based on the check bit deinterleaving method.Proposed corresponding support HARQ scheme on the code-rate-compatible quasi-cyclic LDPC code basis that designs based on above method, transmitting-receiving two-end control expense is less, has improved the performance of whole system.
Claims (34)
1, a kind of method that generates quasi-cyclic low-density parity check sign indicating number is characterized in that, described method comprises:
The low code check of acquisition system requires and the degree of high code check quasi-cyclic low-density parity check sign indicating number distributes, and the degree of the low code check quasi-cyclic low-density parity check sign indicating number of design distributes;
Distribute and the degree of high code check quasi-cyclic low-density parity check sign indicating number distributes variable node that need in the high code check quasi-cyclic low-density parity check sign indicating number in the process of the low code check quasi-cyclic low-density parity check sign indicating number base check matrix of structure to determine the check-node that decomposes and needs to expand according to the degree of described low code check quasi-cyclic low-density parity check sign indicating number;
Based on the restriction of building method and low code check quasi-cyclic low-density parity check sign indicating number to biradical check matrix check part structure, the basic check matrix of the low code check quasi-cyclic low-density parity check sign indicating number of structure.
2, the method for claim 1 is characterized in that, the check part structure of the biradical check matrix of the basic check matrix of described low code check quasi-cyclic low-density parity check sign indicating number is:
Wherein, the number of degrees of first check bit correspondence are 4, h
b(0)=1, h
b(m
b'-1)=1, h
b(k)=1,0＜k＜(m
b'-1), m
b'＞m
b, m
bThe high code check quasi-cyclic low-density parity check sign indicating number of ' expression is through decomposing back corresponding check interstitial content, the number of degrees span of the check bit correspondence that remaining high code check quasi-cyclic low-density parity check sign indicating number corresponding check bit and decomposition method produce is 2≤i≤3, i represents the number of degrees value of check bit correspondence, and the number of degrees of the check bit correspondence that produces by extended method are 1.
3, method as claimed in claim 2, it is characterized in that, based on the restriction to biradical check matrix check part structure of building method and low code check quasi-cyclic low-density parity check sign indicating number, the basic check matrix of the low code check quasi-cyclic low-density parity check sign indicating number of structure is:
According to of the restriction of low code check quasi-cyclic low-density parity check sign indicating number to the check part structure of biradical check matrix, decompose and extended operation based on the variable node of the check-node that needs in building method and the high code check quasi-cyclic low-density parity check sign indicating number to decompose and the needs expansion basic check matrix to high code check quasi-cyclic low-density parity check sign indicating number, structure hangs down the basic check matrix of code check quasi-cyclic low-density parity check sign indicating number.
4, the method for claim 1 is characterized in that, the check part of the biradical check matrix of described high code check quasi-cyclic low-density parity check sign indicating number has the biconjugate corner structure, and the degree of first check bit correspondence is 3, and structure is:
H wherein
b(0)=1, h
b(m
b-1)=1, h
b(k)=1,0＜k＜(m
b-1), m
bCheck-node number before expression is decomposed.
5, the method for claim 1 is characterized in that, described method also comprises,
The basic check matrix of described quasi-cyclic low-density parity check sign indicating number is expanded to the check matrix of low code check quasi-cyclic low-density parity check sign indicating number by spreading factor.
6, the method for claim 1 is characterized in that, described method also comprises,
Basic check matrix to described low code check quasi-cyclic low-density parity check sign indicating number uses spreading factor that the cyclic shift amount is revised, and obtains the basic check matrix of revising;
Obtain the check matrix of the low code check quasi-cyclic low-density parity check sign indicating number under the required code length by the spreading factor expansion.
7, a kind of method that generates code-rate-compatible quasi-cyclic low-density parity check sign indicating number is characterized in that described method comprises:
The low code check of acquisition system requires and the degree of high code check quasi-cyclic low-density parity check sign indicating number distributes, and the degree of the low code check quasi-cyclic low-density parity check sign indicating number of design distributes;
Distribute and the degree of high code check quasi-cyclic low-density parity check sign indicating number distributes variable node that need in the high code check quasi-cyclic low-density parity check sign indicating number in the basic check matrix process of the low code check quasi-cyclic low-density parity check sign indicating number of structure to determine the check-node that decomposes and needs to expand according to the degree of described low code check quasi-cyclic low-density parity check sign indicating number;
Based on the restriction of building method and low code check quasi-cyclic low-density parity check sign indicating number to biradical check matrix check part structure, the basic check matrix of the low code check quasi-cyclic low-density parity check sign indicating number of structure;
Obtain low code check quasi-cyclic low-density parity check sign indicating number and delete surplus operation, obtain the quasi-cyclic low-density parity check sign indicating number of code-rate-compatible.
8, method as claimed in claim 7 is characterized in that, the check part structure of the biradical check matrix of the basic check matrix of described low code check quasi-cyclic low-density parity check sign indicating number is:
Wherein, the number of degrees of first check bit correspondence are 4, h
b(0)=1, h
b(m
b'-1)=1, h
b(k)=1,0＜k＜(m
b'-1), m
b'＞m
b, m
bThe high code check quasi-cyclic low-density parity check sign indicating number of ' expression is through decomposing back corresponding check interstitial content, the number of degrees span of the check bit correspondence that remaining high code check quasi-cyclic low-density parity check sign indicating number corresponding check bit and decomposition method produce is 2≤i≤3, i represents the number of degrees value of check bit correspondence, and the number of degrees of the check bit correspondence that produces by extended method are 1.
9, method as claimed in claim 7 is characterized in that, the check part of the biradical check matrix of described high code check quasi-cyclic low-density parity check sign indicating number has the biconjugate corner structure, and the degree of first check bit correspondence is 3, and structure is:
H wherein
b(0)=1, h
b(m
b-1)=1, h
b(k)=1,0＜k＜(m
b-1), m
bCheck-node number before expression is decomposed.
10, method as claimed in claim 7 is characterized in that, also comprise behind the basic check matrix of the low code check quasi-cyclic low-density parity check sign indicating number of described method construct,
The basic check matrix of described quasi-cyclic low-density parity check sign indicating number is expanded to the check matrix of low code check quasi-cyclic low-density parity check sign indicating number by spreading factor.
11, method as claimed in claim 10 is characterized in that, delete surplus operation and also comprise before,
Check bit to low code check quasi-cyclic low-density parity check sign indicating number carries out interlace operation.
12, method as claimed in claim 11 is characterized in that, to the check bit of low code check quasi-cyclic low-density parity check sign indicating number interweave for:
To high code check quasi-cyclic low-density parity check sign indicating number corresponding check bit with based on the check bit that decomposition method produces is that unit carries out piecemeal with the spreading factor;
The check block that generates is interweaved;
With information bit and the check bit that produces of the check block after interweaving and extended method be multiplexed into a low code check quasi-cyclic low-density parity check sign indicating number code word.
13, method as claimed in claim 8, it is characterized in that, based on the restriction to biradical check matrix check part structure of building method and low code check quasi-cyclic low-density parity check sign indicating number, the basic check matrix of the low code check quasi-cyclic low-density parity check sign indicating number of structure is:
According to of the restriction of low code check quasi-cyclic low-density parity check sign indicating number to the check part structure of biradical check matrix, decompose and extended operation based on the variable node of the check-node that needs in building method and the high code check quasi-cyclic low-density parity check sign indicating number to decompose and the needs expansion basic check matrix to high code check quasi-cyclic low-density parity check sign indicating number, structure hangs down the basic check matrix of code check quasi-cyclic low-density parity check sign indicating number.
14, method as claimed in claim 10, it is characterized in that, the check part of described low code check quasi-cyclic low-density parity check sign indicating number is made up of three parts, high code check quasi-cyclic low-density parity check sign indicating number corresponding check bit is based on the check bit of decomposition method generation and the check bit that produces based on extended method.
15, method as claimed in claim 7 is characterized in that, described method also comprises,
Basic check matrix to the described low code check quasi-cyclic low-density parity check sign indicating number that constructs uses spreading factor that the cyclic shift amount is revised, and obtains the basic check matrix of revising;
Obtain the check matrix of the low code check quasi-cyclic low-density parity check sign indicating number under the required code length by the spreading factor expansion.
16, a kind of quasi-cyclic low-density parity check code coder is characterized in that described encoder comprises:
The test matrix generation unit is used to design the check matrix of quasi-cyclic low-density parity check sign indicating number, and wherein the check part structure of the biradical check matrix of low code check quasi-cyclic low-density parity check sign indicating number is:
Wherein, the number of degrees of first check bit correspondence are 4, h
b(0)=1, h
b(m
b'-1)=1, h
b(k)=1,0＜k＜(m
b'-1), m
b'＞m
b, m
bThe high code check quasi-cyclic low-density parity check sign indicating number of ' expression is through decomposing back corresponding check interstitial content, the number of degrees span of the check bit correspondence that remaining high code check quasi-cyclic low-density parity check sign indicating number corresponding check bit and decomposition method produce is 2≤i≤3, i represents the number of degrees value of check bit correspondence, and the number of degrees of the check bit correspondence that produces by extended method are 1.
17, a kind of mixed automatic retransferring method based on code-rate-compatible quasi-cyclic low-density parity check sign indicating number is characterized in that described method is:
Determine check bit to be sent original position in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word and the particular location of check bit in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word to be sent, pass through formula
F
k＝(SPID
k*L
k)mod(ParityLen)(a)
Determine check bit to be sent original position in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word, wherein SPID
kExpression bag indicated value, L
kRepresent check bit number to be sent, ParityLen represents the total number of check bit in the low code check quasi-cyclic low-density parity check sign indicating number code word, and k represents number of retransmissions, passes through formula
S
k，i＝(F
k+i)mod(ParityLen)，i＝0，1，L?L
k-1(b)
Determine check bit to be sent particular location in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word;
Send the packet that the information bit connection is formed with the check bit of determining according to above-mentioned formula.
18, method as claimed in claim 17 is characterized in that described method also comprises:
Receiving feedback information;
If the feedback information that receives is a confirmation signal, continue to send new code word.
19, method as claimed in claim 17 is characterized in that, described method also comprises: "
Receiving feedback information;
If the feedback information that receives is a signal unconfirmed, then judge whether to reach maximum retransmission;
If reach maximum retransmission then continue to send new code word,
If do not reach maximum retransmission, determine that once more check bit to be sent at the original position of low code check quasi-cyclic low-density parity check sign indicating number code word and the particular location of check bit in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word to be sent, sends the packet that corresponding bit is formed.
20, method as claimed in claim 19, it is characterized in that, if the described maximum retransmission that do not reach, determine check bit to be sent once more at the original position of low code check quasi-cyclic low-density parity check sign indicating number code word and the particular location of check bit in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word to be sent, the packet that sends corresponding bit composition is:
Retransmission data packet may is identical with the content of the packet that sends first, and check bit wherein to be sent is by formula (a) (SPID wherein
k=0, L
k=L
0) determine, send this packet; Or
During re-transmission according to SPID
kAnd L
kValue, calculate check bit to be sent at the original position of low code check quasi-cyclic low-density parity check sign indicating number code word and the particular location of check bit in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word to be sent by formula (a) and formula (b), form packet by check bit to be sent then, send this packet; Or
During re-transmission according to SPID
kAnd L
kValue, the check bit that calculates transmission by formula (a) and formula (b) is at the original position of low code check quasi-cyclic low-density parity check sign indicating number code word and the particular location of check bit in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word to be sent, information bit and check bit composition packet to be sent send this packet then.
21, a kind of method of reseptance that mixing retransmits automatically based on code-rate-compatible quasi-cyclic low-density parity check sign indicating number is characterized in that described method comprises:
Determine to receive in the packet data corresponding to check bit in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word original position and corresponding to the particular location of data in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word of check bit, pass through formula
F
k＝(SPID
k*L
k)mod(ParityLen)
Determine to receive in the packet the original position of data in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word, wherein SPID corresponding to check bit
kExpression bag indicated value, L
kThe check bit number that expression sends, ParityLen are represented the total number of check bit in the low code check quasi-cyclic low-density parity check sign indicating number code word, and k represents number of retransmissions, passes through formula
S
k，i＝(F
k+i)mod(ParityLen)，i＝0，1，L?L
k-1
Determine to receive in the packet the particular location of data in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word corresponding to check bit;
The packet that receives is deciphered, if correct transmission of decoding confirmed feedback signal, if decipher incorrect then send signal unconfirmed.
22, method as claimed in claim 21 is characterized in that, if receive data the non-first time, then current packet that receives and the packet that receives is before merged, and is combined into a code word and deciphers.
23, a kind of generating apparatus of quasi-cyclic low-density parity check sign indicating number is characterized in that, described generating apparatus comprises:
Degree distribution determining unit, degree distribution situation based on high code check quasi-cyclic low-density parity check sign indicating number, the degree of the low code check quasi-cyclic low-density parity check sign indicating number of design distributes, and the check part of the biradical check matrix of described high code check quasi-cyclic low-density parity check sign indicating number has the biconjugate corner structure;
Computing unit, be used for distributing and the degree of high code check quasi-cyclic low-density parity check sign indicating number distributes variable node that need in the high code check quasi-cyclic low-density parity check sign indicating number in the basic check matrix process of the low code check quasi-cyclic low-density parity check sign indicating number of structure to determine the check-node that decomposes and needs to expand according to the degree of described low code check quasi-cyclic low-density parity check sign indicating number;
The check matrix generation unit, based on the restriction of building method and low code check quasi-cyclic low-density parity check sign indicating number to biradical check matrix check part structure, the check matrix of the low code check quasi-cyclic low-density parity check sign indicating number of structure.
24, generating apparatus as claimed in claim 23 is characterized in that, described generating apparatus also comprises:
Coding unit is used for encoding based on described low code check quasi-cyclic low-density parity check code check matrix, obtains low code check quasi-cyclic low-density parity check sign indicating number.
25, generating apparatus as claimed in claim 23 is characterized in that, the check part structure of the biradical check matrix of the basic check matrix of the low code check quasi-cyclic low-density parity check sign indicating number of described check matrix generation unit structure is:
Wherein, the number of degrees of first check bit correspondence are 4, h
b(0)=1, h
b(m
b'-1)=1, h
b(k)=1,0＜k＜(m
b'-1), m
b'＞m
b, m
bThe high code check quasi-cyclic low-density parity check sign indicating number of ' expression is through decomposing back corresponding check interstitial content, the number of degrees span of the check bit correspondence that remaining high code check quasi-cyclic low-density parity check sign indicating number corresponding check bit and decomposition method produce is 2≤i≤3, i represents the number of degrees value of check bit correspondence, and the number of degrees of the check bit correspondence that produces by extended method are 1.
26, a kind of generating apparatus of code-rate-compatible quasi-cyclic low-density parity check sign indicating number is characterized in that described generating apparatus comprises:
Degree distribution determining unit, degree distribution situation based on high code check quasi-cyclic low-density parity check sign indicating number, the degree of the low code check quasi-cyclic low-density parity check sign indicating number of design distributes, and the check part of the biradical check matrix of described high code check quasi-cyclic low-density parity check sign indicating number has the biconjugate corner structure;
Computing unit, be used for distributing and the degree of high code check quasi-cyclic low-density parity check sign indicating number distributes according to the degree of described low code check quasi-cyclic low-density parity check sign indicating number, determine the low code check quasi-cyclic low-density parity check sign indicating number of structure basic check matrix process in need in the high code check quasi-cyclic low-density parity check sign indicating number check-node that decomposes and needs to expand variable node;
The check matrix generation unit, based on the restriction of building method and low code check quasi-cyclic low-density parity check sign indicating number to biradical check matrix check part structure, the basic check matrix of the low code check quasi-cyclic low-density parity check sign indicating number of structure;
Coding unit is used for encoding based on described low code check quasi-cyclic low-density parity check code check matrix, obtains low code check quasi-cyclic low-density parity check sign indicating number;
Delete surplus operating unit, be used for low code check quasi-cyclic low-density parity check sign indicating number is deleted surplus operation and the different code check quasi-cyclic low-density parity check sign indicating numbers of acquisition system needs, thereby obtain the quasi-cyclic low-density parity check sign indicating number of code-rate-compatible.
27, generating apparatus as claimed in claim 26 is characterized in that, described encoder also comprises:
Interleave unit is used for interweaving for the check bit of the low code check quasi-cyclic low-density parity check sign indicating number that obtains based on said method.
28, generating apparatus as claimed in claim 26 is characterized in that, described generating apparatus also comprises:
Code length amending unit, this code length amending unit are used for using spreading factor that the cyclic shift amount is revised to the basic check matrix of the described low code check quasi-cyclic low-density parity check sign indicating number that constructs.
29, generating apparatus as claimed in claim 26 is characterized in that, described check matrix generation unit also comprises,
Expansion module, it is used for the basic check matrix of described quasi-cyclic low-density parity check sign indicating number is expanded to by spreading factor the check matrix of low code check quasi-cyclic low-density parity check sign indicating number.
30, a kind of transmitting terminal device is characterized in that, described transmitting terminal device comprises:
Position calculation unit, it is used to pass through formula
F
k＝(SPID
k*L
k)mod(ParityLen)100
Determine check bit to be sent original position in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word, wherein SPID
kExpression bag indicated value, L
kRepresent check bit number to be sent, ParityLen represents the total number of check bit in the low code check quasi-cyclic low-density parity check sign indicating number code word, and k represents number of retransmissions, passes through formula
S
k，i＝(F
k+i)mod(ParityLen)，i＝0，1，L?L
k-1
Determine check bit to be sent particular location in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word;
Transmitting element is used to the packet that sends information bit and form according to the check bit that above-mentioned formula is determined.
31, device as claimed in claim 30 is characterized in that, this device also comprises:
Receiving element is used to receive the feedback information that sends from receiving terminal.
32, device as claimed in claim 31 is characterized in that, this device also comprises:
Judging unit, the type of the feedback information that is used to judge that receiving element receives.
33, a kind of receiving end device is characterized in that, described device comprises:
The packet receiving element is used to accept the packet from transmitting terminal;
Computing unit, it is used to pass through formula
F
k＝(SPID
k*L
k)mod(ParityLen)
Determine to receive in the packet the original position of data in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word, wherein SPID corresponding to check bit
kExpression bag indicated value, L
kThe check bit number that expression sends, ParityLen are represented the total number of check bit in the quasi-cyclic low-density parity check sign indicating number code word of low code check, and k represents number of retransmissions, passes through formula
S
k，i＝(F
k+i)mod(ParityLen)，i＝0，1，L?L
k-1
Determine to receive in the packet the particular location of data in the check bit of low code check quasi-cyclic low-density parity check sign indicating number code word corresponding to check bit;
Decoding unit is used for the packet that receives is deciphered;
The feedback signal transmitting element is used for sending and feeds back signal to transmitting terminal, if correct transmission of decoding confirmed feedback signal, if decipher incorrect then send signal unconfirmed.
34, device as claimed in claim 33 is characterized in that, this device also comprises:
Merge cells is used for current packet that receives and the packet that receives are before merged, and is combined into a code word and deciphers.
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| CN102075196A (en) * | 2010-12-10 | 2011-05-25 | 清华大学 | Multi-code rate multi-code length QC-LDPC code construction method and coding modulation system |
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| CN108988869A (en) * | 2017-05-31 | 2018-12-11 | 电信科学技术研究院 | A kind of method and device, the computer storage medium of determining check matrix |
| CN109155635A (en) * | 2016-06-14 | 2019-01-04 | 华为技术有限公司 | A kind of method, transmitting terminal and the receiving end of signal transmission |
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| CN102075196A (en) * | 2010-12-10 | 2011-05-25 | 清华大学 | Multi-code rate multi-code length QC-LDPC code construction method and coding modulation system |
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| CN101572554B (en) | 2013-04-24 |
| CN102651652B (en) | 2015-07-29 |
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