CN109155282A - 用于半导体器件的集成电阻器 - Google Patents
用于半导体器件的集成电阻器 Download PDFInfo
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- CN109155282A CN109155282A CN201680085885.7A CN201680085885A CN109155282A CN 109155282 A CN109155282 A CN 109155282A CN 201680085885 A CN201680085885 A CN 201680085885A CN 109155282 A CN109155282 A CN 109155282A
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- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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Abstract
一种异质结构半导体器件包括:第一有源区和第二有源区,每个有源区彼此电隔离,并且每个有源区包括第一有源层和第二有源层,其中一个电荷被布置在第一有源层和第二有源层之间。一个功率晶体管被形成在所述第一有源区中,并且一个集成栅极电阻器被形成在所述第二有源区中。一个栅极阵列在所述功率晶体管的第一有源区之上横向延伸。第一欧姆触点和第二欧姆触点分别被布置在所述集成栅极电阻器的第一横向端和第二横向端处,所述第一欧姆触点和所述第二欧姆触点被电连接到所述第二有源层的第二部分,所述第二欧姆触点还被电连接到所述栅极阵列。一个栅极总线被电连接到所述第一欧姆触点。
Description
技术领域
本公开内容涉及半导体器件和用于制造半导体器件的工艺;更具体地,涉及与开关模式功率转换器一起使用的半导体器件以及其制造方法。
背景技术
电子器件使用电力来运行。开关模式功率转换器由于其高效率、小尺寸和低重量而被广泛使用,以为当今许多电子设备供电。常规的壁式插座提供高压交流电(ac)。在开关模式功率转换器中,通过能量传递元件转换高压交流电以提供良好调节的直流(dc)输出。开关模式功率转换器包括控制器,该控制器通过感测表示一个或多个输出量的一个或多个输入并且在闭环中控制输出来提供输出调节。在运行中,利用功率开关来通过使占空比(通常是功率开关的接通时间与总开关周期的比率)变化、使开关频率变化或使开关模式功率转换器中的功率开关的每单位时间的脉冲数目变化来提供期望的输出。
集成电路通常被形成在晶片(wafer,圆片)上。该晶片然后被分离成含有集成电路的一个副本的个体管芯(die)。控制器和功率开关可以被集成在同一个管芯中,或可以在两个单独的管芯中。
附图说明
下面参考以下附图对本发明的非限制性和非穷举性的实施方案进行描述,其中贯穿各个视图,相同的附图标记指代相同的部分,除非另有说明。
图1A是具有集成电阻器的半导体器件的示例示意图。
图1B是图1A中示出的具有集成电阻器的半导体器件的示例布局的顶层视图。
图2A是沿着切割线A-A’取得的图1B的具有集成电阻器的半导体器件的横断面视图。
图2B是用于利用台面蚀刻进行隔离来制造图2A的具有集成电阻器的半导体器件的示例工艺流程。
图3A是沿着切割线A-A’取得的图1B的具有集成电阻器的半导体器件的另一个实施例的横断面视图。
图3B是用于利用离子注入进行隔离来制造图3A的具有集成电阻器的半导体器件的示例工艺流程。
图4A是具有集成电阻器的半导体器件的另一个示例示意图。
图4B是沿着图1B的示例布局的切割线A-A’取得的图4A的具有集成电阻器的半导体器件的横断面视图。
图5是沿着图1B的示例布局的切割线B-B’取得的图4A的具有集成电阻器的半导体器件的横断面视图。
贯穿附图的这些若干视图,对应的参考字符指示对应的部件。本领域技术人员将理解,图中的元件是为了简化和清楚而例示的,并且不一定按比例绘制。例如,图中的一些元件的尺寸可能相对于其他元件被夸大,以帮助增进对所公开的器件的各实施方案的理解。此外,常常没有描绘在商业上可行的实施方案中有用或必要的普通但公知的元件,以便于较少受妨碍地查看所公开的这些各实施方案。
具体实施方式
在下面的描述中,阐述了许多具体细节以提供对本发明的透彻理解。然而,本领域普通技术人员将明了,不需要采用所述具体细节来实施本发明。在其他情况下,没有详细描述众所周知的材料或方法,以避免模糊本发明。
贯穿本说明书提及“一个实施方案”,“一实施方案”,“一个实施例”或“一实施例”意味着,结合该实施方案或实施例描述的具体特征、结构或特性被包括在本发明的至少一个实施方案中。因此,贯穿本说明书在多个地方出现的短语“在一个实施方案中”、“在一实施方案中”、“一个实施例”或“一实施例”不一定都指代相同的实施方案或实施例。此外,具体特征、结构或特性可以在一个或多个实施方案或实施例中以任何合适的组合和/或子组合进行组合。具体特征、结构或特性可以被包括在集成电路、电子电路、组合逻辑电路或提供所描述的功能的其他合适的部件中。另外,应理解,随此提供的图用于向本领域普通技术人员进行解释的目的,并且附图不一定按比例绘制。
出于本公开内容的目的,“接地”或“地电位”是指如下参考电压或电位:对照所述参考电压或电位来定义或测量电子电路或集成电路(IC)的所有其他电压或电位。
如本文所使用的,“晶片”是在半导体器件和集成电路的制造中使用的晶体材料的薄片,所述晶体材料诸如硅、蓝宝石、碳化硅、氮化镓等晶体材料。
在本申请的上下文中,当晶体管处于“关断状态”或“关断”时,该晶体管大体上不传导电流。相反,当晶体管处于“接通状态”或“接通”时,该晶体管能够显著传导电流。举例来说,功率晶体管可以包括N沟道金属氧化物半导体场效应晶体管(NMOS),其中高电压被支撑在第一端子即漏极和第二端子即源极之间。功率MOSFET可以包括功率开关,该功率开关由集成控制器电路驱动以调节提供给负载的能量。
在一个实施方案中,功率晶体管包括异质结场效应晶体管(HFET),异质结场效应晶体管也被称为高电子迁移率晶体管(HEMT)。HFET基于III-V直接过渡半导体材料,诸如砷化铝铟镓(AlInGaAs)化合物材料或氮化铝铟镓(AlInGaN)化合物材料。功率MOSFET基于Si和其他宽带隙半导体材料,诸如碳化硅(SiC)。HFET和基于SiC的功率MOSFET均由于其优于硅基器件的优异物理性质而被有利地用在某些电子器件中。例如,GaN和AlGaN/GaN晶体管通常用于高速开关应用和高功率应用(例如,200-600V以及以上),诸如用于功率开关和功率转换器,这是由于由基于GaN的材料和器件结构提供的高电子迁移率、高击穿电压以及高饱和电子速度特性。由于HFET的物理性质,HFET可以比在相同电压下传导相同电流的其他半导体开关显著更快地改变状态,并且宽带隙可以改善HFET在升高温度下的性能。
根据本发明的实施方案,公开了基于氮化物的HFET器件结构以及其制造方法,其包括HFET器件芯片(chip)中的单片集成栅极电阻器。在一个实施方案中,与标准HFET器件布局相比,集成器件电阻器不需要管芯上的任何附加面积。在另一个实施方案中,控制栅极电阻值以对氮化物HFET开关速度进行动态控制,特别是在高频运行时。
用于功率转换器的控制器和功率开关可以一起集成在同一个集成电路管芯中,或可以被分成不同的集成电路管芯。晶体管,诸如金属氧化物半导体场效应晶体管(MOSFET)、异质结场效应晶体管(HFET)、高电子迁移率晶体管(HEMT)、绝缘栅双极晶体管(IGBT)、双极结型晶体管(BJT)、注入增强型栅极晶体管(IEGT)和门极可关断晶闸管(GTO),可以被用作功率开关。另外,功率开关可以基于硅(Si)、氮化镓(GaN)或碳化硅(SiC)半导体。晶体管通常具有第一端子和第二端子以及控制第一端子和第二端子之间的电流的控制端子。对于MOSFET或HFET,控制端子可以被称为栅极端子,而第一端子和第二端子分别是漏极端子和源极端子。
对于功率开关的集成电路,多个个体晶体管可以被并联连接在一起以用作单个功率晶体管。每个晶体管可以具有栅极指状物、源极指状物和漏极指状物,栅极指状物、源极指状物和漏极指状物然后被用来将个体晶体管耦合在一起。例如,栅极指状物可以耦合在一起作为栅极场板和栅极总线。然后该栅极总线被耦合到焊盘,该焊盘是晶体管的栅极端子。可以有利地利用栅极电阻器来抑制由基于氮化物的HFET的低栅极电荷、栅极电容和极快的开关速度引起的振荡。
在示例实施方案中,栅极电阻被集成在用作功率开关的GaN HFET中。多个栅极指状物被耦合在一起以形成控制多个晶体管指状物(源极-漏极对)的栅极电极阵列。不是将栅极电极阵列和栅极总线形成在一起,而是将栅极阵列和栅极总线分开。在一个实施例中,栅极电阻器被定位在栅极阵列和栅极总线之间。特别地,栅极电阻器被布置在栅极总线和栅极阵列的下面,以便与HFET一起集成在同一个集成电路管芯上,而不使用附加面积。
图1A例示了具有集成栅极电阻104的半导体器件100的示例示意图。如示出的,半导体器件100包括晶体管102和栅极电阻器104。半导体器件100还包括漏极端子106、源极端子108和栅极端子110。漏极端子106被耦合到晶体管102的漏极,而源极端子108被耦合到晶体管102的源极。栅极端子110通过栅极电阻器104耦合到晶体管102的栅极。换句话说,栅极电阻器104被耦合在栅极端子110和晶体管102的栅极之间。如示出的,晶体管102是n型晶体管,然而应理解,晶体管102也可以被实现为p型晶体管。此外,在一个实施方案中,晶体管102是GaN HFET,然而,其他晶体管类型可以受益于本公开内容的教导。
图1B示出了具有集成栅极电阻器104的半导体器件100的示例布局的顶层视图101。晶体管102的有源区和栅极电阻器104的有源区由相应的断面线阴影区域表示。应理解,晶体管102可以包括耦合在一起以形成晶体管102的许多晶体管。栅极阵列116被示出为具有布置在晶体管102上面的多个细长的构件或指状物。每个指状物在第一横向方向上延伸。所有指状物通过布置在栅极电阻器104上面的栅极金属的一部分彼此连接。栅极金属的连接部分在大体上垂直于所述第一横向方向的第二横向方向上延伸。多个通路欧姆触点118将栅极金属电连接到电阻器104的一端(上端)。栅极指状物可以耦合到晶体管102的个体晶体管的每个栅极。包括栅极阵列116的栅极金属也可以被用作栅极场板。电阻器104的另一端(底端)通过通路欧姆触点114与栅极总线112电连接。在完全制造的半导体器件中,栅极总线112被耦合到半导体器件100的栅极端子110。
本领域的实践者将理解,因为栅极电阻器104主要位于栅极总线112下方,所以具有图1B中示出的集成栅极电阻器的器件布局与常规晶体管布局相比不需要附加的管芯面积(也称为“基板面(real estate,有效面积)”)。
如示出的,栅极电阻器104具有一个有源区,该有源区的特征在于在第一横向方向上的宽度Y 122和在第二横向方向上的长度X 120。在一个实施例中,栅极电阻器104的电阻可以是以欧姆-平方为单位测量的薄层电阻。该电阻大体上是材料的电阻率乘以长度X 120除以宽度Y 122。在一个实施例中,宽度Y 122可以被选择为大体上等于晶体管102的宽度,而长度X 120可以被选择以达到目标电阻值。
图2A例示了沿着切割线A-A’取得的图1B的具有集成电阻器204的半导体器件200的横断面视图,该切割线大体上沿着半导体器件200的第一横向方向。此外,图2A的横断面视图例示了已经利用台面蚀刻来制造半导体器件200且特别是将栅极电阻器204与功率晶体管202隔离时的半导体器件200。
如图2A中示出的,衬底220可以被布置在半导体器件200的底部,例如,晶片的底部。衬底220可以包括蓝宝石(Al2O3)、硅(Si)、氮化镓(GaN)、砷化镓(GaAs)、碳化硅(SiC)或其他合适的衬底材料。第一有源层222被布置在衬底220上面,并且可以包括GaN、氮化铟(InN)、氮化铝(AlN)、氮化铝镓(AlGaN)、氮化铟镓(InGaN)或氮化铝铟镓(AlInGaN)。在其他实施例中,第一有源层222可以包括含有氮化物化合物或其他III族或III-IV族半导体材料元素的不同的半导体材料。
在一个实施例中,第一有源层222可以在1-10微米厚的范围内。在另一个实施例中,第一有源层222可以在2-6微米厚的范围内。可以在衬底220上生长或以其他方式形成第一有源层222。为了避免因晶格失配和/或热膨胀系数差异的可能问题,可以在衬底220和第一有源层222之间布置一个或多个附加层。例如,可以在衬底220和第一有源层222之间形成可选的薄成核层。
继续图2A的实施例,第二有源层224被布置在第一有源层222上面。第二有源层224可以包括AlGaN、氮化铝铟(AlInN)、砷化铟(InAs)、砷化铝(AlAs)、砷化铟镓(InGaAs,铟镓砷)、砷化铝镓(AlGaAs)或砷化铟铝镓(InAlGaAs)。在其他实施例中,第二有源层224可以包括不同的III族或III-V族半导体材料。
在一个实施例中,第二有源层224可以在10-40纳米(nm)厚的范围内。对于AlGaN第二有源层224的实施例,第二有源层224可以是15-30%的氮化铝对镓。此外,第二有源层224的材料可以是非化学计量的化合物。在这样的材料中,元素的比率不容易用普通整数表示。例如,第二有源层224可以是III族或III-V族氮化物半导体材料的非化学计量化合物,例如AlxGa1-xN,其中0<X<1。可以在第一有源层222上生长或沉积第二有源层224。
在图2A中还示出了电荷层226,该电荷层可以形成在第一有源层222和第二有源层224之间,这是由于这两个层之间的带隙差异、自发和/或压电极化不连续性或第一有源层222和/或第二有源层224的有意掺杂。电荷层226限定横向导电沟道,该横向导电沟道有时被称为二维电子气(2DEG)层,因为被捕获在由第一有源层222和第二有源层224之间的带隙差异造成的量子阱中的电子在两个横向维度上能自由移动,但是在第三(竖直)维度上被紧紧地限制。此外,第一有源层222有时被称为沟道层,而第二有源层224有时被称为阻挡层或施主层。对于示出的实施例,栅极电阻器204包括形成在第一有源层222和第二有源层224之间的电荷层226。
图2A的实施例包括有空隙的区域(open region)或空隙232,该有空隙的区域或空隙将栅极电阻器204的有源区与GaN晶体管202的有源区分开。注意到,空隙232被形成为跨越第二有源层224的整个竖直厚度和第一有源层222的一部分。如示出的,空隙232将层222、224的一部分(最左边)以及包括栅极电阻器204的电荷层226,与层222、224的另一部分(最右边)以及包括GaN晶体管202的电荷层226分开。在一个示例制造工艺中,使用台面蚀刻形成空隙232。在其他实施方案中,可以使用众所周知的晶体管隔离方法形成空隙232。
图2A的横断面视图示出了布置在第二有源层224上的欧姆触点214&218。欧姆触点214提供至栅极总线212的电接触,而欧姆触点216提供至栅极阵列216的电接触。如示出的,欧姆触点214&218被布置成穿过栅极电介质层228以接触第二有源层224。欧姆触点214&218可以是金基材料或无金材料(诸如钛或铝)。在一个实施例中,在沉积栅极电介质层228之前形成欧姆触点214&218。在另一个实施例中,通过在栅极电介质层228中蚀刻开口随后进行金属沉积步骤和退火步骤来形成欧姆触点214&218。对于示出的实施例,欧姆触点214&218被布置在沿着第一横向方向示出的两个空隙232之间。
注意到,在每个空隙232中,栅极电介质层228被直接布置在第一有源层224上。栅极电介质层228可以包括适合于形成栅极绝缘体的各种材料,诸如氧化铝(Al2O3)、氧化锆(ZrO2)、氮化铝(AlN)、二氧化铪(HfO2)、二氧化硅(SiO2)、氮化硅(SiN、Si3N4)、氮化铝硅(AlSiN)、氮化碳(CN)、氮化硼(BN)或其他合适的栅极电介质材料。在另一个实施例中,栅极电介质层228可以包括有助于保留与第二有源层224的原子布置的基于氮化物的材料。虽然图2A例示了单个栅极电介质层,但是应理解,可以利用多个栅极电介质层。
栅极总线212被示出为布置在欧姆触点212和栅极电介质层228上面,而包括栅极阵列216的栅极金属被布置在欧姆触点218和栅极电介质层228上面。复合钝化层230被布置在栅极总线212和栅极阵列216上面。此外,复合钝化层230被布置在欧姆触点214和欧姆触点218之间的栅极电介质层228上面。复合钝化层230还填充每个空隙232。在一个实施例中,复合钝化层230可以包括构成完全制造的半导体器件200的多个电介质层、钝化层、场板材料和金属层。这些层中的一些可以用于电场分布。
在运行中,电荷层226中的电荷在欧姆触点214和218之间横向流动。这样,电流通过栅极电阻器204在栅极总线212和栅极阵列216之间流动。对于图2A中示出的实施例,栅极电阻器204的结构类似于GaN晶体管202的有源区结构。这样,可以利用相同的工艺流程将栅极电阻204集成在与GaN晶体管202相同的管芯中。
图2B是用于利用台面蚀刻来制造如图2A中示出的具有集成电阻器的半导体器件200的示例工艺流程201。在示出的实施例中,工艺201开始于块280,在该块中获得衬底。该衬底可以是硅、蓝宝石、SiC、独立GaN或其他合适的衬底材料。在块282处,在衬底上生长(或沉积)第一有源层和第二有源层。可以使用金属有机物化学气相沉积(MOCVD)或金属有机物气相外延(MOVPE)来生长或沉积该第一有源层和该第二有源层。在一个实施例中,第一有源层的厚度可以在1-10微米厚的范围内,而第二有源层可以在10-40nm厚的范围内。
在块284处,对该器件进行台面蚀刻以将栅极电阻与有源器件的其余部分隔离。可以使用电感耦合等离子体(ICP)蚀刻来完成台面蚀刻。在块286处,形成用于栅极总线和栅极阵列的欧姆触点。所述欧姆触点可以是金基欧姆触点或无金欧姆触点。对于金基欧姆触点,使用在850-1000摄氏度(℃)之间退火的金属堆形成欧姆触点。对于无金欧姆触点,通过凹部蚀刻第二有源层(诸如AlGaN)、沉积无金材料(诸如钛、铝或其他合适的材料)然后在450-600℃下退火来形成欧姆触点。
在块288处,沉积栅极电介质。可以使用等离子体增强化学气相沉积(PECVD)或原子层沉积(ALD)来沉积栅极电介质。在块290处,沉积并且图案化栅极金属(形成栅极总线和栅极阵列)。金属被沉积在一个层中,然后被图案化/被蚀刻成单独的部段。可以使用电子束溅射或物理气相沉积(PVD)来完成金属沉积。可以使用湿法化学蚀刻的ICP蚀刻来完成图案化/蚀刻。在块292处,形成器件200的另外的钝化层、电介质层、场板层、金属层和其他互连结构。这些可以包括栅极、源极和漏极连接的场板等。
图3A例示了沿着图1B的切割线A-A’取得的具有集成电阻器304的半导体器件300的横断面视图,该切割线大体上沿着半导体器件300的第一横向方向。此外,图3A的横断面视图例示了利用离子注入来制造半导体器件300时的半导体器件300。
应理解,类似命名和编号的元件如上文所描述的那样耦合和起作用。图3A中示出的器件300与图2A中示出的器件200共享许多类似之处,然而,代替将栅极电阻器304的有源区与GaN晶体管302的有源区电隔离的空隙,一对注入区域334用来将栅极电阻器304与GaN晶体管302分离。如示出的,第一有源区322被布置在衬底320的顶部,且第二有源层324被布置在第一有源层322的顶部。注入区域334被布置在第一有源层322和第二有源层324内,从第二有源层324的顶表面向下延伸到在2DEG电荷层326下方的第一有源层322中。换句话说,注入区域334延伸穿过第二有源层324的整个竖直厚度并且延伸到第一有源层322的上部部分中。注入区域334将层322、324的一部分(最左边)以及包括栅极电阻器304的电荷层326,与层322、324的一部分(最右边)以及包括GaN晶体管302的电子层326电隔离。在一个实施例中,注入区域334可以使用离子注入技术形成,并且包括注入的氩(Ar)、氮(N)或其他合适的元素。
如图3A中示出,欧姆触点314&318分别被布置在栅极电阻器304的相对端,其中每个欧姆触点邻近注入区域334中的一个布置。欧姆触点314&318被示出为沿着第一横向方向分开。欧姆触点314被栅极总线312覆盖并且被电连接到栅极总线312。类似地,欧姆触点318被栅极阵列316覆盖并且被电连接到栅极阵列316。栅极总线312和栅极阵列316二者都通过栅极电介质层328与下面的注入区域334和第二有源层324竖直分离并且绝缘。
图3B是用于利用离子注入来制造如图3A中示出的具有集成电阻器的半导体器件的示例工艺流程301。应理解,工艺301类似于工艺201。此外,工艺块380、382、386、388、390和392与如关于图2B所讨论的块280、282、286、288、290和292大体上相同。然而,工艺流程301不包括台面蚀刻隔离步骤(块284),而是包括用于离子注入以将栅极电阻器与晶体管器件的有源区隔离的块387。
在图3B的实施例中,在块386处形成欧姆触点,该步骤发生在块382之后,块382是生长/沉积第一有源层和第二有源层的步骤。在块387处,可以使用掩模和光致抗蚀剂以在对于器件300而言注入区域应在的位置处图案化开口,来实现Ar、N或其他合适的材料的离子注入。此外,欧姆触点可以被用来对准用于注入的掩膜。一旦完成离子注入,就沉积栅极电介质。(块388)在沉积栅极电介质之后,可以进行栅极金属沉积和图案化。(块390)在块392处,进行钝化和金属化(例如,场板金属、互连结构等)步骤以完成制造。应理解,可以改变步骤387、388和390的顺序,例如,可以在离子注入步骤之前执行栅极电介质沉积和钝化沉积。
图4A例示了具有集成电阻的半导体器件400的另一个示例示意图。对于示出的实施例,半导体器件400类似于图1A中示出的半导体器件100,然而,半导体器件400可以利用一个晶体管以具有可变的集成栅极电阻。如示出的,半导体器件400包括晶体管492和栅极电阻404。然而,栅极电阻404由一个晶体管(例如,JFET)例示。半导体器件400还包括漏极端子406、源极端子408和栅极端子410。漏极端子406被耦合到晶体管402的漏极,而源极端子408耦合到晶体管402的源极。栅极端子410通过栅极电阻404(即JFET)耦合到晶体管402的栅极。或者换句话说,栅极电阻404被耦合在栅极端子410和晶体管402的栅极之间。在示出的实施例中,晶体管402的栅极被耦合到栅极电阻404(被例示为晶体管)的漏极,并且栅极端子410被耦合到栅极电阻404的源极。器件400还包括电阻端子411。电阻器端子411被耦合到例示栅极电阻的晶体管404的栅极。响应于在电阻器端子411处接收的信号,栅极电阻/晶体管404的值可以变化。此外,半导体器件400可以具有与图1B类似的顶层视图,外加沿第一方向在欧姆触点118和112之间并且基本跨越第二方向的另一个欧姆触点(代表电阻器端子411)。
图4B例示了沿着如图1B中示出的切割线A-A’取得的具有集成栅极电阻器404的半导体器件400的横断面视图,其具有附加的欧姆触点411。应理解,类似命名和编号的元件如上文描述的那样耦合和起作用。此外,器件400的横断面被例示为具有将栅极电阻器404的有源区与GaN晶体管402的有源区横向分离的空隙432。应理解,代替空隙432,离子注入区域(如图3A中示出的)可以用来将栅极电阻器404与GaN晶体管402隔离。
图4B中示出的半导体器件400与图2A中示出的器件200共享许多类似之处,然而,器件400还包括附加的金属触点411,该附加的金属触点是隔离的触点。在示出的实施例中,金属触点411(代表电阻器控制端子)在栅极电阻器404之上被沉积在栅极电介质层428上。金属触点411被横向布置在欧姆触点414(被电连接到栅极总线412)和欧姆触点418(被电连接到栅极阵列416)之间。复合钝化层430被布置在栅极总线412、栅极阵列416和金属触点411上面。注意到,复合钝化层430填充空隙432。
本领域的实践者将理解,如所配置的,栅极电阻器404的电阻可以在施加到金属触点411的电压的控制下变化。也就是说,金属触点411充当场效应晶体管配置中的栅极,该栅极控制电荷层426中的电荷,电荷以电流的形式在欧姆触点414和416之间横向流动。电荷流动,并且因此电流,可以通过从外部电路施加到金属触点411的电压来控制。这样,在金属触点411处接收的信号可以控制在电荷层404中流动的电荷的量,并且这样可以使栅极电阻器404的电阻变化。
图5是具有集成电阻器的半导体器件500的横断面视图,该视图是沿着图1B的示例布局的切割线B-B’取得的。特别地,图5例示了包括图1A的功率晶体管102的晶体管之一的横断面。切割线B-B’是大体上沿着半导体器件500的第二横向方向取得的。应理解,图5共享如图2A、图3A和图4B中示出的类似特征。另外,类似命名和编号的元件如上文所描述的那样耦合和起作用。
如图5中示出的,衬底520被布置在半导体器件500的底部。衬底500可以包括蓝宝石(Al2O3)、硅(Si)、氮化镓(GaN)、砷化镓(GaAs)、碳化硅(SiC)或其他衬底材料。第一有源层522被布置在衬底520上面,并且可以包括GaN、氮化铟(InN)、氮化铝(AlN)、氮化铝镓(AlGaN)、氮化铟镓(InGaN)或氮化铝铟镓(AlInGaN)。在其他实施例中,第一有源层522可以包括含有氮化物化合物或其他III-IV族元素的不同的半导体材料。在一个实施例中,第一有源层522可以在1-10微米厚的范围内。在另一个实施例中,第一有源层可以在2-6微米厚的范围内。为了避免因晶格失配和/或热膨胀系数差异的可能问题,可以在衬底520和第一有源层522之间布置一个或多个附加层。例如,可以在衬底520和第一有源层522之间形成可选的薄成核层。
第二有源层524被布置在第一有源层522上面,并且可以包括AlGaN、氮化铝铟(AlInN)、砷化铟(InAs)、砷化铝(AlAs)、砷化铟镓(InGaAs)、砷化铝镓(AlGaAs)或砷化铟铝镓(InAlGaAs)。在其他实施例中,第二有源层524可以包括不同的III-IV族氮化物或砷化物半导体材料。在一个实施例中,第二有源层524可以在10-40纳米(nm)厚的范围内。对于示例AlGaN第二有源层524,第二有源层524可以是15-30%的氮化铝对氮化镓。此外,第二有源层524的材料可以是非化学计量化合物。在这样的材料中,元素的比率不容易用普通整数表示。例如,第二有源层524可以是III-IV族氮化物半导体材料的非化学计量化合物,例如AlxGa1-xN,其中0<X<1。
在图5中还示出了电荷层526,该电荷层被形成在第一有源层522和第二有源层524之间,这是由于这两个层之间的带隙差异、自发和/或压电极化不连续性或第一有源层522和/或第二有源层的有意掺杂。电荷层526限定了横向导电沟道,该横向导电沟道也被称为二维电子气(2DEG)层,因为被捕获在由第一有源层522和第二有源层524之间的带隙差异造成的量子阱中的电子在两个横向维度上能自由移动,但是在第三(竖直)维度上被紧紧地限制。
欧姆触点540&538被示出为布置在第二有源层524上。在一个实施方案中,欧姆触点540&528分别是图1A的晶体管102的源极触点和漏极触点。在图5中还示出了布置在第二有源层524的顶部的栅极电介质层528。栅极电介质层528可以包括适合于形成栅极绝缘体的各种材料,诸如氧化铝(Al2O3)、氧化锆(ZrO2)、氮化铝(AlN)、二氧化铪(HfO2)、二氧化硅(SiO2)、氮化硅(SiN、Si3N4)、氮化铝硅(AlSiN)、氮化碳(CN)、氮化硼(BN)或其他合适的栅极电介质材料。在另一个实施例中,栅极电介质层528可以是可以保留与第二有源层524的原子布置的基于氮化物的材料。虽然图5例示了单个栅极电介质层,但是应理解,也可以使用多个栅极电介质层。
在图5中,栅极触点516被示出为布置在栅极电介质层528上,其在一个实施例中是一个隔离的触点。在示出的实施例中,栅极触点516起图1A的晶体管102的栅极端子的作用。栅极触点516是栅极阵列的指状物构件之一。复合钝化层530被布置在触点516、538、540和栅极电介质层528中的每个上面并且覆盖触点516、538、540和栅极电介质层528中的每个。在一个实施例中,复合钝化层530可以包括构成半导体器件500的多个电介质层、钝化层、场板材料和金属层。这样的层的例子包括用于触点516、540和538的栅极、源极和漏极场板,或附加的钝化层。这些层中的一些可以用于电场分布。
在运行中,半导体器件500被配置为晶体管,其中电荷层526中的电荷以电流的形式在欧姆触点540和538之间横向流动。此电流也可以在外部耦合电路中流动。电荷流动,并且因此电流,可以通过从外部电路施加到栅极触点516的电压来控制。
本发明的例示的实施例的以上描述,包括摘要中所描述的内容,并非意在是穷举性的或是对所公开的精确形式的限制。虽然出于例示性目的在本文中描述了本发明的具体实施方案和实施例,但是在不脱离本发明的更宽泛的精神和范围的前提下,多种等同改型是可能的。实际上,应理解,出于解释目的提供了具体示例电压、电流、频率、功率范围值、时间等,并且根据本发明的教导在其他实施方案和实施例中也可以采用其他值。鉴于以上详细描述,可以对本发明的实施例做出这些改型。在随附的权利要求中使用的术语不应被解释为将本发明限制于说明书和权利要求书中公开的具体实施方案。相反,范围完全由随附的权利要求确定,所述权利要求应根据权利要求解释的既定原则来解释。因此,本说明书和附图被认为是例示性的而不是限制性的。
Claims (21)
1.一种异质结构半导体器件,包括:
第一有源层;
第二有源层,其被布置在所述第一有源层上,一个电荷层被布置在所述第一有源层和所述第二有源层之间;
一个功率晶体管,其具有第一有源区,所述第一有源区包括所述第一有源层的第一部分和所述第二有源层的第一部分,在运行中,电流流动通过所述电荷层的第一部分;
一个栅极阵列,其在所述功率晶体管的第一有源区之上横向延伸,所述栅极阵列起所述功率晶体管的栅极的作用;
一个栅极电阻器,其具有第二有源区,所述第二有源区包括所述第一有源层的第二部分、所述第二有源层的第二部分和所述电荷层的第二部分,所述第二有源区与所述第一有源区电隔离;
第一触点和第二触点,所述第一触点和所述第二触点分别被布置在所述栅极电阻器的第一横向端和第二横向端,所述第一触点和所述第二触点电连接到所述第二有源层的第二部分,所述第二触点还电连接到所述栅极阵列;以及
一个栅极总线,其电连接到所述第一触点。
2.根据权利要求1所述的异质结构半导体器件,其中所述栅极电阻器具有由所述第二有源区的长度和宽度限定的电阻值,所述长度在第一横向方向上延伸,并且所述宽度在大体上垂直于所述第一横向方向的第二横向方向上延伸。
3.根据权利要求2所述的异质结构半导体器件,其中所述第二有源区的长度大体上包括所述第一触点和所述第二触点之间在所述第一横向方向上的距离。
4.根据权利要求1所述的异质结构半导体器件,其中所述栅极阵列通过栅极电介质层与所述第二有源层的所述第一部分绝缘。
5.根据权利要求1所述的异质结构半导体器件,其中所述栅极阵列包括多个指状物,所述多个指状物中的每个在所述第一有源区之上在所述第一横向方向上延伸。
6.根据权利要求2所述的异质结构半导体器件,其中所述电阻值被确定为大体上抑制在所述功率晶体管中流动的电流的振荡。
7.根据权利要求1所述的异质结构半导体器件,其中所述第一有源层包括基于氮化物的半导体材料。
8.根据权利要求1所述的异质结构半导体器件,其中所述第一有源层选自由氮化镓(GaN)、氮化铟(InN)、氮化铝(AlN)、氮化铝镓(AlGaN)、氮化铟镓(InGaN)或氮化铝铟镓(AlInGaN)组成的组。
9.根据权利要求5所述的异质结构半导体器件,其中所述栅极阵列包括在所述第二横向方向上延伸的连接部分,所述多个指状物经由所述连接部分彼此连接。
10.根据权利要求9所述的异质结构半导体器件,其中所述连接部分在所述第二横向方向上具有大体上等于所述栅极电阻器的宽度的宽度。
11.根据权利要求1所述的异质结构半导体器件,其中所述第一有源层在竖直方向上具有在1-10微米厚的范围内的厚度。
12.根据权利要求1所述的异质结构半导体器件,其中所述第二有源层在竖直方向上具有在10-40纳米(nm)厚的范围内的厚度。
13.根据权利要求1所述的异质结构半导体器件,其中所述第一有源层和所述第二有源层限定一个空隙,所述空隙将所述第二有源区与所述第一有源区电隔离。
14.根据权利要求1所述的异质结构半导体器件,还包括一个注入区域,所述注入区域将所述第二有源区与所述第一有源区电隔离。
15.根据权利要求1所述的异质结构半导体器件,还包括一个布置在所述第二有源区上方的电阻器控制端子,施加到所述电阻器控制端子的信号控制所述栅极电阻器的电阻值。
16.根据权利要求1所述的异质结构半导体器件,其中所述电阻器控制端子包括一个布置在栅极电介质层上的附加的金属触点。
17.一种制造异质结构半导体器件的方法,包括:
在衬底上形成第一有源层;
在所述第一有源层上形成第二有源层,所述第一有源层和所述第二有源层具有不同的带隙,使得在它们之间形成电荷层;
限定第一有源区和第二有源区,所述第一有源区包括所述第一有源层的第一部分、所述第二有源层的第一部分和所述电荷层的第一部分,所述第二有源区包括所述第一有源层的第二部分、所述第二有源层的第二部分和所述电荷层的第二部分,所述第二有源区与所述第一有源区电隔离,其中所述第一有源区包括一个功率晶体管,并且所述第二有源区包括所述异质结构半导体器件的集成栅极电阻器;
直接在所述第二有源层的所述第二部分上形成第一触点和第二触点,所述第一触点和第二触点横向分开一距离,所述第一触点和所述第二触点分别包括所述集成栅极电阻器的第一端子和第二端子;以及
形成在所述功率晶体管的第一有源区之上横向延伸的栅极阵列,所述栅极阵列电连接到所述第二触点并且起所述功率晶体管的栅极的作用。
18.根据权利要求17所述的方法,其中形成所述栅极阵列包括:
形成在所述第二有源层的所述第一部分和第二部分之上延伸的栅极电介质层;
在所述栅极电介质层之上形成金属层;
将所述金属层图案化以限定所述栅极阵列。
19.根据权利要求18所述的方法,其中将所述金属层图案化还限定栅极总线,所述栅极总线电连接到所述第一欧姆触点。
20.根据权利要求17所述的方法,其中限定所述第一有源区和所述第二有源区包括:在所述第一有源区和所述第二有源区之间在所述第一有源层和所述第二有源层中蚀刻一个空隙。
21.根据权利要求17所述的方法,其中限定所述第一有源区和所述第二有源区包括:在所述第一有源区和所述第二有源区之间在一个半导体材料区域中注入离子。
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