CN1091535A - The method and apparatus that is used for the error correction code data transmission - Google Patents

Abstract

A kind of be used to discern and/or proofread and correct 1 and multi-bit according to the method and apparatus of word error.In order to optimize identification and correcting feature, reduce coding depth simultaneously as far as possible, promptly reduce the quantity of necessary gate level, the present invention's suggestion is divided into data word and check word the partial words of per 4 bit widths, check word is made of P check digit like this, and data word is made of d data bit.Be to produce check word and adopt a d*P generator matrix, the generation weighting Gs=d/4 of each column vector wherein, and the generation weighting Gz=P/4 of each row vector press one of maximum 2 bit affects of each data bit of line mode like this and checks partial words.

Description

The method and apparatus that is used for the error correction code data transmission

The present invention relates to a kind of be used to discern and/or proofread and correct 1 and multi-bit according to the method and apparatus of word, data word is wherein transmitted by data bus, and can read in memory assembly or write.

This method and apparatus belongs to the computer organization design, particularly belongs to primary memory structure field.

Because the development of advancing by leaps and bounds of software, make it become complicated and huge day by day, and the raising trend of session pulse repetition rate computing (Sprich Taktfrequenz-stellen) processing speed, to hardware and to improving constantly as the requirement of calculating and storing the computing machine of usefulness.Therefore the functional adjustment that has the processor of storer has great importance.

For optimization utilize its work efficiency, modern RISC processor needs bigger primary memory word wide.Sort memory generally is to adopt well-known DRAMs technology to realize, interrelate with so-called RISC processor, can with access time of the PRAMs of general length by strengthening wide being compensated of primary memory word.

Wide for the designed target word of the computing machine of the risc-based processor of up-to-date generation is that the primary memory word of 128 bits is wide.

The storer that is made of DRAMs has an error rate of determining that is called soft error (Soft-Errors).Along with the growth of memory span, the possibility that generally speaking is subject to the infringement of soft error also becomes big.Transmit enough reliabilities of data in order to guarantee, these data are that these data words have so-called identification or the correcting code (EDC/ECC) of makeing mistakes.

Can discern amiss bank bit thus to a certain extent and proofread and correct these data errors in some occasion of determining.But the continuing of the pulse repetition rate of the ever-increasing computing machine of having mentioned along with the front of efficient increases, and the problem that we face is, for the time that error correcting code is used fewer and feweri.

We can see and have had multiple error correction code approach from present data document, they are at the integrity problem that has taken into full account data aspect the calculating transmission undoubtedly, but these documents do not relate to for the simplification aspect that does not belong to the computer activity of data processing discussed here at all.

Therefore people develop the digital memory that has redundance that can write and repeat to read again, promptly be provided with check word, can realize error measuring by the parity checking or the error correcting of mode word, for example the SEC-DED code, single error is proofreaied and correct, according to two error detection occurs of breathing out plain code.For the situation that adopts the memory assembly that constitutes by word, the error measuring of such unit error recovery and two promptly two mistakes affirmations is far from being enough, this is that the inefficacy of certain single storage chip can cause a plurality of mistakes of every batch of canned data because in this memory function piece.This all words to storer utilize the algorithmic language general construction realize the what is called check of row formula parity checking and (Checksum) method be based on known coding method.This method depends on whom, promptly by how many data word bits constitute the horizontally-arranged codes and.This genealogical classification is determined by the efficient and the application of these methods.

It is not enough to have confirmed that in practicality this method exists, it or too simple so that do not possess enough work efficiencies, perhaps on processing time or storage time, consume big.

DE3716554C2 discloses a kind of method and apparatus by means of a standard check word of digital memory acquisition that can write and can read, and has wherein adopted a predetermined generator polynomial that produces memory content.This generator polynomial produces the check word of a reality from memory content when check, and should compare with the standard check word by actual check word.Exist the content in the storer to pass at present, they are superimposed with the new information that will deposit in by mould 2-computing, this result and factor X ^PMultiply each other, wherein P is illustrated in the position of the canned data that is occurred in the storer.Realize a surplus value mould g(x by this operation result), g(x here) be exactly so-called generator polynomial.The result who is generated is as the check word variable, with itself and old check word exclusive-OR.

In checking procedure, produce an interruption by a storage write operation, produce the corresponding memory access in this case in the memory block that can handle in checking procedure, this check word variable or be added on the actual check word perhaps is added on the standard check word like this.This checking procedure will be able to further execution according to write operation.

Compare with other existing methods, at first this disclosed method only needs less storage consumption in fault identification or correction, but requires the periodicity calculation process ability of computing machine significantly to strengthen.Therefore its shortcoming is, the optimization of this method only is embodied in the simplification of check word, rather than on the memory capacity.It does not consider following aspect, promptly when shortening computing time, considers effectively to utilize or make under the minimum condition of check digit, also can fully improve word wide utilize degree.Also have this danger under the working method of this external complicated operation, promptly check word structure itself is independent.

Last this method may cause loss of data, and the data of being lost can not be resumed again.

Each coding method that exists in the prior art proposes higher requirement to hardware, and this also is the factor that can not be ignored.

From known each method, particularly we discussed on the processing time in the acceptable method, the common issue with that we find be to hardware require too highly, consume big.Except hardware consumption, also exist the induction mistake to come source problem.

The maximum technological difficulties of judging hardware consumption from the coding method that realizes are coding depth.For generating code or coding method, aspect physics realization, need many gate levels (Gattereben), the result, coding or fault identification and correcting method have the most mainly caused hardware consumption.So we can say, existent method and equipment are always only realized optimizing with a kind of or other kind mode, that is to say or make and handle exclusive disjunction time minimum, perhaps make the data reliability maximum, and software or hardware consumption are minimized.Can only realize generally that by known method a kind of optimization improves, but the spinoff that also brings other simultaneously.

Also have at present a kind of improvement of configuration aspects, when storer became bigger and bigger, the integrated level of memory chip was also high more, and promptly memory chip is more and more littler and more and more intensive.The shortcoming of this architecture advances is, must carry out expensive check when making the sort memory element, and this has significantly improved the cost of these elements.That is to say, in many cases, when people produce large-scale memory component (＞4 megabit), can not carry out 100% error correction check.

But people find in practical application sort memory element, in data are passed on it are carried out the meaning that error check has particular importance.

Prentice Hall New Jersey 07632 in 1989, Englewood Cliffs publish by T.R.N.Rao, enumerated certain methods in the professional book that E.Fujiwara writes " mistake-control-code of the computer system " literary composition, their demanding data reliabilities, and since its numercal comprehensive complicated algorithm, obvious demanding software and hardware consumption.

In existent method, as broad as long or not significantly difference between the mistake of data word and the mistake of check word.This is because data word generally is to transmit as total data word with check word, so this have the shortcoming of the resolvability of mistake to be: identify extremely inaccurate as mistake.

Therefore from these prior arts, the purpose of this invention is to provide a kind of like this method and apparatus, it provides the partly possibility of error recovery when optimizing fault identification, optimized coding depth simultaneously, thereby can make necessary gate circuit progression realize minimizing.

Proposed invention purpose and method of the present invention are to adopt the feature of the characteristic of claim 1 to realize.The further integrity measure of this method is documented among the dependent claims 2-4.

Can adopt the feature of claim 5 characteristic according to the equipment of claim 5 preamble, to support purpose of the present invention.The further configuration of this equipment is described in remaining dependent claims.

Method of the present invention is used to optimize fault identification, adopts the deep layer code means simultaneously, changes sentence and says, with a kind of plain mode outside unexpected necessary gate level realization is minimized.Compare with existing classic method, reduced computing consumption, and quite reliable as desired by the data of the method transmission, and speed is faster.This is because the generation of check word is obtained by the whole circuit technology, that is to say, is to need not to adopt the arithmetic operation by software control to obtain by hardware.

For with the classification of the connotation of mistake, a good scheme of this method is by determining the weight of deviation testing word-comprehensive word (Syndromwort), the distinguishable mistake that goes out in the data bit from the mistake of check digit.

Having proved useful especially is to set total word length W=140 bit, data word length d=128 bit wherein, and check word length P=12 bit.When the message part word length was formed with 4 bits, then the message part number of words was 32.Check part number of words is 3, and wherein each check partial words is made up of 4 bits.Be of the generator matrix generation of the check word of a data word generation by a 128*12.Design is to produce by such method about the check word of data word for this, and when the parity checking of row mode, per 1 check bit is considered or produced 32 generation data bit.This that is to say, with other word, by each row in 12 row of 128*12 generator matrix only by 32 data bit constitute the horizontally-arranged code and, so respectively constitute 12 check digit.This situation is called " generating weighting Gs ".And total check word structure produces under the following conditions simultaneously, and the row formula selection of being undertaken by 128 data bit of promptly every generation 32 data bit is to distribute like this, and the generation weight Gz of each row vector is a data bit 3.That is to say that with other word each in 128 data bit in this embodiment respectively influences 3 check digit.In a mode that will be further described below, inspection of this check word itself or assurance are that the check digit relevant with this and data bit generates different.

Therefore generate with respect to the check word that is made of check digit, the check word generation that is made of data word is uneven.

The equipment aforementioned of the present invention of using method of the present invention has following advantage, and promptly data word mistake and the mistake in check word can be differentiated mutually.Thereby improved the quality that mistake is identified significantly.

Adopt equipment of the present invention to realize making coding depth to minimize.Physically necessary gate level is simplified greatly, and this equipment has higher mistake appraise quality, and has therefore improved arithmetic speed.

By disposing comprehensive evaluation unit, when determining a repairable mistake, filtered invalid check word, and made the word of having corrected enter application.This provides the possibility of simplifying this equipment in addition.Simplification to the integral device that adopts the inventive method is confirmed that by the following fact promptly for last mistake or the localization of identifying, the error correction unit of unit data position must only be considered 3 bits.These 3 bits be with by generator matrix by the row predefined with 3 serve as the generation weight mode corresponding to.

Content with reference to the accompanying drawings can more clearly understand method and apparatus of the present invention, further is illustrated below.Accompanying drawing is:

Fig. 1 a is the generator matrix sectional view of data bit 0-63, and this figure is used to represent the condition of this method.

Fig. 1 b is the generator matrix sectional view of the data bit 64-127 that continues as Fig. 1.

Fig. 1 c is the 128-139 position generator matrix figure that is used to produce the check word influence of monitoring check word.

Fig. 2 represents " exclusive OR " tree network figure of the column vector of one 12 bit trial word.

Fig. 3 represents the misconnection figure as 12 exclusive OR structures of check word generator or detecting device.

Fig. 4 is the structural drawing of correcting unit.

Fig. 5 represents misconnection and the data flow figure between generator and the detecting device.

Fig. 6 represents the data flowchart through correcting unit.

Fig. 1 a-1b represents the generator matrix that formed by the inventive method, and the generator matrix of the check word relevant with data check is illustrated respectively among Fig. 1 a-1b, and these independent matrix-blocks are arranged mutually continuously by the binary digit sequence number of data word.Check word matrix among Fig. 1 c in addition that is connected.The vertical edges of this matrix provides 128 data bit, and its horizontal sides provides 12 bit check words.

Field these 128 data bit of explanation with the intersection mark among the figure respectively influence a check bit.Thereby can predict corresponding 32 data bit of per 1 check bit.

These 128 data bit are that a message part word is coefficient with 4 always.This be by 32 or 35(band detected words) the DRAMs storer of parallel 4 bit wides of bar on purpose realized.

12 check digit are attached on 128 data bit among Fig. 1 c, and they are divided into each by 43 check partial words that constitute, because they always are arranged in the storer with 4 bit wides.

The predetermined weighted value Gz=3 of generator, this is meant every row of this matrix, this has relation with the condition of adding, be that each data bit only influences maximum 2 bits in the check part word by line mode, we can say at last, replace all 12 check bit, only must consider 3 (unit data position) now, this is meant by line mode certainly.

This makes realizes error recovery very apace under the situation of recoverable mistake.And check word itself will be encoded according to Fig. 1 c.In other words, relate to a kind of like this method in this fault identification and bearing calibration, promptly the same just as the normal method of describing in technical literature, verification does not add in this generator matrix surely.

Under the situation of single binary bit mistake in the correctable data word (Gsy=n, n＞2) and the single binary bit mistake in the correctable check word (Gsy=1), the weighting Gsy of comprehensive word is asymmetric.Its condition is, these binary digits are to distribute like this in a row matrix, one with partial words that the memory assembly width conforms in, 2 bits of encoded (representing with intersecting to accord with in the matrix) with maximum, can determine like this, can distinguish in a check 3 bits and 4 bit errors and single binary bit mistake of recoverable data in the partial words.Provide possibility for simplifying correcting unit like this, the position of drawing fork in the matrix has been deciphered because only need.Whether the existence of determining a repairable data bit mistake can realize according to the weighted value of comprehensive word (between the specified and practice examining word poor) (mould displacement sign indicating number and).In this case, if there is no mistake, these data words are then by normal transmission, exist if the weighted value of comprehensive word demonstrates a repairable mistake, then 3 bit partial words mistakes of repairable data bit mistake and check word itself are distinguished mutually and are distinguished.Under the situation that the data bit mistake occurs, this comprehensive word produce one with generation joint in error correction unit " mistake, complexity and cost are big especially for this known method, and are in operation and very easily make mistakes.This single byte errors is significant, because under the situation of the memory element that adopts the 4-bit width, the mistake of a hardware shows that certain used in storer memory module has damaged.Fact proved that method of the present invention provides a kind of technical unusual simple method of operation, can quickly and reliably come out to above-mentioned fault identification with interference-free.Identify precision in order to improve identification, in the preferred embodiment of the inventive method, the generator matrix shown in this 12 bit trial radical certificate is distributed by further systematization.

These 12 check digit are divided into 4 son group U0, U1, and U2, U3, one group of per 3 bit, they distribute systematically according to claim 4, and this is for discerning and differentiating different error types and created condition.

Carry out distinguishing of single error type is following:

1 bit error the in-data bit is to be that 3 Kazakhstan prescribed distance is distributed on two or 3 check partial words and is distributed on two or 3 son groups and discerned in check digit by one.

-1 bit trial word error is by being that 1 Kazakhstan prescribed distance is distinguished or discerned in detecting position.

-2 bit errors in check digit are by being that 2 Kazakhstan prescribed distance is distinguished in the check digit.

3 bits the in-data bit and 4 bit errors cause in check digit bigger or equal 4 Kazakhstan prescribed distance.

It is 3 the corresponding to coding of Kazakhstan matrix that-3 bit burst errors in check digit produce in the check digit, thereby starts this error correction procedure that data bit of mistake is arranged, and finishes the correction (conversion) of this wrong bit.Under the situation of the 3 bit partial words mistakes that detected words occurs, the not encoding section phase-splitting coordination as yet of this comprehensive word and this generator matrix, thus do not start the correction input process.Produce desired normal data word at output terminal like this.

This unusual asymmetry has also reduced the coding depth on the correcting logic significantly, so because hardware consumption only needs very little realization expense less, owing to can obtain higher arithmetic speed less correction time.These two major advantages of the present invention just.

In order to further specify the mode of action of the inventive method, at first introduce relevant notion of breathing out prescribed distance here.Promptly breathe out the prescribed distance value and show, how many bits one first check word and another check word differ actually.

In the method for the invention, mistake identifies that breathing out prescribed distance according to this realizes.

Learn that thus any 1 bit error can be discerned and recoverable, 2 bit errors can identify arbitrarily, and 3 bits and 4 bit errors also can be discerned in addition, even these mistakes produce from one 4 bit information partial words.This storer is that the DRAMs by 4 bit widths constitutes as previously mentioned.Realize the structural design that the relevant check word of method of the present invention generates has confirmed it is very practical.Adopt this structural design, realized the identification of above-mentioned 3-bit and 4-bit error first, described mistake is meant the mistake that is occurred in the message part word of a 4-bit width.

If the distribution of data word and the check word that is constituted thereon generate and realize by method of the present invention, it almost is impossible then only determining these special mistakes with little consumption like this.Utilize the special method of prior art can detect also that so-called " the individual character prescribed distance so only relate to a check partial words, and maximum only relates to two groupings.The check word that is used for this mistake is that to be used for the check word of 1-bit error not inconsistent with data bit.

It is 4 Kazakhstan prescribed distance that-4-bit error in check digit produces in the check digit.

-3-bit is identified with the 2-bit error is the same arbitrarily with 4-bit burst error, distinguishes mutually surely but differ.This can be represented according to very little frequency number of times.

Further rule is, accurate 3 check digit of each data bit affects, and they are to divide like this, i.e. one or two check word one grouping has nothing to do.Further described code, i.e. check digit modulation is to divide like this, promptly the bits of encoded of each check digit 4-bit-message part word is accurately disposable relevant.

Employing produces 384(128*3 by 3 in 12 codings or the generator) individual signal is as coded signal.Per 12 check digit are subjected to 32(384/12) influence of data word bits.Thereby reduced maximum coding depth, and a kind of useful modular construction is provided, it has the hardware pattern of simplification and has the processing speed of optimization.All these conditions all have been included in the generator matrix design of Fig. 1 a-1c.

Fig. 2 shown as the embodiment that from 128 bit data word, produces 12 bit trial words by hard-wired primary element.Matrix takes place check word one " Structure Conversion " here begins to produce.According to the generator matrix, the bit of these 32 data words that will consider is deposited in " exclusive OR-tree-like " structure shown among the figure; The input of these 32 XOR structures is represented with X.Here demonstrate at each XOR element 10,11,12 ... in per 4 data bit deposit in as an input quantity.Signal and remaining output signal in each exclusive OR element output terminal output are transported to next exclusive OR-level 18 jointly.Illustrated this level in, parity checking generally by the generator matrix 12 row one of 32 bits selected and that deposit in constituted.Also have a control bit K also to be input to this exclusive OR-level in addition, the function of this control bit will be described below.Because the generator matrix relevant with the check word of selected 12-bit width comprised 12 this parity checkings by row, this hardware also is made of 12 such exclusive OR-tree networks.These exclusive OR-tree networks are respectively exported the check word of a 12-bit.

Fig. 3 represents the general structure of this generator, and generator is assembled by 12 devices shown in Figure 2.128 bit data word transmit by bus D, and these data words will be imported corresponding to the generator matrix that is disposed, and that is to say, adopt reasonable configuration to deposit in each 32 input ends 100,101 of 12 exclusive OR-tree networks.As shown in Figure 2, can deposit a control bit K in each exclusive OR-tree branch, so 12-bit control vector is provided altogether.

These 12 exclusive ORs-branch's output is used for the overall test word of whole data word.This total configuration (Fig. 3) occurs twice exactly in this device, once be called generator 1, once is called verifier one recognizer (Priifer-fortan Checker) 2 from now on.And the structure of generator 1 and recognizer 2 is identical.

Above-mentioned control input K is the input side that is connected on exclusive OR-tree network 100,101, under normal circumstances, K value when generator 1 is made as 0, and under the situation of test, this control input can be set at 1, this is in order to simulate a mistake, and till the testing hardware system.Under the situation of recognizer 2, this control input all flows in the corresponding acceptance inspection position, thus on output terminal directly acquisition be ready to the comprehensive syndrome of stand-by mistake, promptly refer to the bit difference between the check word of regeneration and the check word that receives.

Fig. 4 has shown the correcting unit 200 of this device.140 total number of bits are divided into data word Ds according to word and check word P is input in this correcting unit.This 128 bit data word is input in the actual adjusting level 201, and each bit is handled through the controlled converter 210 of a separation there, and this converter is made of an exclusive OR-element that simply has two inputs and an output.

Each of 128 bits occupies the input end A of a converter 210 at every turn.Another input end B of check word matrix decoder 202 these converters of control.The input side of this check word matrix decoder 202 deposits the comprehensive syndrome of difference check word Sy-in.This comprehensive test word is emphasized once more on this position that generally error recovery has only in this case just startup certainly, thereby identifies repairable mistake.By the address that check word matrix decoder 202 also can be found the data bit of relevant band mistake from this comprehensive word Sy-check word, control the work of relevant converter 210 then.

Export the 128 bit data word Dc that proofreaied and correct from this correcting unit.Comprehensive word check level 203 is used to determine whether to exist an aforesaid correctable mistake.Here check word Sy also inputs to this comprehensive word check level 203 when depositing check word matrix decoder 202 in.

This check word matrix decoder 202 is pressed line mode with the decoding of this generator matrix, and when having value among the relevant capable n of bit at this generator matrix of these 3 marks and be 1, the value that then produces a bit n of 128 bit data word vectors is 1.

This unit has filtered invalid check word by comprehensive word check when finding to have correctable mistake, have only the word of having proofreaied and correct just to be adopted, thereby simplified cellular construction.In this case, from 203 outputs of comprehensive word check level so-called sign (Flag), i.e. data one a soft error-sign Sf.When comprehensive word input during, and when not producing this soft error-sign Sf, will produce a hard mistake-sign Hf more than 1 bit.This hard mistake-sign is provided by hard mistake generator 204.The formation of this hard mistake generator comprises the AND circuit of one 12 times OR circuit, converter and 2 times.

Fig. 5 is illustrated in the data flow between check word generator 1 and the check word assessor 2, and the functional annexation between discrete component.This check word generator starts when data transmission, and notes this 128 bit data word Ds and this 12 bit generator mask G.This 128 bit data word is input in the generator 1, and is sent to the output terminal of generator 1 by a parallel circuit, converges mutually with this 12 bit trial word P there.Total data word D of this 140 bit is propagated then.The operation of memory function piece 300 is to realize through the data circuit of this double-head arrow sign.This streams data is carried out at both direction, promptly deposits in and takes out, and memory function spare 300 is DRAMs structures of 4 bit widths, thereby this data word is divided into 35 DRAMs.The word of this 140 bit long is subjected to the protection of this check word on its total length, and this check word is protected jointly.After being divided into 128 bit data word Ds and check word P now, the total data word D of this that receive on receiver deposits in the verifier 2 that is assembled.This verifier is checked this check word, and form the comprehensive word of differential check word Sy--.

This comprehensive word is delivered in the correcting unit shown in Figure 4 200 then, identifies situation according to mistake, proofreaies and correct error correction procedure when needed.

Control input among Fig. 2 deposits in the verifier 2 with check digit simultaneously, thereby in the inner differential process that forms of verifier, also can form this comprehensive word structure.

Fig. 6 represents the additional correcting unit of receiving in 2 configurations of generator 1/ verifier 200.The output of verifier 2 is as the input of correcting unit among Fig. 6 200 among Fig. 5.Data word Ds and formed comprehensive word Sy deposit in the mode shown in Fig. 4.

Data word Dc after output has been proofreaied and correct from this correcting unit 200 then, it is sent into again in the multiplier 4 then.Not calibrated data word Ds also sends into another input end of this multiplier 4 simultaneously.Inner structure according to correcting unit 200, a soft error-mark Sf sends into multiplier 4 as the control input from these correcting unit 200 outputs, thereby this multiplier can be determined according to the error state of having identified, export the data word Dc after having proofreaied and correct actually or export original data word Ds.

Exist under the situation of hard mistake, this correcting unit provides relevant hard mistake-mark Hf, for example interrupts the Writing/Reading process suddenly and shows mistake.

Claims (10)

1, is used for discerning and/or the method for correction data word 1 bit and many bit errors, these data words are implemented in reading and writing in the memory assembly by data bus, check word is attached on the data word, according to the difference structure by turn between the practice examining word after specified check word and the data transmission, form a comprehensive word, the value of this comprehensive word makes and can realize an error correction procedure under the situation of data error having, or impels the repetitive operation of a read/write processes in case of necessity

It is characterized in that,

-total word length W is divided into data word length d and check word length P, and the bit number of numeral is an x=d/4 data division word, is benchmark with 4 bits promptly at every turn, and the bit number of check word is a y=P/4 check partial words, with 4 bits is benchmark, and each partial words belongs to the memory element of one 4 bit width

-be to produce like this with respect to the check word of a data word, this check word generator adopts the d*P generator matrix form of each column vector (1-P), generation is weighted to Gs=d/4, thereby when pressing the row parity checking, the amount of each d/4 data bit influences a check digit, and each row vector has generator weighting Gz=P/4 simultaneously, like this, presses a check of maximum 2 bit affects of each data bit of line mode partial words.

2, according to claim 1 be used for discern and/or the method for correction data word 1 and many bit errors, it is characterized in that, total word length W=140 bit, data word length d=128 bit wherein, check word length P=12 bit, so the big or small y=3 of the big or small x=32 of data division word and check partial words.

3, be used to discern and/or proofread and correct 1 and the method for many bit errors according to claim 2, it is characterized in that, repairable unit mistake in check word is to distinguish by the weighted value of the comprehensive word of Gsy=3 and the repairable unit mistake in the data word, data word has the weighted value of the comprehensive word of Gsy=1, identify have such mistake after, realize error-correction operation by changing this wrong bit.

4, be used to discern and/or correct 1 and the method for many bit errors according to claim 3, it is characterized in that, identify in order further to realize mistake, this generator matrix should satisfy following condition in the check word generating process, following 4 son group U0, U1, the U2 of being divided into of per 3 bits of this check word, U3, wherein:

The not acceptor group U0 influence of the 32nd bit 0 of 32 data partial words,

The not acceptor group U1 influence of the 32nd bit 1 of 32 data partial words,

The not acceptor group U2 influence of the 32nd bit 2 of 32 data partial words,

The not acceptor group U3 influence of the 32nd bit 3 of 32 data partial words.

5, be used for discerning and/or the device of correction data word 1 and many bit errors, these data words are implemented in read/write operation in the memory assembly by data bus, wherein check word is attached on the data word in generator, difference structure according to specified check word and practice examining word, on data receiver, produce a comprehensive word, carry out relevant error recovery or restart read/write processes one time by error correction unit of this comprehensive word control

It is characterized in that,

Also have P the tree-like unit (100 of check word exclusive OR, 101,), the input X of each unit is in d/4, and this data word length (d) has check word, the data word bit of selecting of this d/4 deposits relevant unit in, the check word that a check digit is respectively exported in these tree-like unit converges to (18), therefore by P exclusive OR-tree structure (100,101,) always constitute the check digit of P check word

Data transmitter side at generator (1), check word (P) is attached on this data word (Ds), and has a verifier (2) identical with generator (1) structure at receiver side, it exports this comprehensive word (Sy), this comprehensive word and data word (Ds) are sent on the correcting unit (200) jointly, correcting unit is made of d converter (210), the input of each converter (A) has one of controlled d data bit, the input of each converter (B) is subjected to depositing in the control of each output of the check word matrix decoder (202) of comprehensive word, and the output of each converter always produces the data word after having proofreaied and correct.

6, according to claim 5 be used for discern and/or the device of correction data word 1 and many bit errors, it is characterized in that,

Exclusive OR-tree-like unit (100,101,) be to constitute like this, it has d/4 data bit to be tested, forms d*P generator matrix, its weighting Gs=d/4 with each column vector (1-P), thereby when pressing the parity checking of row mode, check digit of every d/4 data position influence, simultaneously each row vector has generator weighting Gz=P/4, thus one of check word that constitutes by 4 bits by maximum 2 bit affects of each data bit of line mode.

7, according to claim 6ly be used for discerning and/or the device of correction data position 1 and many bit errors, it is characterized in that, this correcting unit (200) has a comprehensive word assessor (203), this comprehensive word (Sy) both had been input to check word matrix decoder (202), be input to this comprehensive word assessor again, after this comprehensive word assessor (203) evaluation, set an output soft error-sign (Sf) or a hard mistake sign (Hf) according to the weighted value of check word, with this soft error sign control multiplier (4), make this multiplier from data word (Ds) that is transmitted and the data word (Dc) of having proofreaied and correct, select the active data word.

8, according in the aforementioned claim one or more be used for discern and/or the device of correction data word 1 and many bit errors, it is characterized in that, each exclusive OR-tree unit (100,101 ...) have an additional control input K.

9, according to Claim 8 be used for discern and/or the device of correction data word 1 and many bit errors, it is characterized in that,

Go up each may command at verifier (2) and directly import relevant acceptance inspection position, thereby the relevant bit of at every turn exporting this comprehensive word of (18) at exclusive OR-assembly is available.

10, according in the aforementioned claim one or more be used for discern and/or the device of correction data word 1 and many bit errors, it is characterized in that, exclusive OR-tree network (100,101 ...) input quantity x select like this, it can deposit data word length d=128 bit in, and its exportable 12 check digit, thus be as the criterion with per 4 bits, and the amount of data division word is x=32, be as the criterion with per 4 bits equally, the amount of check partial words is y=3.

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