CN111124741B - Enhanced type checking and error correcting device facing memory characteristics - Google Patents
Enhanced type checking and error correcting device facing memory characteristics Download PDFInfo
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- CN111124741B CN111124741B CN201911271305.5A CN201911271305A CN111124741B CN 111124741 B CN111124741 B CN 111124741B CN 201911271305 A CN201911271305 A CN 201911271305A CN 111124741 B CN111124741 B CN 111124741B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
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Abstract
The invention relates to a memory-feature-oriented enhanced type checking and error correcting device, which comprises: the arithmetic coding module is arranged on a write path of the memory and used for generating an N-bit check code according to the M-bit data and writing the data bit and the check bit into the memory, wherein the check code comprises a CRC (cyclic redundancy check) code and an even check code; the algorithm decoding module is arranged on a memory read path and used for checking and correcting errors in a particle unit according to K bit data; and one side of the interface module is respectively connected with the algorithm coding module and the algorithm decoding module, and the other side of the interface module is connected with the memory and is used for grouping the K bit data output by the algorithm coding module according to the number of memory particles and dividing the K bit data on the memory interface into T groups in a 16-bit mode to realize data remapping. The invention can carry out random error correction on a certain memory grain.
Description
Technical Field
The invention relates to the technical field of memory data check and error correction, in particular to an enhanced check and error correction device facing to memory characteristics.
Background
With the continuous improvement of the process and the continuous increase of the demand, the memory interface frequency is higher and higher, the number of the memory interface channels is larger and larger, and the transmission stability of the memory interface faces more challenges. The memory data errors are not only related to the memory cells themselves, but are also more limited by the board level design of the PCB. The influence brought by the integrity of the power supply and the signal is often related to multi-bit data in the same group (the data of the same memory grain is used as a group, and the PCB design adopts the same wiring mode), and the ECC correction algorithm only corrects one bit and cannot cope with the situation.
Disclosure of Invention
The invention aims to provide an enhanced checking and error correcting device facing to memory characteristics, which can carry out random error correction on certain memory particles.
The technical scheme adopted by the invention for solving the technical problems is as follows: there is provided a memory-feature-oriented enhanced parity error correction apparatus, comprising: the arithmetic coding module is arranged on a write path of the memory and used for generating an N-bit check code according to the M-bit data and writing the data bit and the check bit into the memory, wherein the check code comprises a CRC (cyclic redundancy check) code and an even check code; the algorithm decoding module is arranged on a memory read path and used for checking and correcting errors in a particle unit according to K bit data; one side of the interface module is connected with the algorithm coding module and the algorithm decoding module respectively, the other side of the interface module is connected with the memory and used for grouping K bit data output by the algorithm coding module according to the number of memory particles and dividing the K bit data on the memory interface into T groups in a 16-bit mode to realize data remapping, wherein the K bit data are arranged in the sequence of M bit data, CRC check codes and even check codes, and K = M + N.
The algorithm coding module comprises a CRC-16 check unit and a first even check unit, wherein the CRC-16 check unit obtains a CRC check code through CRC-16 operation according to M/16 group data; and the first even check unit carries out bitwise XOR operation on the M/16 group of data and the CRC check code to obtain an even check code.
The algorithm decoding module comprises a second even check unit, an exclusive OR operation unit and an error correction unit; the second even check unit obtains a new even check code by performing bitwise XOR operation on the first T-1 group of input K bit data; the XOR operation unit obtains an error position indication bit by XOR operation of the even check code and the new even check code; and the error correction unit respectively restores the previous T-2 group data of the K bit data according to the error position indication bits, respectively regenerates new CRC codes for the restored data, and determines the error group by comparing the new CRC codes with the CRC codes and corrects the error.
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: the invention is based on a CRC/even check hybrid check algorithm, comprises an algorithm coding module and an algorithm decoding module, can realize continuous 4-bit data check and error correction aiming at memory particles, and greatly improves the error correction capability compared with ECC. The invention provides a more efficient data error correction mechanism aiming at the error characteristics of the memory, and the stability of the memory is ensured to the maximum extent.
Drawings
FIG. 1 is a schematic structural diagram of an embodiment of the present invention;
FIG. 2 is a diagram of data mapping logic in an embodiment of the present invention;
FIG. 3 is a schematic diagram of an algorithm encoding module according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an algorithm decoding module in the embodiment of the present invention.
Detailed Description
The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.
The embodiment of the invention relates to an enhanced checking and error correcting device facing to memory characteristics, which comprises: the arithmetic coding module is arranged on a write path of the memory and used for generating an N-bit check code according to the M-bit data and writing the data bit and the check bit into the memory, wherein the check code comprises a CRC (cyclic redundancy check) code and an even check code; the algorithm decoding module is arranged on a memory read path and used for checking and correcting errors in a particle unit according to K bit data; one side of the interface module is connected with the algorithm coding module and the algorithm decoding module respectively, the other side of the interface module is connected with the memory and used for grouping K bit data output by the algorithm coding module according to the number of memory particles and dividing the K bit data on the memory interface into T groups in a 16-bit mode to realize data remapping, wherein the K bit data are arranged in the sequence of M bit data, CRC check codes and even check codes, and K = M + N.
As shown in fig. 1, in the present embodiment, four beats of data (72 bits × 4 beats) are present on the memory interface, the four beats of data are verified as a whole, and 288 bits of data are grouped according to the x4 granule of the memory. The 288-bit data includes 256-bit data and a 32-bit check code, wherein the 32-bit check code is divided into a 16-bit CRC check code (CRC-16) and a 16-bit even check code. In the data mapping logic shown in fig. 2, the interface module in this embodiment uses the data mapping logic of fig. 2 to divide 288 bits of data into 18 groups.
As shown in fig. 3, the algorithm encoding module includes a CRC-16 check unit and a first even check unit, and the CRC-16 check unit obtains a CRC check code through CRC-16 operation according to 16 groups of data; and the first even check unit carries out bitwise XOR operation on the 16 groups of data and the CRC check code to obtain an even check code.
In the embodiment, data check is performed on 18 groups of information, and a check algorithm is combined with CRC-16 check and even check. The 1 st group to the 16 th group correspond to 256 bits of data, the 17 th group is the CRC check code of the first 16 groups, and the 18 th group is the even check code of the first 17 groups. The algorithm encoding module generates an original CRC check code (CRC _ old) and an even check code (P _ old) for the write operation.
As shown in fig. 4, the algorithm decoding module includes a second even check unit, an exclusive or operation unit, and an error correction unit; the second even check unit obtains a new even check code (P _ new) by carrying out bitwise XOR operation on the first 17 groups of input 288 bit data; the XOR operation unit obtains an error position indication bit (P _ rec) by carrying out XOR operation on the even parity code (P _ old) and the new even parity code (P _ new); the error correction unit restores the previous 16 groups of 288-bit data respectively according to the error position indication bits (P _ rec), regenerates new CRC codes (CRC _ new1.. CRC _ new 16) respectively for the restored data, and determines the error groups and corrects the errors by comparing the new CRC codes (CRC _ new1.. CRC _ new 16) and the CRC check codes (CRC _ old).
It is not easy to find that the invention sets up the algorithm coding module on the memorizer write path, produce CRC code and even check code according to 256 bit data, and write data bit and check bit into the memorizer. An algorithm decoding module is arranged on a read path of the memory, and check error correction in a unit of x4 grains is carried out according to 288 bits of information. Compared with ECC (error correction code) checking, the method can correct errors of the x4 grains of the memory, and can realize continuous 4-bit data checking and error correction of the memory grains. Any bit data error of a certain x4 grain can be corrected by the method, and ECC correction can only aim at one bit data error. Obviously, compared with ECC check, the error correction capability is greatly improved.
Claims (3)
1. An enhanced parity error correction (ECC) apparatus for memory-oriented features, comprising: the algorithm coding module is arranged on a writing path of the memory and used for generating an N-bit check code according to the M-bit data and writing the data bits and the check bits into the memory, wherein the check code comprises a CRC (cyclic redundancy check) code and an even check code; the algorithm decoding module is arranged on a memory read path and used for carrying out check error correction by taking particles as units according to K bit data; and the interface module is connected with the algorithm coding module and the algorithm decoding module on one side, and connected with the memory on the other side, and is used for grouping the K bit data output by the algorithm coding module according to the number of memory particles, and dividing the K bit data on the memory interface into T groups in a 16-bit mode per group to realize data remapping, wherein the K bit data are arranged in the order of M bit data, CRC check codes and even check codes, and K = M + N.
2. The enhanced memory-oriented error correction check device of claim 1, wherein the algorithm coding module comprises a CRC-16 check unit and a first even check unit, and the CRC-16 check unit obtains a CRC check code through CRC-16 operation according to M/16 groups of data; and the first even check unit carries out bitwise XOR operation on the M/16 group of data and the CRC check code to obtain an even check code.
3. The enhanced memory-oriented parity error correction apparatus of claim 1, wherein the algorithm decoding module comprises a second even parity unit, an exclusive-or operation unit and an error correction unit; the second even check unit obtains a new even check code by performing bitwise XOR operation on the first T-1 group of input K bit data; the XOR operation unit obtains an error position indication bit by XOR operation of the even check code and the new even check code; and the error correction unit respectively restores the previous T-2 group data of the K bit data according to the error position indication bits, respectively regenerates new CRC codes for the restored data, and determines the error group by comparing the new CRC codes with the CRC codes and corrects the error.
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| CN113094206A (en) * | 2021-04-14 | 2021-07-09 | 合肥富煌君达高科信息技术有限公司 | High-speed data access method and device based on error correction |
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| CN102339647B (en) * | 2010-07-23 | 2014-05-14 | 北京兆易创新科技股份有限公司 | Detection method and apparatus for error checking and correcting (ECC) check module |
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