CN109148614B - Silicon heterojunction solar cell and preparation method thereof - Google Patents
Silicon heterojunction solar cell and preparation method thereof Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 25
- 239000010703 silicon Substances 0.000 title claims abstract description 25
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 153
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 129
- 239000000956 alloy Substances 0.000 claims abstract description 129
- 230000007704 transition Effects 0.000 claims abstract description 74
- 229910052751 metal Inorganic materials 0.000 claims abstract description 73
- 239000002184 metal Substances 0.000 claims abstract description 73
- 239000010949 copper Substances 0.000 claims abstract description 70
- 229910052802 copper Inorganic materials 0.000 claims abstract description 59
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims description 34
- 229910002065 alloy metal Inorganic materials 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 238000005275 alloying Methods 0.000 claims description 9
- 229910017755 Cu-Sn Inorganic materials 0.000 claims description 8
- 229910017927 Cu—Sn Inorganic materials 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 229910000846 In alloy Inorganic materials 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 7
- 238000005240 physical vapour deposition Methods 0.000 claims description 7
- 229910052738 indium Inorganic materials 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 229910003310 Ni-Al Inorganic materials 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000004050 hot filament vapor deposition Methods 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 321
- 210000004027 cell Anatomy 0.000 description 51
- 230000007797 corrosion Effects 0.000 description 11
- 238000005260 corrosion Methods 0.000 description 11
- 239000000463 material Substances 0.000 description 10
- 230000000694 effects Effects 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 239000010408 film Substances 0.000 description 5
- 229910000510 noble metal Inorganic materials 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 239000000969 carrier Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 4
- 238000011049 filling Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Abstract
The invention discloses a silicon heterojunction solar cell and a preparation method thereof. Wherein, this solar cell includes: an n-type crystalline silicon substrate layer; lightly doped n-type hydrogenated amorphous silicon buffer layers formed on upper and lower side surfaces of the substrate layer; a heavily doped p-type hydrogenated amorphous silicon emitter layer formed on a surface of the hydrogenated amorphous silicon buffer layer on one side; the heavily doped n-type hydrogenated amorphous silicon back surface field layer is formed on the surface of the hydrogenated amorphous silicon buffer layer at the other side; a transparent conductive oxide layer formed on surfaces of the hydrogenated amorphous silicon emitter layer and the hydrogenated amorphous silicon back surface field layer; a metal gate line electrode layer, the metal gate line electrode layer comprising: the alloy transition layer is formed on at least one surface of the transparent conductive oxide layer, the hydrogenated amorphous silicon back surface field layer and the hydrogenated amorphous silicon emitter layer; and the copper-containing conductive alloy layer is formed on the surface of the alloy transition layer.
Description
Technical Field
The invention relates to the field of solar cells, in particular to a silicon heterojunction solar cell containing a copper alloy electrode and a preparation method thereof.
Background
In conventional crystalline silicon-based solar cells, the electrodes are typically prepared by screen printing an Ag paste followed by sintering at high temperature (> 700 ℃) to form a good ohmic contact between the Ag and the substrate Si, the paste used being a high temperature Ag paste. However, the electrode formed by this method has the characteristics of expensive material, wide line width and limited line height, and limits the application of thinner silicon wafers, and is becoming one of the limiting factors for further reducing the cost of the battery and improving the efficiency.
In amorphous silicon/crystalline silicon heterojunction solar cells, the p-n junction is formed by using an amorphous silicon thin film, so that the forming temperature of the thin film determines the highest preparation process temperature of the cell, and can only be about 200 ℃ in general. In order to meet the low-temperature preparation requirement of the heterojunction battery, when the electrode is prepared, low-temperature Ag paste is adopted, however, the electrode formed by sintering the paste has obviously increased series resistance, and the improvement of the battery efficiency is not facilitated. Another solution is to replace Ag with Cu, which is a non-noble metal. Cu has low cost and conductivity similar to Ag, and is a promising material. However, cu is easily oxidized and corroded in a wet environment, and the electrical resistance is greatly increased, and the strength is lowered. Therefore, cu electrodes often need to be coated on the surface to protect them from corrosion. The commonly used Cu electrode is a stacked metal layer of Ni/Cu/Sn formed by chemical plating/electroplating/photoinduced electroplating and the like, wherein the metal Ni is used as a barrier layer to prevent Cu from diffusing into silicon, and Sn is covered on the surface of the Cu layer to play a role in protecting Cu from being oxidized and simultaneously facilitating welding. The electrode has a thinner grid line and lower contact resistance, but has the problem of poor adhesion between the stacked metal layers and the substrate Si, and the barrier layer of a single element such as Ni, ta, ti, cr has higher resistivity, so that the conductivity can be improved if Cu alloy is formed, and meanwhile, the alloying of Cu is also beneficial to improving the oxidation resistance and corrosion resistance of pure copper.
Thus, the existing solar cell needs to be improved.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, an object of the present invention is to provide a silicon heterojunction solar cell (hereinafter also simply referred to as "solar cell") which can effectively reduce the series resistance of the cell, and is advantageous for improving the oxidation resistance, corrosion resistance, etc. of the electrode and enhancing the stability of the cell in the application environment by alloying the metal gate electrode layer.
According to one aspect of the invention, a silicon heterojunction solar cell is provided. According to an embodiment of the present invention, the solar cell includes:
an n-type crystalline silicon substrate layer;
lightly doped n-type hydrogenated amorphous silicon buffer layers formed on upper and lower side surfaces of the substrate layer;
a heavily doped p-type hydrogenated amorphous silicon emitter layer formed on a surface of the lightly doped n-type hydrogenated amorphous silicon buffer layer at one side;
the heavily doped n-type hydrogenated amorphous silicon back surface field layer is formed on the surface of the lightly doped n-type hydrogenated amorphous silicon buffer layer at the other side;
a transparent conductive oxide layer formed on surfaces of the heavily doped p-type hydrogenated amorphous silicon emitter layer and the heavily doped n-type hydrogenated amorphous silicon back surface field layer;
a metal gate line electrode layer, the metal gate line electrode layer comprising:
an alloy transition layer formed on a surface of at least one of the transparent conductive oxide layer, the heavily doped n-type hydrogenated amorphous silicon back surface field layer, and the heavily doped p-type hydrogenated amorphous silicon emitter layer;
and a copper-containing conductive alloy layer formed on a surface of the alloy transition layer.
According to the solar cell provided by the embodiment of the invention, the metal grid line electrode layer is formed by alloy metal, and the main component of the alloy metal is copper, so that the use of noble metals such as Ag is greatly reduced while the lower resistivity is maintained, the oxidation resistance, corrosion resistance and the like of single metal can be effectively improved to a certain extent by alloying, the stability of the cell in an application environment is enhanced, wherein the alloy transition layer not only can increase the adhesive force of the electrode on the surface of the cell and improve the matching degree of the thermal expansion coefficient between the cell material and the electrode material, but also can play a role of local doping on the contact position of the cell and the electrode through doping elements, and the series resistance of an emitter or a back field and the grid line is reduced, thereby realizing the effects of improving the cell filling factor and the cell efficiency.
In addition, the solar cell according to the above embodiment of the present invention may further have the following additional technical features:
according to an embodiment of the invention, the doping concentration of the lightly doped n-type hydrogenated amorphous silicon layer is 10 8 -10 17 /cm 3 。
According to an embodiment of the present invention, the alloy transition layer contains at least two metals selected from Cu, mo, W, ti, ni, cr, al, mg, ta, sn, zn and Ag, preferably, the alloy transition layer contains a Ni-Cu-Sn alloy, a Ni-Cu-In alloy, or a Ni-Al alloy.
According to an embodiment of the present invention, the copper-containing conductive alloy layer contains Cu and at least one metal selected from Mo, W, ti, ni, cr, al, mg, ta, sn, zn and Ag.
According to an embodiment of the present invention, the alloy transition layer may further contain an element selected from B, P, ga and In.
According to an embodiment of the present invention, the copper-containing conductive alloy layer may further contain at least one element selected from B, P, ga and In.
According to an embodiment of the invention, the copper content of the copper-containing conductive alloy layer is gradually increased from the end near the alloy transition layer to the end far from the alloy transition layer, the copper content near the alloy transition layer is 85% -99% wt, and the copper content far from the alloy transition layer is 99% -100% wt.
According to an embodiment of the present invention, the resistivity of the metal gate line electrode layer is not more than 1.5X10 -5 Ω·cm。
According to the embodiment of the invention, the thickness of the n-type crystal silicon substrate layer is 50-200 mu m.
According to the embodiment of the invention, the thickness of the lightly doped n-type hydrogenated amorphous silicon buffer layer is 1-15nm.
According to the embodiment of the invention, the thickness of the heavily doped p-type hydrogenated amorphous silicon emitter layer is 5-25nm.
According to the embodiment of the invention, the thickness of the heavily doped n-type hydrogenated amorphous silicon back surface field layer is 5-25nm.
According to an embodiment of the present invention, the transparent conductive oxide layer has a thickness of 50-300nm.
According to an embodiment of the invention, the thickness of the alloy transition layer is 5-300nm.
According to an embodiment of the invention, the thickness of the copper-containing conductive alloy layer is 1-100 μm.
According to another aspect of the present invention, there is provided a method of preparing the aforementioned silicon heterojunction solar cell. According to an embodiment of the invention, the method comprises:
providing an n-type crystalline silicon substrate layer;
forming lightly doped n-type hydrogenated amorphous silicon buffer layers on the upper side surface and the lower side surface of the n-type crystalline silicon substrate layer;
forming a heavily doped p-type hydrogenated amorphous silicon emitter layer on the surface of the lightly doped n-type hydrogenated amorphous silicon buffer layer at one side;
forming a heavily doped n-type hydrogenated amorphous silicon back surface field layer on the surface of the lightly doped n-type hydrogenated amorphous silicon buffer layer at the other side;
forming transparent conductive oxide layers on the surfaces of the heavily doped p-type hydrogenated amorphous silicon emitter layer and the heavily doped n-type hydrogenated amorphous silicon back surface field layer respectively; and
and forming a metal gate line electrode layer on the surface of at least one layer of the transparent conductive oxide layer, the heavily doped n-type hydrogenated amorphous silicon back surface field layer and the heavily doped p-type hydrogenated amorphous silicon emitter layer, wherein the metal gate line electrode layer comprises an alloy transition layer and a copper-containing conductive alloy layer.
According to the method for preparing the solar cell, the prepared solar cell is provided with the alloy metal grid line electrode layer, and the main component of the electrode layer is copper, so that the use of noble metals such as Ag is greatly reduced while the lower resistivity is kept, the oxidation resistance, corrosion resistance and the like of single metal can be effectively improved by alloying to a certain extent, and the stability of the cell in an application environment is enhanced, wherein the alloy transition layer not only can increase the adhesive force of the electrode on the surface of the cell and improve the matching degree of the thermal expansion coefficient between the cell material and the electrode material and the like, but also can play a role of local doping on the contact position of the cell and the electrode through doping elements, and reduce the series resistance of an emitter and the grid line, thereby realizing the effect of improving the filling factor and the cell efficiency.
In addition, the method for manufacturing a solar cell according to the above-described embodiment of the present invention may further have the following additional technical features:
according to the embodiment of the invention, the n-type hydrogenated amorphous silicon buffer layer, the heavily doped p-type hydrogenated amorphous silicon emitter layer and the heavily doped n-type hydrogenated amorphous silicon back surface field layer are formed by adopting an ion enhanced chemical vapor deposition method, hot filament chemical vapor deposition, microwave plasma chemical vapor deposition or electron cyclotron resonance chemical vapor deposition.
According to an embodiment of the present invention, the alloy transition layer is formed by a physical vapor deposition method, preferably, an evaporation deposition method and a sputtering deposition method.
According to an embodiment of the present invention, the copper-containing conductive alloy layer is formed by an electroplating method.
According to an embodiment of the present invention, a method of forming the metal gate line electrode layer includes: depositing an alloy metal on the surface of at least one of the transparent conductive oxide layer, the hydrogenated amorphous silicon back surface field layer and the heavily doped p-type hydrogenated amorphous silicon emitter layer to form an alloy transition layer; forming a mask layer of a predetermined pattern on the surface of the alloy transition layer by using a photoresist film; forming the copper-containing conductive alloy layer on the surface of the alloy transition layer, wherein the copper-containing conductive alloy layer and the mask layer are arranged in a crossing manner; removing the mask layer and the alloy transition layer covered by the mask layer so as to form a metal gate line electrode layer intermediate; and annealing the intermediate of the metal gate line electrode layer to obtain the metal gate line electrode layer.
According to an embodiment of the invention, the alloy metal is a Ni-Cu-Sn alloy or a Ni-Cu-In alloy.
According to an embodiment of the invention, the transparent conductive oxide layer is the transparent conductive oxide layer near the hydrogenated amorphous silicon back surface field layer end or the hydrogenated amorphous silicon emitter layer end.
According to an embodiment of the present invention, a method of forming the metal gate line electrode layer includes: removing a portion of the transparent conductive oxide layer to form a transparent conductive oxide layer having a predetermined pattern, wherein the transparent conductive oxide layer is the transparent conductive oxide layer near the hydrogenated amorphous silicon emitter layer; depositing an alloy metal on surfaces of the transparent conductive oxide layer having a predetermined pattern and the hydrogenated amorphous silicon emitter layer so as to form an alloy transition layer; forming a mask layer on the surface of the alloy transition layer above the transparent conductive oxide layer; forming the copper-containing conductive alloy layer on the surface of the alloy transition layer above the hydrogenated amorphous silicon emitter layer so as to form a metal gate line electrode layer intermediate, wherein the copper-containing conductive alloy layer is arranged in a crossing manner with the mask layer; removing the mask layer and the alloy transition layer covered by the mask layer so as to form a metal gate line electrode layer intermediate; and annealing the intermediate of the metal gate line electrode layer to obtain the metal gate line electrode layer.
According to an embodiment of the invention, the alloy metal is a ni—al alloy.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 shows a schematic structure of a solar cell according to an embodiment of the present invention;
fig. 2 shows a schematic structure of a solar cell according to an embodiment of the present invention;
FIG. 3 shows a schematic diagram of an intermediate process of a method of manufacturing a solar cell according to one embodiment of the invention;
fig. 4 shows a flow diagram of a method of manufacturing a solar cell according to an embodiment of the invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
In the description of the present invention, the terms "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", etc. refer to the orientation or positional relationship based on that shown in the drawings, merely for convenience of description of the present invention and do not require that the present invention must be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
It should be noted that the terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying a number of technical features being indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. Further, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
According to one aspect of the invention, a silicon heterojunction solar cell is provided. Referring to fig. 1 and 2, the solar cell according to an embodiment of the present invention will be explained, the solar cell including: an n-type crystalline silicon substrate layer 100, a lightly doped n-type hydrogenated amorphous silicon buffer layer 200, a heavily doped p-type hydrogenated amorphous silicon emitter layer 300, a heavily doped n-type hydrogenated amorphous silicon back surface field layer 400, a transparent conductive oxide layer 500, and a metal gate line electrode layer 600. According to the solar cell provided by the embodiment of the invention, the metal grid line electrode layer is formed by alloy metal, and the main component of the alloy metal is copper, so that the use of noble metals such as Ag is greatly reduced while the lower resistivity is maintained, the oxidation resistance, corrosion resistance and the like of single metal can be effectively improved to a certain extent by alloying, the stability of the cell in an application environment is enhanced, wherein the alloy transition layer not only can increase the adhesive force of the electrode on the surface of the cell and improve the matching degree of the thermal expansion coefficient between the cell material and the electrode material, but also can play a role of local doping on the contact position of the cell and the electrode through doping elements, and the series resistance of an emitter and the grid line is reduced, thereby realizing the effect of improving the cell filling factor and the cell efficiency.
The silicon heterojunction solar cell according to the embodiment of the present invention is explained below with reference to fig. 1 and 2, specifically as follows:
n-type crystalline silicon substrate layer 100: the substrate layer 100 provides an attached carrier for other structures of the solar cell according to embodiments of the present invention.
According to an embodiment of the invention, the thickness of the substrate layer 100 is 50-200 μm.
Lightly doped n-type hydrogenated amorphous silicon buffer layer 200: according to an embodiment of the present invention, the lightly doped n-type hydrogenated amorphous silicon buffer layer 200 is formed on both upper and lower side surfaces of the substrate layer 100. Therefore, the hydrogenated amorphous silicon buffer layer can repair dangling bonds in the deposited silicon film by introducing hydrogen atoms, so that defects in crystal lattices are reduced, and on the premise that good interface passivation effect can be ensured by using the hydrogenated amorphous silicon layer to replace intrinsic amorphous silicon as a passivation layer, the allowable thickness range of the hydrogenated amorphous silicon layer is increased, so that a preparation process window is widened, the manufacturing difficulty of a battery is reduced, the series resistance is remarkably improved, and the performance of the battery is improved.
According to an embodiment of the invention, the lightly doped n-type hydrogenated amorphous silicon layerIs 10 in doping concentration 8 -10 17 /cm 3 。
According to an embodiment of the present invention, the thickness of the lightly doped n-type hydrogenated amorphous silicon buffer layer 200 is 1-15nm. Since the hydrogenated amorphous silicon buffer layer can integrate passivation effect and reduce potential barrier, the thickness of the hydrogenated amorphous silicon buffer layer can be allowed to be appropriately increased, so that the process difficulty can be reduced.
Heavily doped p-type hydrogenated amorphous silicon emitter layer 300: according to an embodiment of the present invention, the heavily doped p-type hydrogenated amorphous silicon emitter layer 300 is formed on the surface of the one-side lightly doped n-type hydrogenated amorphous silicon buffer layer 200, that is, the heavily doped p-type hydrogenated amorphous silicon emitter layer 300 is formed on one of the two outer surfaces of the hydrogenated amorphous silicon buffer layer 200.
According to an embodiment of the present invention, the thickness of the heavily doped p-type hydrogenated amorphous silicon emitter layer 300 is 5-25nm. The heavily doped p-type hydrogenated amorphous silicon emitter layer can be used to form a p-n junction built-in electric field with the n-type crystalline silicon substrate layer. As the emitter, the p layer with high carrier concentration has strong absorption to the short wave light, and the p-type B doping has more internal defects, so that the hole pairs formed by absorbed photons are easy to recombine at the defects, and the short wave light is lost, therefore, the amorphous silicon in the heavily doped p-type hydrogenated amorphous silicon emitter layer needs to have high enough doping concentration and small thickness as possible. On the other hand, if the thickness of the heavily doped p-type hydrogenated amorphous silicon emitter layer is too small, carriers in a large part of the region of the heavily doped p-type hydrogenated amorphous silicon emitter layer may be depleted due to being located near the p-n junction, influencing the output of current, and by disposing the first lightly doped n-type hydrogenated amorphous silicon layer between the heavily doped p-type hydrogenated amorphous silicon emitter layer and the n-type crystalline silicon substrate, the influence of depletion of carriers may be effectively reduced, thereby further improving the performance of the battery.
Heavily doped n-type hydrogenated amorphous silicon back surface field layer 400: the hydrogenated amorphous silicon back surface field layer 400 is formed on the surface of the other side lightly doped n-type hydrogenated amorphous silicon buffer layer 200 according to an embodiment of the present invention. That is, the heavily doped n-type hydrogenated amorphous silicon back surface layer 400 is formed on the other of the two outer surfaces of the hydrogenated amorphous silicon buffer layer.
Therefore, an electric field formed between the heavily doped n-type hydrogenated amorphous silicon back surface field layer and the n-type crystalline silicon substrate layer can help carriers to be effectively transferred to the conductive layer, and a lightly doped n-type hydrogenated amorphous silicon buffer layer arranged between the heavily doped n-type hydrogenated amorphous silicon back surface field layer and the n-type crystalline silicon substrate layer can reduce carrier recombination, so that the performance of the battery is improved.
According to an embodiment of the present invention, the heavily doped n-type hydrogenated amorphous silicon back surface field layer 300 has a thickness of 5-25nm. Thus, the recombination of carriers on the cell surface is significantly reduced, and the efficiency of the solar cell is higher.
Transparent conductive oxide layer 500: the transparent conductive oxide layer 500 is formed on the surfaces of the heavily doped p-type hydrogenated amorphous silicon emitter layer 300 and the heavily doped n-type hydrogenated amorphous silicon back surface field layer 400 according to an embodiment of the present invention.
It should be emphasized that the transparent conductive oxide layer 500 may be formed on the entire surfaces of the hydrogenated amorphous silicon emitter layer 300 and the hydrogenated amorphous silicon back surface field layer 400, i.e., entirely covering the surfaces of the hydrogenated amorphous silicon emitter layer 300 and the hydrogenated amorphous silicon back surface field layer 400, or may be formed on a portion of the surfaces of the hydrogenated amorphous silicon emitter layer 300 and the hydrogenated amorphous silicon back surface field layer 400, i.e., only covering a portion of the surfaces of the hydrogenated amorphous silicon emitter layer 300 and the hydrogenated amorphous silicon back surface field layer 400, and the remaining portion may be covered by the transition metal layer.
Metal gate line electrode layer 600: according to an embodiment of the present invention, the metal gate line electrode layer 600 includes: an alloy transition layer 610 and a copper-containing conductive alloy layer 620, wherein the alloy transition layer 610 is formed on a surface of at least one of the transparent conductive oxide layer 500, the hydrogenated amorphous silicon back surface field layer 400 and the heavily doped p-type hydrogenated amorphous silicon emitter layer 300, and the copper-containing conductive alloy layer 620 is formed on a surface of the alloy transition layer 610. The alloy transition layer 610 of the solar cell may be formed on the transparent conductive oxide layer 500, the hydrogenated amorphous silicon back surface field layer 400, or the heavily doped p-type hydrogenated amorphous silicon emitter layer 300, or may be formed on any two or three layers thereof, respectively. Therefore, the alloy transition layer not only can increase the adhesive force of the electrode on the surface of the battery and improve the matching degree of the thermal expansion coefficient between the battery material and the electrode material, but also can play a role of local doping on the contact position of the battery and the electrode through doping elements and reduce the series resistance of the emitter and the grid line, thereby realizing the effect of improving the battery filling factor and the battery efficiency, greatly reducing the use of noble metals such as Ag and the like while keeping lower resistivity, and the oxidation resistance, corrosion resistance and the like of single metal can be effectively improved by alloying to a certain extent, and the environmental stability of the electrode is enhanced.
According to an embodiment of the present invention, the transparent conductive oxide layer 500 has a thickness of 50-300nm.
According to an embodiment of the present invention, the alloy transition layer 610 contains at least two metals selected from Cu, mo, W, ti, ni, cr, al, mg, ta, sn, zn and Ag. According to a preferred embodiment of the present invention, the alloy transition layer 610 contains a Ni-Cu-Sn alloy, a Ni-Cu-In alloy, or a Ni-Al alloy, wherein Ni In the alloy can provide good adhesion to silicon, cu In the Ni-Cu-Sn or Ni-Cu-In alloy can reduce the resistivity of the alloy electrode and provide a base layer for subsequent electroplating, sn In the Ni-Cu-Sn alloy can form ohmic contact with tin-doped indium oxide, and group iii element Al In the Ni-Al alloy can form good contact with the p-type hydrogenated amorphous silicon emitter layer after annealing diffusion, reducing the resistivity. Further, according to an embodiment of the present invention, the Ni-Cu-Sn alloy contains 30 to 50 mass% of Ni,35 to 55 mass% of Cu and 15 to 25 mass% of Sn, the Ni-Cu-In alloy contains 30 to 50 mass% of Ni,35 to 55 mass% of Cu and 15 to 25 mass% of In, and the Ni-Al alloy contains 3 to 6 mass% of Al and 94 to 97 mass% of Ni. Therefore, the alloy has a lower melting point, and is favorable for forming an alloy electrode with good performance in subsequent low-temperature heat treatment.
The alloy transition layer 610 may further contain at least one element selected from B, P, ga and In according to an embodiment of the present invention. Therefore, the element plays a role in local doping on the contact position of the battery body and the electrode, and the series resistance of the emitter/back field and the grid line is reduced.
According to an embodiment of the present invention, the thickness of the alloy transition layer 610 is 5-300nm.
According to an embodiment of the present invention, the copper-containing conductive alloy layer 620 contains Cu and at least one metal selected from Mo, W, ti, ni, cr, al, mg, ta, sn, zn and Ag. Thus, by selecting an appropriate metal to alloy with Cu, the weather resistance of the electrode is significantly improved while not substantially affecting the electrical conductivity.
According to an embodiment of the present invention, the copper-containing conductive alloy layer 620 may further contain at least one element selected from B, P, ga and In. The copper-containing conductive alloy layer 620 has a thickness of 1-100 μm in accordance with an embodiment of the present invention.
According to an embodiment of the present invention, the copper content of the copper-containing conductive alloy layer 620 is graded from the near alloy transition layer 610 end to the far alloy transition layer 610 end, and the copper content of the near alloy transition layer 610 end is 85% -99% wt, and the copper content of the far alloy transition layer 610 end is 99% -100% wt.
According to an embodiment of the present invention, the resistivity of the metal gate line electrode layer 600 is not more than 1.5X10 -5 Omega cm. Therefore, the metal gate line electrode layer and the transparent conductive oxide layer form good ohmic contact, and have good corrosion resistance and oxidation resistance.
According to another aspect of the present invention, there is provided a method of preparing the aforementioned silicon heterojunction solar cell. Referring to fig. 3, the method of manufacturing the aforementioned solar cell according to an embodiment of the present invention will be explained, and includes:
s100 provides n-type crystalline silicon substrate layer
According to an embodiment of the present invention, an n-type crystalline silicon substrate layer 100 is provided. Specifically, the substrate layer 100 is cleaned, and a textured structure is formed on the upper and lower surfaces of the substrate layer 100.
The kind of the crystalline silicon in the n-type crystalline silicon substrate layer is not particularly limited according to the embodiment of the present invention, and a person skilled in the art may select according to actual needs, and according to the embodiment of the present invention, the n-type crystalline silicon substrate layer 100 is an n-type monocrystalline silicon substrate or an n-type polycrystalline silicon substrate.
S200 forming a lightly doped n-type hydrogenated amorphous silicon buffer layer
According to an embodiment of the present invention, lightly doped n-type hydrogenated amorphous silicon buffer layers 200 are formed on upper and lower both side surfaces of the n-type crystalline silicon substrate layer 100. Specifically, the hydrogenated amorphous silicon buffer layer 200 is formed using a chemical vapor deposition method according to an embodiment of the present invention. The lightly doped n-type hydrogenated amorphous silicon buffer layer 200 can reduce defects in the crystal lattice by introducing hydrogen atoms to repair dangling bonds in the deposited silicon film.
S300 forming a heavily doped p-type hydrogenated amorphous silicon emitter layer
According to an embodiment of the present invention, a heavily doped p-type hydrogenated amorphous silicon emitter layer 300 is formed on the surface of the one side lightly doped n-type hydrogenated amorphous silicon layer 200.
S400 forming a heavily doped n-type hydrogenated amorphous silicon back surface field layer
According to an embodiment of the present invention, a heavily doped n-type hydrogenated amorphous silicon back surface field layer 400 is formed on the surface of the other side lightly doped n-type hydrogenated amorphous silicon buffer layer 200.
S500 formation of transparent conductive oxide layer
According to an embodiment of the present invention, a transparent conductive oxide layer 500 is formed on the surfaces of the heavily doped p-type hydrogenated amorphous silicon emitter layer 300 and the heavily doped n-type hydrogenated amorphous silicon back surface field layer 400. According to an embodiment of the present invention, the kinds of the two transparent conductive oxide layers 500 on the surfaces of the heavily doped p-type hydrogenated amorphous silicon emitter layer 300 and the heavily doped n-type hydrogenated amorphous silicon back surface field layer 400 may be the same or different.
According to an embodiment of the present invention, the hydrogenated amorphous silicon buffer layer 200, the hydrogenated amorphous silicon emitter layer 300, the hydrogenated amorphous silicon back surface field layer 400, and the transparent conductive oxide layer 500 are formed by ion-enhanced chemical vapor deposition, hot filament chemical vapor deposition, microwave plasma chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition.
S600 forming a metal gate line electrode layer
A metal gate electrode layer 600 is formed on the surface of at least one of the transparent conductive oxide layer 500, the hydrogenated amorphous silicon back surface field layer 400, and the heavily doped p-type hydrogenated amorphous silicon emitter layer 300, wherein the metal gate electrode layer contains an alloy transition layer 610 and a copper-containing conductive alloy layer 620.
According to an embodiment of the present invention, the alloy transition layer 610 is formed using a physical vapor deposition method. According to a preferred embodiment of the present invention, the alloy transition layer 610 is formed by physical vapor deposition, evaporation deposition, and/or sputtering deposition.
In accordance with an embodiment of the present invention, copper-containing conductive alloy layer 620 is formed using an electroplating process.
To facilitate understanding of the method of forming the metal gate line electrode layer, an example method of forming the metal gate line electrode layer is provided herein:
(1-a) depositing an alloy metal on the surface of at least one of the transparent conductive oxide layer 500, the hydrogenated amorphous silicon back surface field layer 400, and the heavily doped p-type hydrogenated amorphous silicon emitter layer 300, forming an alloy transition layer 610.
According to an embodiment of the invention, the alloying metal is a Ni-Cu-Sn alloy or a Ni-Cu-In alloy.
According to an embodiment of the present invention, the alloy transition layer 610 is formed using a deposition method, including but not limited to Physical Vapor Deposition (PVD).
(1-b) forming a mask layer 630 of a predetermined pattern on the surface of the alloy transition layer 610 using a photoresist film.
The material of the mask layer 630 is not particularly limited, but must be electrically insulating according to an embodiment of the present invention.
According to an embodiment of the present invention, a part of the alloy transition layer is etched away by a chemical agent using a photolithography method and a mask having a grid electrode pattern to form an opening position where the alloy metal contacts the transparent conductive oxide layer, and then the photoresist film is cured by a heat treatment to form a mask layer.
(1-c) a copper-containing conductive alloy layer 620 is formed on the surface of the alloy transition layer 610, specifically, at the location of the opening where the alloy metal contacts the transparent conductive oxide layer. Since the mask layer is electrically insulating, by electroplating, a copper-containing conductive alloy layer can only be formed at the location of the opening in the mask layer.
(1-d) removing the mask layer 630 and the alloy transition layer 610 covered by the mask layer 630 to form a metal gate line electrode layer intermediate. It should be noted that during the removal of the alloy transition layer 610, a certain corrosion effect on the formed copper-containing conductive alloy layer is unavoidable. Since the thickness of the copper-containing conductive alloy layer 620 is much greater than the alloy transition layer 610, the corrosion is relatively slight and does not adversely affect the performance of the subsequent electrode.
(1-e) annealing the intermediate of the metal gate line electrode layer to obtain the metal gate line electrode layer 600. Specifically, the annealing treatment is performed in a protective atmosphere.
According to an embodiment of the invention, the annealing treatment is carried out at a temperature of 125-350 ℃ for 15-60 minutes. Therefore, the annealing efficiency is high, and the effect is good.
In the metal gate electrode layer 600, the copper content is graded from 96% -99% wt near the transparent conductive oxide layer to 99-100% wt on top of the metal gate electrode layer, according to an embodiment of the present invention.
For a further understanding of the method of forming the metal gate electrode layer, referring to fig. 4, an exemplary method of forming the metal gate electrode layer 600 is provided herein:
(2-a) removing a portion of the transparent conductive oxide layer 500 to form the transparent conductive oxide layer 500 having a predetermined pattern, wherein the transparent conductive oxide layer 500 is the transparent conductive oxide layer 500 of the near heavily doped p-type hydrogenated amorphous silicon emitter layer 300. The method for forming the transparent conductive oxide layer 500 near the side of the amorphous silicon back surface field layer 400 is as described in the above steps (1-a) - (1-e).
According to an embodiment of the present invention, the transparent conductive oxide layer is removed using photolithography or wet etching.
Note that, the transparent conductive oxide layer 500 may be the transparent conductive oxide layer 500 of the near-hydrogenated amorphous silicon back surface field layer 400, that is, the alloy transition layer 610 may be formed on the hydrogenated amorphous silicon back surface field layer 400.
(2-b) depositing an alloy metal on the surfaces of the transparent conductive oxide layer 500 and the hydrogenated amorphous silicon emitter layer 300 having a predetermined pattern, forming an alloy transition layer 610.
According to an embodiment of the invention, the alloy metal is a ni—al alloy. Thus, after the group III element Al is annealed and diffused, good contact can be formed with the p-type hydrogenated amorphous silicon emitter layer 300, and the resistivity is reduced.
(2-c) a mask layer 630 is formed on the surface of the alloy transition layer 610 above the transparent conductive oxide layer 500.
The material of the mask layer 630 is not particularly limited, but must be electrically insulating according to an embodiment of the present invention.
(2-d) forming a copper-containing conductive alloy layer 620 on the surface of the alloy transition layer 610 above the hydrogenated amorphous silicon emitter layer 300, forming a metal gate line electrode layer intermediate.
(2-e) removing the mask layer 630 and the alloy transition layer 610 covered by the mask layer 630 so as to form a metal gate line electrode layer intermediate. Also, during removal, some etching of the formed copper-containing conductive alloy layer is unavoidable. Since the thickness of the copper-containing conductive alloy layer is much higher than the alloy transition layer, the corrosion is relatively slight and does not adversely affect the performance of the subsequent electrode.
(2-f) annealing the metal gate line electrode layer intermediate to obtain the metal gate line electrode layer 600. The annealing treatment is the same as (1-e), and will not be described in detail here.
In the metal gate electrode layer 600, the copper content is graded from 85-95% wt near the transparent conductive oxide layer to 95% -100% wt on top of the metal gate electrode layer, according to an embodiment of the present invention.
It should be noted that, the above two metal gate electrode layers are used for manufacturing the double-sided electrode of the silicon heterojunction battery, and similar technical routes can also be used for manufacturing the single-sided electrode of the silicon heterojunction battery. It will be apparent to those skilled in the art that many more modifications besides those already described are possible without the invention being limited to the details and limitations of the invention.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.
Claims (14)
1. A silicon heterojunction solar cell, comprising:
an n-type crystalline silicon substrate layer;
the lightly doped n-type hydrogenated amorphous silicon buffer layer is formed on the upper side surface and the lower side surface of the n-type crystalline silicon substrate layer;
a heavily doped p-type hydrogenated amorphous silicon emitter layer formed on a surface of the lightly doped n-type hydrogenated amorphous silicon buffer layer at one side;
the heavily doped n-type hydrogenated amorphous silicon back surface field layer is formed on the surface of the lightly doped n-type hydrogenated amorphous silicon buffer layer at the other side;
a transparent conductive oxide layer formed on surfaces of the heavily doped p-type hydrogenated amorphous silicon emitter layer and the heavily doped n-type hydrogenated amorphous silicon back surface field layer;
a metal gate line electrode layer, the metal gate line electrode layer comprising:
an alloy transition layer formed on a surface of at least one of the transparent conductive oxide layer, the heavily doped n-type hydrogenated amorphous silicon back surface field layer, and the heavily doped p-type hydrogenated amorphous silicon emitter layer;
a copper-containing conductive alloy layer formed on a surface of the alloy transition layer;
the alloy transition layer contains at least two metals selected from Cu, mo, W, ti, ni, cr, al, mg, ta, sn, zn and Ag,
the copper-containing conductive alloy layer contains Cu and at least one metal selected from Mo, W, ti, ni, cr, al, mg, ta, sn, zn and Ag;
the thickness of the alloy transition layer is 5-300 a nm a,
the thickness of the copper-containing conductive alloy layer is 1-100 mu m.
2. The silicon heterojunction solar cell of claim 1, wherein the doping concentration of the lightly doped n-type hydrogenated amorphous silicon buffer layer is 10 8 -10 17 /cm 3 。
3. The silicon heterojunction solar cell according to claim 1, wherein the alloy transition layer further contains at least one element selected from B, P, ga and In,
and/or the copper-containing conductive alloy layer further contains at least one element selected from B, P, ga and In.
4. The silicon heterojunction solar cell of claim 1, wherein the copper content of the copper-containing conductive alloy layer is graded from near the alloy transition layer end to far the alloy transition layer end, and the copper content near the alloy transition layer end is 85% -99% wt, and the copper content far the alloy transition layer end is 99% -100% wt.
5. The silicon heterojunction solar cell of claim 1, wherein the metal gateThe resistivity of the wire electrode layer is not more than 1.5X10 -5 Ω∙cm。
6. The silicon heterojunction solar cell of claim 1, wherein the thickness of the n-type crystalline silicon substrate layer is 50-200 μm,
and/or the thickness of the lightly doped n-type hydrogenated amorphous silicon buffer layer is 1-15nm,
and/or the thickness of the heavily doped p-type hydrogenated amorphous silicon emitter layer is 5-25nm,
and/or the thickness of the heavily doped n-type hydrogenated amorphous silicon back surface field layer is 5-25nm,
and/or the thickness of the transparent conductive oxide layer is 50-300nm.
7. A method of making the silicon heterojunction solar cell of any one of claims 1-6, comprising:
providing an n-type crystalline silicon substrate layer;
forming lightly doped n-type hydrogenated amorphous silicon buffer layers on the upper side surface and the lower side surface of the n-type crystalline silicon substrate layer;
forming a heavily doped p-type hydrogenated amorphous silicon emitter layer on the surface of the lightly doped n-type hydrogenated amorphous silicon buffer layer at one side;
forming a heavily doped n-type hydrogenated amorphous silicon back surface field layer on the surface of the lightly doped n-type hydrogenated amorphous silicon buffer layer at the other side;
forming transparent conductive oxide layers on the surfaces of the heavily doped p-type hydrogenated amorphous silicon emitter layer and the heavily doped n-type hydrogenated amorphous silicon back surface field layer respectively; and
and forming a metal gate line electrode layer on the surface of at least one layer of the transparent conductive oxide layer, the heavily doped n-type hydrogenated amorphous silicon back surface field layer and the heavily doped p-type hydrogenated amorphous silicon emitter layer, wherein the metal gate line electrode layer comprises an alloy transition layer and a copper-containing conductive alloy layer.
8. The method of claim 7, wherein the lightly doped n-type hydrogenated amorphous silicon buffer layer, the heavily doped p-type hydrogenated amorphous silicon emitter layer, and the heavily doped n-type hydrogenated amorphous silicon back surface field layer are each formed by ion-enhanced chemical vapor deposition, hot filament chemical vapor deposition, microwave plasma chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition,
and/or, the alloy transition layer is formed by adopting a physical vapor deposition method,
and/or, the copper-containing conductive alloy layer is formed by adopting an electroplating method.
9. The method of claim 8, wherein the physical vapor deposition method is an evaporation deposition method and a sputtering deposition method.
10. The method of claim 8, wherein the method of forming the metal gate line electrode layer comprises:
depositing an alloy metal on the surface of at least one of the transparent conductive oxide layer, the heavily doped n-type hydrogenated amorphous silicon back surface field layer and the heavily doped p-type hydrogenated amorphous silicon emitter layer so as to form an alloy transition layer;
forming a mask layer of a predetermined pattern on the surface of the alloy transition layer by using a photoresist film;
forming the copper-containing conductive alloy layer on the surface of the alloy transition layer, wherein the copper-containing conductive alloy layer and the mask layer are arranged in a crossing manner;
removing the mask layer and the alloy transition layer covered by the mask layer so as to form a metal gate line electrode layer intermediate;
and annealing the intermediate of the metal gate line electrode layer to obtain the metal gate line electrode layer.
11. The method of claim 10, wherein the alloying metal is a Ni-Cu-Sn alloy or a Ni-Cu-In alloy.
12. The method of claim 10, wherein the transparent conductive oxide layer is the transparent conductive oxide layer near the heavily doped n-type hydrogenated amorphous silicon back surface field layer end or the heavily doped p-type hydrogenated amorphous silicon emitter layer end.
13. The method of claim 8, wherein the method of forming the metal gate line electrode layer comprises:
removing a portion of the transparent conductive oxide layer to form a transparent conductive oxide layer having a predetermined pattern, wherein the transparent conductive oxide layer is the transparent conductive oxide layer proximate to the heavily doped p-type hydrogenated amorphous silicon emitter layer;
depositing an alloy metal on surfaces of the transparent conductive oxide layer having a predetermined pattern and the heavily doped p-type hydrogenated amorphous silicon emitter layer so as to form an alloy transition layer;
forming a mask layer on the surface of the alloy transition layer above the transparent conductive oxide layer;
forming the copper-containing conductive alloy layer on the surface of the alloy transition layer above the heavily doped p-type hydrogenated amorphous silicon emitter layer, wherein the copper-containing conductive alloy layer is arranged in a crossing manner with the mask layer;
removing the mask layer and the alloy transition layer covered by the mask layer so as to form a metal gate line electrode layer intermediate;
and annealing the intermediate of the metal gate line electrode layer to obtain the metal gate line electrode layer.
14. The method of claim 13, wherein the alloying metal is a Ni-Al alloy.
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| CN113035972A (en) * | 2021-02-04 | 2021-06-25 | 苏州元昱新能源有限公司 | Heterojunction photovoltaic cell of grid line electrode made of silver-free slurry |
| CN113410328A (en) * | 2021-05-12 | 2021-09-17 | 北京工业大学 | Crystalline silicon heterojunction solar cell |
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