CN109144925B

CN109144925B - Universal serial bus circuit

Info

Publication number: CN109144925B
Application number: CN201810840739.1A
Authority: CN
Inventors: 林小琪; 林宜兴
Original assignee: Weifeng Electronics Co ltd
Current assignee: Weifeng Electronics Co ltd
Priority date: 2018-07-27
Filing date: 2018-07-27
Publication date: 2020-07-28
Anticipated expiration: 2038-07-27
Also published as: CN109144925A

Abstract

The invention provides a universal serial bus circuit which comprises a power supply circuit and a terminal circuit. The power circuit is used for providing differential signals. The terminal circuit is coupled to the power circuit. The termination circuit is used for receiving differential signals through the first signal output end and the second signal output end, and comprises a first load circuit and a second load circuit. When the USB circuit operates in a handshake mode, the termination circuit receives a differential signal through the first load circuit and the second load circuit, and outputs a pulse signal through the first signal output terminal and the second signal output terminal. When the USB circuit operates in a normal mode, the termination circuit receives the differential signal through the first load circuit and outputs a data signal through the first signal output terminal and the second signal output terminal.

Description

Universal serial bus circuit

Technical Field

The present invention relates to a Bus circuit, and more particularly, to a Universal Serial Bus (USB) circuit.

Background

Generally, Universal Serial Bus (USB) 2.0 supports full Speed (fullseed) and High Speed (High Speed) data transfer. Under the specification of the USB2.0 standard, when the USB device as the host is coupled to the device, the device and the USB device will first perform a Handshake (Handshake) mode to confirm the data transmission capabilities of each other. That is, before the data signal is transmitted, the USB device as the master device alternately transmits the negative pulse signal and the positive pulse signal to the device, so that the device can effectively determine whether the USB device supports high-speed data transmission. In other words, when the device-side apparatus fails to respond to the negative pulse signal and the positive pulse signal alternately transmitted by the USB device, the device-side apparatus will confirm that the data transmission between the USB device and the device-side apparatus will only operate at full speed. Otherwise, the device-side equipment will confirm that the data transmission operation between the USB device and the device-side equipment is high-speed data transmission.

However, the terminal circuit of the general USB circuit receives the differential signal provided by the current source through only two switching transistors and outputs the pulse signal and the data signal to the device terminal, so that the switching transistors of the general terminal circuit need to bear larger current during the handshake mode, so that the switching transistors of the terminal circuit may operate in a Saturation region (Saturation region), and a non-linear region (L initial region), so that the Chirp K signal and the Chirp J signal generated by the general USB device may have unstable or voltage drift.

Disclosure of Invention

The invention provides a Universal Serial Bus (USB) circuit which can effectively generate pulse signals (Chirp K signals and Chirp J signals) and data signals and is suitable for USB2.0 High-Speed (High Speed) transmission.

The universal serial bus circuit of the invention comprises a power supply circuit and a terminal circuit. The power circuit is used for providing differential signals. The terminal circuit is coupled to the power circuit. The terminal circuit is used for receiving the differential signal through the first signal output end and the second signal output end. The termination circuit includes a first load circuit and a second load circuit. When the USB circuit operates in a normal mode, the termination circuit receives the differential signal through the first load circuit and outputs a data signal through the first signal output terminal and the second signal output terminal. When the USB circuit operates in a handshake mode, the termination circuit receives a differential signal through the first load circuit and the second load circuit, and outputs a pulse signal through the first signal output terminal and the second signal output terminal.

Based on the above, the USB circuit of the present invention can support USB2.0 high-speed transmission, and can effectively provide pulse signals (Chirp K signal and Chirp J signal) and data signals through the termination circuit. In addition, the universal serial bus circuit of the invention also has the efficacy of effectively reducing the power consumption of the USB circuit and reducing the circuit area.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic diagram of a universal serial bus circuit according to an embodiment of the invention.

Fig. 2 is a circuit diagram of a universal serial bus circuit according to an embodiment of the invention.

Fig. 3 is a signal waveform diagram of the pulse signal according to the embodiment of fig. 2.

Fig. 4 is a signal waveform diagram of a data signal according to the embodiment of fig. 2.

Fig. 5 is a circuit diagram of a universal serial bus circuit according to another embodiment of the invention.

Fig. 6 is a circuit diagram of a universal serial bus circuit according to yet another embodiment of the present invention.

Fig. 7 is a signal waveform diagram of a pulse signal according to the embodiment of fig. 6.

Description of the symbols:

100. 300, 500, 700: universal serial bus circuit

110. 310, 510, 710: power supply circuit

120. 320, 520, 720: terminal circuit

121. 321, 521, 721: a first load circuit

122. 322, 522, 722: second load circuit

200. 400 and 600: device end circuit

301. 302, 701, 702: pulse signal

401. 402, a step of: data signal

323. 324, 523, 524: diode unit

330. 530 and 730: pull-down circuit

540. 740: protective circuit

M1, M1 ', M2, M2', M3, M4, M5, M5 ', M6, M6', M7, M8, M9, M10: transistor with a metal gate electrode

R1, R2, R3, R4, R5, R6, Rp, Ra, Rb: resistance (RC)

S1, S2, S3: switch with a switch body

I1, I2: current source

DP and DM: signal output terminal

Detailed Description

In order that the present invention may be more readily understood, the following detailed description is provided as an illustration of specific embodiments of the invention. Further, wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic diagram of a universal serial bus circuit according to an embodiment of the invention. Referring to fig. 1, a Universal Serial Bus (USB) circuit 100 includes a power circuit 110 and a termination circuit 120. The power circuit 110 is coupled to the termination circuit 120. In the present embodiment, the termination circuit 120 includes a first load circuit 121 and a second load circuit 122. The power circuit 110 is coupled to the first load circuit 121 and the second load circuit 122 via the signal output terminals DP and DM. The power supply circuit 110 is configured to selectively provide a Differential (Differential) signal to the first load circuit 121 and the second load circuit 122.

In the embodiment, the USB circuit 100 can support USB2.0 High Speed (High Speed) transmission. Therefore, when the USB circuit 100 is coupled to an external device terminal through the signal output terminals DP and DM and the USB circuit 100 operates in a Handshake (Handshake) mode, the USB circuit 100 outputs a pulse signal to the external device terminal through the signal output terminals DP and DM. The pulse signal is a signal in which the USB circuit 100 outputs a plurality of negative pulse signals (Chirp K signals) and a plurality of positive pulse signals (Chirp J signals) through the signal output terminals DP and DM, and the negative pulse signals (Chirp K signals) and the positive pulse signals (Chirp J signals) are alternately arranged. The voltage of the positive pulse signal (Chirp J signal) can be between 700 and 1100 millivolts (mV), and the voltage of the negative pulse signal can be between-900 and-500 mV. That is, when the external device receives the positive pulse signal (Chirp J signal) and the negative pulse signal (Chirp K signal) alternately output by the USB circuit 100, the external device can effectively confirm that the USB circuit 100 can support USB2.0 high-speed transmission, so that the data transmission between the USB circuit 100 and the external device can operate at a transmission speed of 480 megabits per second (Mbps).

In the embodiment, the USB circuit 100 receives the differential signal output by the power circuit 110 through the first load circuit 121 and the second load circuit 122, and outputs the corresponding pulse signal and the data signal. Specifically, when the USB circuit 100 operates in the handshake mode, the termination circuit 120 receives the differential signal through the first load circuit 121 and the second load circuit 122, and alternately outputs a positive pulse signal (Chirp J signal) and a negative pulse signal (Chirp K signal) to the external device terminal through the signal output terminals DP and DM. However, when the USB circuit 100 operates in the normal mode (or data transmission mode), the termination circuit 120 only receives the differential signal outputted from the power circuit 110 through the first load circuit 121 and outputs the data signal to the external device through the signal output terminals DP and DM.

Fig. 2 is a circuit diagram of a universal serial bus circuit according to an embodiment of the invention. Referring to fig. 2, the USB circuit 300 includes a power circuit 310, a termination circuit 320, and a pull-down circuit 330. The termination circuit 320 includes a first load circuit 321 and a second load circuit 322. The USB circuit 300 is coupled to the device side circuit 200 via the signal output terminals DP and DM. In the present embodiment, the device side circuit 200 refers to an equivalent circuit of a USB connection port of a computer apparatus, for example, but the invention is not limited thereto. In the present embodiment, the device-side circuit 200 may include a pull-up resistor Rp and reference resistors Ra and Rb. Pull-up resistor Rp is coupled to switch S1. One end of the reference resistor Ra is coupled to the switch S2, and the other end of the reference resistor Ra is coupled to the ground. One end of the reference resistor Rb is coupled to the switch S3, and the other end of the reference resistor Ra is coupled to the ground.

The power supply circuit 310 includes a current source circuit and transistors M1, M2. The current source circuit includes an input-output power supply (I/O power) I1, and the input-output power supply I1 may provide a power supply signal of 3.3 volts (V), for example. The first terminal of the transistor M1 is coupled to the input/output power source I1. The second terminal of the transistor M1 is coupled to the signal output terminal DP. The first terminal of the transistor M2 is coupled to the input/output power source I1. The second terminal of the transistor M2 is coupled to the signal output terminal DM. In the present embodiment, the second terminal of the transistor M1 and the second terminal of the transistor M2 may alternately output the power signal provided by the input/output power source I1 via the signal output terminals DP and DM to form a differential signal.

The first load circuit 321 includes resistors R1, R2 and transistors M3, M4. A first terminal of the resistor R1 is coupled to the signal output terminal DP. In this embodiment, the first terminal of the transistor M3 is coupled to the second terminal of the resistor R1, and the second terminal of the transistor M3 is coupled to the Ground (Ground). A first terminal of the resistor R2 is coupled to the second signal output terminal DM. The first terminal of the transistor M4 is coupled to the second terminal of the resistor R2, and the second terminal of the transistor M4 is coupled to the ground terminal.

The second load circuit 322 includes resistors R3, R4,

diode units

323, 324, and transistors M5, M6. In this embodiment, the first terminal of the resistor R3 is coupled to the signal output terminal DP. Diode unit 323 is coupled to a second terminal of resistor R3. The first terminal of the transistor M5 is coupled to the diode unit 323, and the second terminal of the transistor M5 is coupled to the ground terminal. A first terminal of the resistor R4 is coupled to the signal output terminal DM. The diode unit 324 is coupled to the second terminal of the resistor R4. The first terminal of the transistor M6 is coupled to the diode unit 324, and the second terminal of the transistor M6 is coupled to the ground terminal. In the present embodiment, the diode unit 323 may include a transistor M7, and the diode unit 324 may include a transistor M8. The first terminal of the transistor M7 is coupled to the resistor R3. The control terminal of the transistor M7 is coupled to the first terminal of the transistor M7. The second terminal of the transistor M7 is coupled to the first terminal of the transistor M5. The first terminal of the transistor M8 is coupled to the resistor R4. The control terminal of the transistor M8 is coupled to the first terminal of the transistor M8. The second terminal of the transistor M8 is coupled to the first terminal of the transistor M6. However, the

diode units

323 and 324 may be other diode circuits, and the

diode units

323 and 324 of the present invention are not limited to fig. 2. In addition, the pull-down circuit 330 includes resistors R5, R6, and the resistors R5, R6 may be 15k ohms (Ohm).

In the present embodiment, when the USB circuit 300 is coupled to the device-side circuit 200 via the signal output terminals DP and DM, the USB circuit 300 serves as a Host (Host) and outputs a USB Reset (Reset) signal to the device-side circuit 200. The device-side circuit 200 supports USB2.0 high-speed transmission, and therefore the device-side circuit 200 then outputs a negative pulse signal (Chirp K signal) to the USB circuit 300, so that the USB circuit 300 confirms that the device-side circuit 200 supports USB2.0 high-speed transmission. Then, the USB circuit 300 alternately returns the negative pulse signal (Chirp K signal) and the positive pulse signal (Chirp J signal) to the device-side circuit 200, so that the device-side circuit 200 can effectively confirm that the USB circuit 300 supports USB2.0 high-speed transmission. Finally, the USB circuit 300 may enter the normal mode and output the data signal to the device-side circuit 200.

Fig. 3 is a signal waveform diagram of the pulse signal according to the embodiment of fig. 2. Referring to fig. 2 and 3, when the USB circuit 300 operates in the handshake mode, the USB circuit 300 may output the alternating positive pulse signal 301 and the negative pulse signal 302 shown in fig. 3 to the device-side circuit 200 via the signal output terminals DP and DM. Specifically, when the USB circuit 300 operates in the handshake mode, the switches S2, S3 of the device-side circuit 200 are not turned on, so that the terminal circuit 320 is subjected to a large current. Therefore, the USB circuit 300 outputs the positive pulse signal 301 and the negative pulse signal 302 to the device-side circuit 200 through the signal output terminals DP and DM. In this embodiment, the peak voltage of the positive pulse signal 301 may be 900mV, and the peak voltage of the negative pulse signal 302 may be-800 mV.

In other words, when the USB circuit 300 operates in the handshaking mode, the termination circuit 320 of the present embodiment can effectively prevent the transistors M3 and M4 of the first load circuit 321 from carrying too much current, so that the transistors M3 and M4 enter the Saturation region (Saturation region) from the linear region (L initial region) to shift the voltages of the pulse signals (Chirp K signal and Chirp J signal) output by the signal output terminals DP and DM.

Fig. 4 is a signal waveform diagram of a data signal according to the embodiment of fig. 2. Referring to fig. 2 and 4, when the USB circuit 300 operates in the normal mode, the switches S2 and S3 of the device-side circuit 200 are turned on, so that the terminal circuit 320 and the reference voltages Ra and Rb of the device-side circuit 200 share the current. The USB circuit 300 will alternately output the data signals 401, 402 shown in fig. 4 to the device-side circuit 200 through the signal output terminals DP, DM. The data signals 401, 402 form differential signals. The voltage peak of data signal 401 may be 400mV and the voltage peak of data signal 402 may be-400 mV. That is, the transistors M3 and M4 and the switches S2 and S3 are turned on, so that the first load circuit 321 and the reference voltages Ra and Rb can receive the current provided by the input/output power source I1. At this time, the transistors M7 and M8 are not turned on because the voltages of the signal output terminals DP and DM are small. Therefore, when the USB circuit 300 operates in the normal mode, the current provided by the input/output power source I1 does not flow through the second load circuit 322.

Fig. 5 is a circuit diagram of a universal serial bus circuit according to another embodiment of the invention. Referring to fig. 5, the USB circuit 500 includes a power supply circuit 510, a termination circuit 520, a pull-down circuit 530, and a protection circuit 540. The termination circuit 520 includes a first load circuit 521 and a second load circuit 522. The USB circuit 500 is coupled to the device-side circuit 400 via the signal output terminals DP and DM. In the present embodiment, the device-side circuit 400 refers to an equivalent circuit of a USB connection port of a computer device, for example, but the invention is not limited thereto. In the present embodiment, the device-side circuit 400 includes, for example, a pull-up resistor Rp and reference resistors Ra and Rb. Pull-up resistor Rp is coupled to switch S1. One end of the reference resistor Ra is coupled to the switch S2, and the other end of the reference resistor Ra is coupled to the ground. One end of the reference resistor Rb is coupled to the switch S3, and the other end of the reference resistor Rb is coupled to the ground terminal.

The power supply circuit 510 includes a current source circuit and transistors M1 ', M2'. The current source circuit includes an input-output power supply I1 and a Core power supply (Core power) I2. The input-output power supply I1 may provide a power supply signal of 3.3V, for example, and the core power supply I2 may provide a power supply signal of 1.05V, for example. The first terminal of the transistor M1' is coupled to the input/output power source I1 and the core power source I2. The second terminal of the transistor M1' is coupled to the signal output terminal DP. The first terminal of the transistor M2' is coupled to the input/output power source I1 and the core power source I2. The second terminal of the transistor M2' is coupled to the signal output terminal DM. In the present embodiment, the second terminal of the transistor M1 'and the second terminal of the transistor M2' may alternately output the power signals provided by the input/output power I1 or the core power I2 via the signal output terminals DP and DM to form a differential signal. It is noted that, compared to the power circuit 310 of the embodiment of fig. 2, the power circuit 510 of the embodiment includes two power sources, and the voltage of the input/output power source I1 is greater than that of the core power source I2. The input/output power I1 and the core power I2 can selectively output power signals via a controller (not shown).

The first load circuit 521 includes resistors R1, R2 and transistors M3, M4. A first terminal of the resistor R1 is coupled to the signal output terminal DP. In this embodiment, the first terminal of the transistor M3 is coupled to the second terminal of the resistor R1, and the second terminal of the transistor M3 is coupled to the ground terminal. A first terminal of the resistor R2 is coupled to the second signal output terminal DM. The first terminal of the transistor M4 is coupled to the second terminal of the resistor R2, and the second terminal of the transistor M4 is coupled to the ground terminal.

The second load circuit 522 includes resistors R3, R4,

diode units

523, 524, and transistors M5, M6. In this embodiment, the first terminal of the resistor R3 is coupled to the signal output terminal DP. Diode unit 523 is coupled to a second terminal of resistor R3. A first terminal of the transistor M5 is coupled to the diode unit 523, and a second terminal of the transistor M5 is coupled to the ground terminal. A first terminal of the resistor R4 is coupled to the signal output terminal DM. The diode unit 524 is coupled to a second terminal of the resistor R4. The first terminal of the transistor M6 is coupled to the diode unit 524, and the second terminal of the transistor M6 is coupled to the ground terminal. In the present embodiment, the diode unit 523 may include a transistor M7, and the diode unit 524 may include a transistor M8. The first terminal of the transistor M7 is coupled to the resistor R3. The control terminal of the transistor M7 is coupled to the first terminal of the transistor M7. The second terminal of the transistor M7 is coupled to the first terminal of the transistor M5. The first terminal of the transistor M8 is coupled to the resistor R4. The control terminal of the transistor M8 is coupled to the first terminal of the transistor M8. The second terminal of the transistor M8 is coupled to the first terminal of the transistor M6. However, the diode unit 523 and the diode unit 524 may be other diode circuits, and the diode unit 523 and the diode unit 524 of the present invention are not limited to fig. 5. In addition, the pull-down circuit 530 includes resistors R5, R6, and the resistors R5, R6 may be 15 kohms.

In the present embodiment, when the USB circuit 500 operates in the handshake mode, the power circuit 510 outputs the power signal to the first terminal of the transistor M1 'and the first terminal of the transistor M2' via the input/output power I1. When the USB circuit 500 operates in the normal mode, the power circuit 510 outputs the power signal to the first terminal of the transistor M1 'and the first terminal of the transistor M2' via the core power I2. However, the transistors M1 ', M2' are low voltage devices (coredevice) configured corresponding to the low voltage core power I2. In advanced manufacturing processes, in order to prevent the transistors M1 'and M2' from being damaged by the voltage of the signal output terminals DP and DM in the full-speed mode (the voltage is 0V to 3.3V), the USB circuit 500 of the present embodiment further includes a protection circuit 540.

The protection circuit 540 is coupled between the power circuit 510 and the termination circuit 520. The protection circuit 540 includes transistors M9, M10. A first terminal of the transistor M9 is coupled to the power circuit 510, and a second terminal of the transistor M9 is coupled to the termination circuit 520. A first terminal of the transistor M10 is coupled to the power circuit 510, and a second terminal of the transistor M10 is coupled to the termination circuit 520. Accordingly, when the signal output terminals DP and DM are in the full-speed mode, the voltage is between 0V and 3.3V, and the transistors M9 and M10 are turned off to protect the transistors M1 'and M2' from being damaged.

In the present embodiment, when the USB circuit 500 is coupled to the device-side circuit 400 through the signal output terminals DP and DM, the USB circuit 500 serves as a master and outputs a USB reset signal to the device-side circuit 400. The device-side circuit 400 supports USB2.0 high speed transmission, so the device-side circuit 400 then outputs a negative pulse signal (Chirp K signal) to the USB circuit 500, so that the USB circuit 500 confirms that the device-side circuit 400 supports USB2.0 high speed transmission. Then, the USB circuit 500 alternately returns the negative pulse signal (Chirp K signal) and the positive pulse signal (Chirp J signal) to the device-side circuit 400 according to the power signal provided by the input/output power I1, so that the device-side circuit 400 can effectively confirm that the USB circuit 500 supports USB2.0 high-speed transmission. Finally, the USB circuit 500 may enter the normal mode and output the data signal to the device-side circuit 400 according to the power signal provided by the core power I2.

Specifically, when the USB circuit 500 operates in the handshake mode, the switches S2 and S3 of the device side circuit 400 are not turned on, so that the termination circuit 520 receives a large current. The USB circuit 500 outputs a positive pulse signal (Chirp J signal) and a negative pulse signal (Chirp k signal) to the device-side circuit 400 through the signal output terminals DP and DM. That is, the transistors M3 and M4 are turned on, so that the first load circuit 521 can receive the current provided by the input/output power source I1. At this time, since the voltages of the signal output terminals DP and DM are larger, the transistors M7 and M8 can be turned on similarly, so that the first load circuit 521 and the second load circuit 522 can share the current provided by the input/output power source I1 at the same time. In other words, when the USB circuit 500 operates in the handshake mode, the termination circuit 520 of the present embodiment can effectively prevent the transistors M3 and M4 of the first load circuit 521 from carrying too much current, so that the transistors M3 and M4 enter the saturation region from the linear region, and the voltages of the pulse signals (Chirp K signal and Chirp J signal) output by the signal output terminals DP and DM drift.

When the USB circuit 500 operates in the normal mode, the switches S2 and S3 of the device-side circuit 400 are turned on, so that the reference voltages Ra and Rb of the device-side circuit 400 and the termination circuit 520 share the current at the same time. The USB circuit 500 will alternately output data signals to the device-side circuit 400 through the signal output terminals DP and DM. That is, the transistors M3 and M4 and the switches S2 and S3 are turned on, and the first load circuit 521 may receive the current provided by the core power source I2. At this time, the transistors M7 and M8 are not turned on because the voltages of the signal output terminals DP and DM are small. Therefore, when the USB circuit 500 operates in the normal mode, the current provided by the core power supply I2 does not flow through the second load circuit 522.

Accordingly, when the USB circuit 500 of the present embodiment operates in the handshake mode, the USB circuit 500 may generate pulse signals (Chirp K signal and Chirp J signal) to the device-side circuit 400 according to the power signal supplied by the input/output power source I1 with a higher voltage. Also, when the USB circuit 500 of the present embodiment operates in the normal mode, the USB circuit 500 may generate the data signal to the device-side circuit 400 by the power signal supplied by the core power I2 with a lower voltage. Therefore, the USB circuit 500 of the present embodiment can effectively avoid the voltage of the pulse signals output by the signal output terminals DP and DM from drifting, and can also effectively reduce power consumption.

Fig. 6 is a circuit diagram of a universal serial bus circuit according to yet another embodiment of the present invention. Referring to fig. 6, the USB circuit 700 includes a power supply circuit 710, a termination circuit 720, a pull-down circuit 730, and a protection circuit 740. The termination circuit 720 includes a first load circuit 721 and a second load circuit 722. The USB circuit 700 is coupled to the device-side circuit 600 via the signal output terminals DP and DM. In the present embodiment, the device-side circuit 600 refers to an equivalent circuit of a USB connection port of a computer device, for example, but the invention is not limited thereto. In the present embodiment, the device-side circuit 600 includes, for example, a pull-up resistor Rp and reference resistors Ra and Rb. Pull-up resistor Rp is coupled to switch S1. One end of the reference resistor Ra is coupled to the switch S2, and the other end of the reference resistor Ra is coupled to the ground. One end of the reference resistor Rb is coupled to the switch S3, and the other end of the reference resistor Rb is coupled to the ground terminal.

The power supply circuit 710 includes a current source circuit and transistors M1 ', M2'. The current source circuit includes a core power supply I2, and the core power supply I2 may provide a power supply signal of 1.05V, for example. The first terminal of the transistor M1' is coupled to the core power source I2. The second terminal of the transistor M1' is coupled to the signal output terminal DP. The first terminal of the transistor M2' is coupled to the core power source I2. The second terminal of the transistor M2' is coupled to the signal output terminal DM. In the present embodiment, the second terminal of the transistor M1 'and the second terminal of the transistor M2' may alternately output the power signal provided by the core power I2 via the signal output terminals DP and DM to form a differential signal. It is noted that, compared to the power circuit 510 of the embodiment of fig. 5, the power circuit 710 of the embodiment includes only one power source.

The first load circuit 721 includes resistors R1, R2 and transistors M3, M4. A first terminal of the resistor R1 is coupled to the signal output terminal DP. In this embodiment, the first terminal of the transistor M3 is coupled to the second terminal of the resistor R1, and the second terminal of the transistor M3 is coupled to the ground terminal. A first terminal of the resistor R2 is coupled to the second signal output terminal DM. The first terminal of the transistor M4 is coupled to the second terminal of the resistor R2, and the second terminal of the transistor M4 is coupled to the ground terminal. The control terminals of the transistors M3 and M4 are controlled by a control signal (not shown). When in the handshake mode or the normal mode, the transistors M3 and M4 are both turned on.

The second load circuit 722 includes transistors M5 ', M6'. In this embodiment, the first terminal of the transistor M5 'is coupled to the first terminal of the transistor M3, and the second terminal of the transistor M5' is coupled to the ground terminal. The first terminal of the transistor M6 'is coupled to the transistor M4, and the second terminal of the transistor M6' is coupled to the ground terminal. In addition, the pull-down circuit 730 includes resistors R5, R6, and the resistors R5, R6 may be 15 kohms. The control terminals of the transistors M5 ', M6' are controlled by another control signal (not shown). When in handshake mode, transistors M5 ', M6' will be turned on. When in the normal mode, the transistors M5 ', M6' will be turned off.

In the present embodiment, when the USB circuit 700 operates in the handshake mode, the power circuit 710 outputs the power signal to the first terminal of the transistor M1 'and the first terminal of the transistor M2' via the core power I2. When the USB circuit 700 operates in the normal mode, the power circuit 710 also outputs the power signal to the first terminal of the transistor M1 'and the first terminal of the transistor M2' via the core power I2. However, the transistors M1 ', M2' are low voltage devices (coredevice) configured corresponding to the low voltage core power I2. In advanced manufacturing processes, in order to prevent the transistors M1 'and M2' from being damaged by the voltage of the signal output terminals DP and DM in the full-speed mode (the voltage is 0V to 3.3V), the USB circuit 700 of the present embodiment further includes a protection circuit 740.

The protection circuit 740 is coupled between the power circuit 710 and the termination circuit 720. The protection circuit 740 includes transistors M9, M10. The first terminal of the transistor M9 is coupled to the power circuit 710, and the second terminal of the transistor M9 is coupled to the termination circuit 720. The first terminal of the transistor M10 is coupled to the power circuit 710, and the second terminal of the transistor M10 is coupled to the termination circuit 720. Accordingly, when the signal output terminals DP and DM are in the full-speed mode, the voltage is between 0V and 3.3V, and the transistors M9 and M10 are turned off to protect the transistors M1 'and M2' from being damaged.

In the present embodiment, when the USB circuit 700 is coupled to the device-side circuit 600 via the signal output terminals DP and DM, the USB circuit 700 serves as a host and outputs a USB reset signal to the device-side circuit 600. The device-side circuit 600 supports USB2.0 high-speed transmission, so the device-side circuit 600 then outputs a negative pulse signal (Chirp K signal) to the USB circuit 700, so that the USB circuit 700 confirms that the device-side circuit 600 supports USB2.0 high-speed transmission. Next, the USB circuit 700 alternately returns the negative pulse signal (Chirp K signal) and the positive pulse signal (Chirp J signal) to the device-side circuit 600 according to the power signal provided by the core power I2, so that the device-side circuit 600 can effectively confirm that the USB circuit 700 supports USB2.0 high-speed transmission. Finally, the USB circuit 700 may enter the normal mode and output the data signal to the device-side circuit 600 according to the power signal provided by the core power I2.

Fig. 7 is a signal waveform diagram of a pulse signal according to the embodiment of fig. 6. Referring to fig. 6 and 7, when the USB circuit 700 operates in the handshake mode, the USB circuit 700 may output the alternating positive pulse signal 701 and the negative pulse signal 702 shown in fig. 7 to the device-side circuit 600 via the signal output terminals DP and DM. Specifically, when the USB circuit 700 operates in the handshake mode, the switches S2 and S3 of the device side circuit 600 are not turned on, so that the terminal circuit 720 receives a large current. Therefore, the USB circuit 700 outputs the positive pulse signal 701 and the negative pulse signal 702 to the device-side circuit 600 through the signal output terminals DP and DM. In this embodiment, the peak voltage of the positive pulse signal 701 may be 800mV, and the peak voltage of the negative pulse signal 702 may be-700 mV.

That is, the transistors M3, M4, M5 ', M6' are turned on, so the first load circuit 721 and the second load circuit 722 can receive the current provided by the core power source I2, so that the first load circuit 721 and the second load circuit 722 can simultaneously share the current provided by the core power source I2. In other words, when the USB circuit 700 operates in the handshake mode, the termination circuit 720 of this embodiment can effectively prevent the transistors M3 and M4 of the first load circuit 721 from carrying too much current, so that the transistors M3 and M4 enter the saturation region from the linear region, and the voltages of the pulse signals (Chirp K signal and Chirp J signal) output by the signal output terminals DP and DM drift.

Referring again to FIG. 6, when the USB circuit 700 operates in the normal mode, the switches S2 and S3 of the device-side circuit 600 are turned on, so that the reference resistors Ra and Rb of the device-side circuit 600 and the termination circuit 720 share the current at the same time. The USB circuit 600 will alternately output data signals to the device side circuit 600 through the signal output terminals DP, DM. That is, the transistors M3 and M4 and the switches S2 and S3 are turned on, and the first load circuit 721 may receive the current supplied from the core power source I2. At this time, the control terminals of the transistors M5 'and M6' are controlled by another control signal (not shown). When in handshake mode, transistors M5 ', M6' will be turned on. When in the normal mode, the transistors M5 ', M6' will be turned off. Therefore, when the USB circuit 700 operates in the normal mode, the current provided by the core power supply I2 does not flow through the second load circuit 722.

Accordingly, when the USB circuit 700 of the present embodiment operates in the normal mode or the handshake mode, the USB circuit 700 may generate the pulse signals (Chirp J signal and Chirp K signal) and the data signal to the device-side circuit 600 according to the power signal supplied by the core power I2 with a lower voltage. Therefore, the USB circuit 700 of the present embodiment can effectively avoid the voltage of the pulse signals output by the signal output terminals DP and DM from drifting, and can also effectively reduce power consumption. More importantly, compared to the USB circuit 500 of fig. 5, the termination circuit 720 of the USB circuit 700 of the present embodiment can effectively generate the pulse signals (Chirp K signal and Chirp J signal) and the data signal with fewer transistors. Therefore, the USB circuit 700 of the present embodiment has the features of low cost and small transistor processing area.

In addition, each Transistor described in the above embodiments may be a Metal Oxide Semiconductor (MOS) Transistor, a Bipolar Junction Transistor (BJT), or the like, and the invention is not limited thereto. In addition, the types of the transistors described in the above embodiments may be N-type transistors or P-type transistors, and the invention is not limited thereto.

In summary, the usb circuit of the present invention can stably output the pulse signals (Chirp K signal and Chirp J signal) to the device side circuit during the handshake mode, so that the device side circuit can effectively confirm the data transmission capability of the usb circuit. In addition, the universal serial bus circuit can further effectively reduce the power consumption of the universal serial bus circuit and reduce the transistor processing area of the terminal circuit through the design of the power supply circuit and the load circuit.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A universal serial bus circuit comprising:

a power circuit for providing a differential signal; and

a termination circuit coupled to the power circuit for receiving the differential signal via a first signal output terminal and a second signal output terminal, and the termination circuit includes a first load circuit coupled to the power circuit via the first signal output terminal and the second signal output terminal, and a second load circuit coupled to the power circuit via the first signal output terminal and the second signal output terminal,

wherein the termination circuit receives the differential signal via the first load circuit and the second load circuit and outputs a pulse signal via the first signal output terminal and the second signal output terminal when the USB circuit operates in a handshake mode,

when the USB circuit operates in a normal mode, the termination circuit receives the differential signal through the first load circuit and outputs a data signal through the first signal output terminal and the second signal output terminal.

2. The universal serial bus circuit of claim 1, wherein the power supply circuit comprises:

a current source circuit for outputting a power signal;

a first transistor, wherein a first terminal of the first transistor is coupled to the current source circuit, and a second terminal of the first transistor is coupled to the first signal output terminal; and

a second transistor, wherein a first terminal of the second transistor is coupled to the current source circuit, a second terminal of the second transistor is coupled to the second signal output terminal,

wherein the second terminal of the first transistor and the second terminal of the second transistor alternately output the power supply signal via the first signal output terminal and the second signal output terminal to form the differential signal.

3. The universal serial bus circuit of claim 2, wherein the current source circuit comprises an input-output power supply, and the input-output power supply is coupled to the first terminal of the first transistor and the first terminal of the second transistor.

4. The universal serial bus circuit of claim 2, wherein the current source circuit comprises a core power supply and an input-output power supply, and the core power supply and the input-output power supply are coupled to the first terminal of the first transistor and the first terminal of the second transistor,

wherein the input-output power supply outputs a first power supply signal to the first terminal of the first transistor and the first terminal of the second transistor when the universal serial bus circuit operates in the handshake mode,

wherein the core power supply outputs a second power supply signal to the first terminal of the first transistor and the first terminal of the second transistor when the universal serial bus circuit operates in the normal mode.

5. The universal serial bus circuit of claim 4, wherein the first power supply signal is greater in voltage than the second power supply signal.

6. The universal serial bus circuit of claim 2, wherein the current source circuit includes a core power supply, and the core power supply is coupled to the first terminal of the first transistor and the first terminal of the second transistor.

7. The universal serial bus circuit of claim 1, wherein the first load circuit comprises:

a first resistor, wherein a first terminal of the first resistor is coupled to the first signal output terminal;

a third transistor, wherein a first terminal of the third transistor is coupled to a second terminal of the first resistor, and a second terminal of the third transistor is coupled to a ground terminal;

a second resistor, wherein a first terminal of the second resistor is coupled to the second signal output terminal; and

a fourth transistor, wherein a first terminal of the fourth transistor is coupled to a second terminal of the second resistor, and a second terminal of the fourth transistor is coupled to the ground terminal.

8. The universal serial bus circuit of claim 7, wherein the second load circuit comprises:

a third resistor, wherein a first terminal of the third resistor is coupled to the first signal output terminal;

a first diode unit coupled to a second end of the third resistor;

a fifth transistor, wherein a first terminal of the fifth transistor is coupled to the first diode unit, and a second terminal of the fifth transistor is coupled to the ground terminal;

a fourth resistor, wherein a first terminal of the fourth resistor is coupled to the second signal output terminal;

a second diode unit coupled to a second end of the fourth resistor; and

a sixth transistor, wherein a first terminal of the sixth transistor is coupled to the second diode unit, a second terminal of the sixth transistor is coupled to the ground terminal,

wherein the first diode unit and the second diode unit are non-conductive when the universal serial bus circuit operates in the normal mode, wherein the first diode unit and the second diode unit are conductive according to the differential signal provided by the power supply circuit when the universal serial bus circuit operates in the handshake mode.

9. The usb circuit according to claim 8, wherein the first diode unit comprises a seventh transistor, wherein a first terminal of the seventh transistor is coupled to the third resistor, a control terminal of the seventh transistor is coupled to the first terminal of the seventh transistor, and a second terminal of the seventh transistor is coupled to the first terminal of the fifth transistor.

10. The usb circuit according to claim 8, wherein the second diode unit comprises an eighth transistor, wherein a first terminal of the eighth transistor is coupled to the fourth resistor, a control terminal of the eighth transistor is coupled to the first terminal of the eighth transistor, and a second terminal of the eighth transistor is coupled to the first terminal of the sixth transistor.

11. The universal serial bus circuit of claim 7, wherein the second load circuit comprises:

a ninth transistor, wherein a first terminal of the ninth transistor is coupled to the first terminal of the third transistor, and a second terminal of the ninth transistor is coupled to the ground terminal; and

a tenth transistor, wherein a first terminal of the tenth transistor is coupled to the first terminal of the fourth transistor, a second terminal of the tenth transistor is coupled to the ground terminal,

wherein the ninth transistor and the tenth transistor are non-conductive when the universal serial bus circuit operates in the normal mode, wherein the ninth transistor and the tenth transistor are conductive to receive the differential signal provided by the power supply circuit when the universal serial bus circuit operates in the handshake mode.

12. The universal serial bus circuit of claim 1, further comprising:

a protection circuit coupled between the power circuit and the termination circuit, wherein the protection circuit comprises:

an eleventh transistor, wherein a first terminal of the eleventh transistor is coupled to the power circuit, and a second terminal of the eleventh transistor is coupled to the termination circuit; and

a twelfth transistor, wherein a first terminal of the twelfth transistor is coupled to the power circuit, and a second terminal of the twelfth transistor is coupled to the termination circuit.

13. The universal serial bus circuit of claim 1, further comprising:

a pull-down circuit coupled to the first signal output terminal and the second signal output terminal, wherein the pull-down circuit comprises:

a fifth resistor, wherein a first terminal of the fifth resistor is coupled to the first signal output terminal, and a second terminal of the fifth resistor is coupled to a ground terminal; and

a sixth resistor, wherein a first terminal of the sixth resistor is coupled to the second signal output terminal, and a second terminal of the sixth resistor is coupled to the ground terminal.

14. The universal serial bus circuit according to claim 1, wherein the pulse signal includes a plurality of negative pulse signals and a plurality of positive pulse signals, and the negative pulse signals and the positive pulse signals are alternately arranged.