CN109116198A - A kind of breakdown test structure, display panel and breakdown test method - Google Patents
A kind of breakdown test structure, display panel and breakdown test method Download PDFInfo
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- CN109116198A CN109116198A CN201810995027.7A CN201810995027A CN109116198A CN 109116198 A CN109116198 A CN 109116198A CN 201810995027 A CN201810995027 A CN 201810995027A CN 109116198 A CN109116198 A CN 109116198A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
- G01R31/1227—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials
- G01R31/1263—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation
- G01R31/129—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation of components or parts made of semiconducting materials; of LV components or parts
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Abstract
The present invention provides a kind of breakdown test structure, display panel and breakdown test methods.The structure includes: substrate；Active layer, the active layer setting is on the substrate；Gate insulation layer, on the active layer, gate insulation layer region corresponding with the active layer edge is climbing area for the gate insulation layer setting, and the region inside the climbing area is plane area；Grid layer, the grid layer is arranged on the gate insulation layer, and including the first grid portion and second gate portion to connect, the first grid portion covers the plane area, the second gate portion covers the climbing area, and the first grid portion and/or second gate portion are pierced pattern to expose the gate insulation layer.Through the embodiment of the present invention, when testing the breakdown voltage of gate insulation layer, plane area can be determined according to puncture place and which breakdown and which elder generation of climbing area is breakdown, and can accurately learn the film layer situation of gate insulation layer according to punch-through.
Description
Technical field
The present invention relates to field of display technology, test more particularly to a kind of breakdown test structure, display panel and breakdown
Method.
Background technique
In recent years, with the hair of OLED (Organic Light-Emitting Diode, Organic Light Emitting Diode) product
Exhibition, the processing procedure of OLED product become increasingly complex, and the quality of preceding layer process will directly affect subsequent processing procedure, or even influence entire
Process flow.Under this development trend, measures each layer of technique and just become more and more important.
Fig. 1 a and Fig. 1 b show the structure of test GI (Gate Insulation, gate insulation layer) breakdown voltage at present, figure
1a is the plan view of TFT (Thin Film Transistor, thin film transistor), and Fig. 1 b is the section at Fig. 1 a dotted line
Figure, applies voltage in source/drain 11 and grid 13, obtains the breakdown voltage of gate insulation layer 12.But it is hit in gate insulation layer 12
When wearing, it not can determine that plane area 121 is breakdown or climbing area 122 is breakdown, therefore the test of layer gate insulating film layer status
As a result inaccurate.
Summary of the invention
The present invention provides a kind of breakdown test structure, display panel and breakdown test method, to solve existing test structure
To the problem of the test result inaccuracy of film layer situation.
To solve the above-mentioned problems, the invention discloses a kind of breakdown to test structure, and the structure includes:
Substrate
Active layer, the active layer setting is on the substrate；
Gate insulation layer, the gate insulation layer are arranged on the active layer, the gate insulation layer and the active layer edge
Corresponding region is climbing area, and the region inside the climbing area is plane area；
Grid layer, the grid layer is arranged on the gate insulation layer, including the first grid portion and second gate portion to connect, institute
It states first grid portion and covers the plane area, the second gate portion covers the climbing area, the first grid portion and/or second gate portion
It is pierced pattern to expose the gate insulation layer.
Optionally, the pierced pattern is comb pattern.
Optionally, the first signal transmssion line is arranged with the active layer same layer, and is connected with the active layer；
Second signal transmission line is arranged with the grid layer same layer, and is connected with the second gate portion；
First signal transmssion line and the second signal transmission line all have end, and first signal transmits
The end of line and the end of the second signal transmission line are all exposed upper surface.
Optionally, the active layer and first signal transmssion line are the polysilicon layer doped with p type impurity；
P type impurity concentration in first signal transmssion line, higher than in the active layer covered by the grid layer
P type impurity concentration.
Optionally, the gate insulation layer is silicon oxide layer；
The grid layer is metal layer.
The embodiment of the present invention provides a kind of display panel again, and the display panel includes such as above-mentioned breakdown test knot
Structure.
The embodiment of the invention also provides a kind of breakdown test methods, test structure applied to above-mentioned breakdown, described to hit
Wearing test structure includes substrate, active layer, gate insulation layer and grid layer, and the gate insulation layer includes climbing area and plane area, institute
Stating grid layer includes first grid portion and second gate portion, and the first grid portion and/or the second gate portion are pierced pattern, the side
Method includes:
Apply voltage on the active layer and the grid layer, wherein the voltage is gradually increased；
When the gate insulation layer is breakdown, breakdown voltage is determined；
It is located at the first grid portion according to the puncture place, determines that the plane area is breakdown；According to the breakdown position
Setting in the second gate portion, determine that the climbing area is breakdown.
Optionally, the pierced pattern is comb pattern.
Optionally, breakdown test structure further includes the first signal transmssion line and second signal transmission line, and described first
Signal transmssion line is connected with the active layer, and the second signal transmission line is connected with the second gate portion, first signal
Transmission line and the second signal transmission line all have end；The method also includes:
Apply voltage in the end of first signal transmssion line and the end of the second signal transmission line.
Compared with prior art, the present invention includes the following advantages:
Breakdown test structure includes substrate, active layer, gate insulation layer and grid layer；Gate insulation layer is corresponding with active layer edge
Region be climbing area, positioned at climbing area inside region be plane area；Grid layer includes first grid portion and second gate portion, and first
Shan Bu overlay planes area, covering climbing area of second gate portion, first grid portion and/or second gate portion are pierced pattern to expose gate insulation
Layer.Since first grid portion and/or second gate portion are pierced pattern, it can determine that grid are exhausted according to first grid portion and second gate portion
The climbing area of edge layer and plane area, and then when testing the breakdown voltage of gate insulation layer, plane can be determined according to puncture place
Area and which breakdown and which elder generation of climbing area are breakdown, and can accurately learn gate insulation according to punch-through
The film layer situation of layer.
Detailed description of the invention
Fig. 1 a shows the plan view of the breakdown test structure of background technique；
Fig. 1 b shows the sectional view of the breakdown test structure of background technique；
Fig. 2 a shows a kind of one of the plan view of breakdown test structure of the embodiment of the present invention one；
Fig. 2 b shows a kind of sectional view of breakdown test structure of the embodiment of the present invention one；
Fig. 3 shows the two of the plan view of a kind of breakdown test structure of the embodiment of the present invention one；
Fig. 4 a shows the active layer of the embodiment of the present invention one and the floor plan of grid layer；
Fig. 4 b shows the active layer of the embodiment of the present invention one and the lamination plan view of grid layer；
Fig. 5 shows a kind of step flow chart of breakdown test method of the embodiment of the present invention three.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
Embodiment one
Referring to shown in a kind of plan view and Fig. 2 b of breakdown test structure provided in an embodiment of the present invention shown in Fig. 2 a
Breakdown test structure sectional view, the structure includes:
Substrate 20；
Active layer 21, the active layer 21 are arranged in the substrate 20；
Gate insulation layer 22, the gate insulation layer 22 are arranged on the active layer 21, and the gate insulation layer 22 has with described
The corresponding region in 21 edge of active layer is climbing area 222, and the region inside the climbing area is plane area 221；
Grid layer 23, the grid layer 23 are arranged on the gate insulation layer 22, test structure referring to breakdown shown in Fig. 3
Plan view, including the first grid portion 231 and second gate portion 232 to connect, the first grid portion 231 covers the plane area 221,
The second gate portion 232 covers the climbing area 222, the first grid portion 231 and/or second gate portion 232 be pierced pattern with
Expose the gate insulation layer 22.
In the present embodiment, Fig. 2 a is the plan view of breakdown test structure, and Fig. 2 b is the sectional view at Fig. 2 a dotted line, referring to figure
2b, active layer 21 are arranged on the substrate 20, and gate insulation layer 22 is arranged on active layer 21, and grid layer 23 is arranged in gate insulation layer 22
On.Gate insulation layer 22 is covered on the region at 21 edge of active layer as climbing area 222, is covered on active layer 21, climbs in area 222
The region in portion is plane area 221.Referring to Fig. 3, grid layer 23 includes the first grid portion 231 and second gate portion 232 to connect, the first grid
Portion 231, second gate portion 232 can be pierced pattern；Either first grid portion 231 is non-pierced pattern, and second gate portion 232 is
Pierced pattern；It can also be that first grid portion 231 is pierced pattern, second gate portion 232 is non-pierced pattern, wherein pierced pattern
Exposed portion gate insulation layer 22.The plane area 221 of gate insulation layer 22 can be determined according to first grid portion 231 and second gate portion 232
With climbing area 222, and then test gate insulation layer 22 breakdown voltage when, can be according to first grid portion 231 and second gate portion 232
Determine that puncture place is plane area or climbing area and plane area and which elder generation of climbing area is breakdown.
Optionally, the pierced pattern is comb pattern.
In the present embodiment, non-pierced pattern can be rectangle, as shown in figure 3, either square, round, the present invention
Embodiment does not limit this in detail, can be configured according to the actual situation.Pierced pattern can be comb pattern, pectination figure
Shape is made of the strip structure of multiple parallel arrangeds.Breakdown ratio in Fig. 3, when the uniform film thickness of gate insulation layer 22, at comb teeth
It is more uniform；It is breakdown at the comb teeth of part when the membrane thickness unevenness of gate insulation layer 22, it is not breakdown at the comb teeth of part.Namely
It says, the film layer situation of gate insulation layer 22 can be determined according to the punch-through at comb teeth.
Optionally, the active layer referring to shown in the floor plan and 4b of active layer shown in Fig. 4 a and grid layer and
The lamination plan view of grid layer；
First signal transmssion line 24 is arranged with 21 same layer of active layer, and is connected with the active layer 21；
Second signal transmission line 25 is arranged with 23 same layer of grid layer, and is connected with the second gate portion 232；
First signal transmssion line 24 and the second signal transmission line 25 all have end, and first signal
The end 241 of transmission line 24 and the end 251 of the second signal transmission line 25 are all exposed upper surface.
In the present embodiment, the first signal transmssion line 24 is arranged with 21 same layer of active layer, and is connected with active layer 21；Second letter
Number transmission line 25 and 23 same layer of grid layer are arranged, and are connected with second gate portion 232.241 He of end of first signal transmssion line 24
The end 251 of second signal transmission line 25 is all exposed upper surface, can be by voltage when testing the breakdown voltage of gate insulation layer 22
It is applied on the end 241 of the first signal transmssion line 24 and the end 251 of second signal transmission line 25.
Optionally, the active layer 21 and first signal transmssion line 24 are the polysilicon layer doped with p type impurity；
P type impurity concentration in first signal transmssion line 24, higher than what is covered by the orthographic projection of the grid layer 23
P type impurity concentration in the active layer 21.
It, can deposit polycrystalline silicon, and doped p-type impurity on the substrate 20 in the present embodiment；By patterning processes to polycrystalline
Silicon is patterned, and active layer 21 and the first signal transmssion line 24 are formed.After forming grid layer 23, grid layer 23 covers portion
Point active layer 21, but do not cover the first signal transmssion line 24, doped p-type impurity again at this time, then in the first signal transmssion line 24
P type impurity concentration, than grid layer 23 cover active layer 21 in p type impurity concentration it is high.The p type impurity of high concentration can drop
The resistance of low first signal transmssion line 24 avoids the resistance of the first signal transmssion line 24 from having an impact breakdown voltage.P type impurity
It can be boron ion, the embodiment of the present invention does not limit this in detail, can be chosen according to the actual situation.
Optionally, the gate insulation layer 22 is silicon oxide layer；
The grid layer 23 is metal layer.
In the present embodiment, gate insulation layer 22 can be silicon oxide layer, such as silicon dioxide layer；Grid layer 23 can be metal
Layer, such as Mo layer；Substrate 20 may include glass substrate and buffer layer.The embodiment of the present invention does not limit this in detail,
It can be chosen according to the actual situation.
In conclusion in the embodiment of the present invention, breakdown test structure includes substrate, active layer, gate insulation layer and grid layer,
Gate insulation layer region corresponding with active layer edge is climbing area, and the region inside climbing area is plane area, grid layer packet
Include first grid portion and second gate portion, overlay planes area of first grid portion, covering climbing area of second gate portion, first grid portion and/or second
Grid portion is pierced pattern to expose gate insulation layer.It, can basis since first grid portion and/or second gate portion are pierced pattern
First grid portion and second gate portion determine climbing area and the plane area of gate insulation layer, and then in the breakdown voltage of test gate insulation layer
When, plane area and climbing area can be determined according to puncture place, and which is breakdown and which is first breakdown, and can be with
The film layer situation of gate insulation layer is accurately learnt according to punch-through.
Embodiment two
The embodiment of the invention provides a kind of display panels.The display panel includes that the breakdown as described in embodiment one is surveyed
Try structure.Structure is tested in the breakdown
Substrate 20；
Active layer 21, the active layer 21 are arranged in the substrate 20；
Gate insulation layer 22, the gate insulation layer 22 are arranged on the active layer 21, and the gate insulation layer 22 has with described
The corresponding region in 21 edge of active layer is climbing area 222, and the region inside the climbing area 222 is plane area 221；
Grid layer 23, the grid layer 23 are arranged on the gate insulation layer 22, the first grid portion 231 including connecting and the
Two grid portions 232, the first grid portion 231 cover the plane area 221, and the second gate portion 232 covers the climbing area 222,
The first grid portion 231 and/or second gate portion 232 are pierced pattern to expose the gate insulation layer 22.
In the present embodiment, using the breakdown voltage of breakdown test structured testing gate insulation layer 22, due to first grid portion 231
And/or second gate portion 232 is pierced pattern, therefore can determine gate insulation layer 22 according to first grid portion 231 and second gate portion 232
Plane area 221 and climbing area 222.It, can be according to 231 He of first grid portion and then when testing the breakdown voltage of gate insulation layer 22
Second gate portion 232 determine puncture place be plane area or climbing area and plane area and climbing area which first it is breakdown.And
And breakdown test structure is separately provided in display panel, both may be implemented the online measuring of gate insulation layer, timeliness compared with
It is good, and other devices are not influenced.
In conclusion display panel includes breakdown test structure in the embodiment of the present invention, it can be accurate according to punch-through
It learns the film layer situation of gate insulation layer, and online measuring may be implemented, timeliness is good.
Embodiment three
Referring to Fig. 5, a kind of step flow chart for puncturing test method provided in an embodiment of the present invention is shown.Applied to reality
The test structure of breakdown described in example one is applied, the breakdown test structure includes substrate 20, active layer 21, gate insulation layer 22 and grid
Layer 23, the gate insulation layer 22 include climbing area 222 and plane area 221, and the grid layer 23 includes first grid portion 231 and second
Grid portion 232, the first grid portion 231 and/or the second gate portion 232 are pierced pattern, which comprises
Step 301, apply voltage on the active layer 21 and the grid layer 23, wherein the voltage is gradually increased.
In the present embodiment, the two sides of gate insulation layer 22 are arranged in active layer 21 and grid layer 23, as test gate insulation layer
Two electrodes of 22 breakdown voltages, apply the voltage being gradually increased on active layer 21 and grid layer 23, so as to test grid
The pressure resistance of insulating layer 22.
Optionally, breakdown test structure further includes the first signal transmssion line 24 and second signal transmission line 25, described
First signal transmssion line 24 is connected with the active layer 21, and the second signal transmission line 25 is connected with the second gate portion 232,
First signal transmssion line 24 and the second signal transmission line 25 all have end, in first signal transmssion line 24
End 241 and the end 251 of the second signal transmission line apply voltage.
Specifically, the first signal transmssion line 24 connects active layer 21, and second signal transmission line 25 connects second gate portion 232,
Apply voltage by the end 251 in the end 251 of the first signal transmssion line 24 and second signal transmission line 25, voltage is applied
On active layer 21 and grid layer 23.
Step 302, when the gate insulation layer 22 is breakdown, breakdown voltage is determined.
In the present embodiment, test structure can be punctured with micro- sem observation, as voltage gradually increases, it will observe and hit
Phenomenon is worn, voltage of the gate insulation layer 22 when breakdown is determined as breakdown voltage.
Step 303, the first grid portion 231 is located at according to the puncture place, determines that the plane area 221 is breakdown；
It is located at the second gate portion 232 according to the puncture place, determines that the climbing area 222 is breakdown.
It, can be according to first since first grid portion 231 and/or second gate portion 232 are pierced pattern in the present embodiment
Grid portion 231 and second gate portion 232 determine plane area 221 and the climbing area 222 of gate insulation layer 22.When puncture place is in first grid portion
When 231, it can be determined that plane area 221 is breakdown；When puncture place is at second gate portion 232, then it can be determined that climbing area
It is breakdown.The sequence of punch-through can also occur according to first grid portion 231 and second gate portion 232, determine plane area and climbing
Which elder generation of area is breakdown.
Optionally, the pierced pattern is comb pattern.
In the present embodiment, the film layer situation of gate insulation layer 22 can be determined according to the distribution of puncture place in pierced pattern.
Specifically, when the uniform film thickness of gate insulation layer 22, the breakdown in pierced pattern at comb teeth is relatively uniform；When gate insulation layer 22
It is breakdown at the comb teeth of part in pierced pattern when membrane thickness unevenness, it is not breakdown at the comb teeth of part, that is to say, that can basis
Punch-through at comb teeth determines the thickness uniformity of gate insulation layer 22.
In conclusion applying the voltage being gradually increased on active layer and grid layer in the embodiment of the present invention；In gate insulation
When layer is breakdown, breakdown voltage is determined；It is located at first grid portion according to puncture place, determines that plane area is breakdown；According to breakdown position
Setting in second gate portion, determine that climbing area is breakdown.Through the embodiment of the present invention, it can accurately know the climbing area of gate insulation layer
Which is breakdown with plane area, the breakdown voltage of which first breakdown and plane area and climbing area, the film of gate insulation layer
Layer status.
All the embodiments in this specification are described in a progressive manner, the highlights of each of the examples are with
The difference of other embodiments, the same or similar parts between the embodiments can be referred to each other.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that the process, method, commodity or the equipment that include a series of elements not only include that
A little elements, but also including other elements that are not explicitly listed, or further include for this process, method, commodity or
The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged
Except there is also other identical elements in process, method, commodity or the equipment for including the element.
Above to a kind of breakdown test structure, display panel and breakdown test method provided by the present invention, carry out in detail
Thin to introduce, used herein a specific example illustrates the principle and implementation of the invention, and above embodiments are said
It is bright to be merely used to help understand method and its core concept of the invention；At the same time, for those skilled in the art, foundation
Thought of the invention, there will be changes in the specific implementation manner and application range, in conclusion the content of the present specification is not
It is interpreted as limitation of the present invention.
Claims (9)
1. structure is tested in a kind of breakdown, which is characterized in that the structure includes:
Substrate；
Active layer, the active layer setting is on the substrate；
Gate insulation layer, on the active layer, the gate insulation layer is corresponding with the active layer edge for the gate insulation layer setting
Region be climbing area, positioned at it is described climbing area inside region be plane area；
Grid layer, the grid layer is arranged on the gate insulation layer, including the first grid portion and second gate portion to connect, described the
One grid portion covers the plane area, and the second gate portion covers the climbing area, the first grid portion and/or the second gate portion
It is pierced pattern to expose the gate insulation layer.
2. structure according to claim 1, which is characterized in that the pierced pattern is comb pattern.
3. structure according to claim 1, which is characterized in that
First signal transmssion line is arranged with the active layer same layer, and is connected with the active layer；
Second signal transmission line is arranged with the grid layer same layer, and is connected with the second gate portion；
First signal transmssion line and the second signal transmission line all have end, and first signal transmssion line
End and the end of the second signal transmission line are all exposed upper surface.
4. structure according to claim 3, which is characterized in that the active layer and first signal transmssion line are to mix
The miscellaneous polysilicon layer for having p type impurity；
P type impurity concentration in first signal transmssion line, higher than the p-type in the active layer covered by the grid layer
Impurity concentration.
5. structure according to claim 1, which is characterized in that the gate insulation layer is silicon oxide layer；
The grid layer is metal layer.
6. a kind of display panel, which is characterized in that the display panel includes that breakdown as described in any one in claim 1-5 is surveyed
Try structure.
7. a kind of breakdown test method, which is characterized in that it is applied to the described in any item breakdown of claim 1-5 and tests structure,
The breakdown test structure includes substrate, active layer, gate insulation layer and grid layer, and the gate insulation layer includes climbing area and plane
Area, the grid layer include first grid portion and second gate portion, and the first grid portion and/or the second gate portion are pierced pattern,
The described method includes:
Apply voltage on the active layer and the grid layer, wherein the voltage is gradually increased；
When the gate insulation layer is breakdown, breakdown voltage is determined；
It is located at the first grid portion according to the puncture place, determines that the plane area is breakdown；According to the puncture place position
In the second gate portion, determine that the climbing area is breakdown.
8. the method according to the description of claim 7 is characterized in that the pierced pattern is comb pattern.
9. the method according to the description of claim 7 is characterized in that breakdown test structure further includes the first signal transmssion line
With second signal transmission line, first signal transmssion line is connected with the active layer, the second signal transmission line with it is described
Second gate portion is connected, and first signal transmssion line and the second signal transmission line all have end；The method also includes:
Apply voltage in the end of first signal transmssion line and the end of the second signal transmission line.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109946589A (en) * | 2019-04-08 | 2019-06-28 | 京东方科技集团股份有限公司 | A kind of undesirable method and device of detection display panel electricity |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101995536A (en) * | 2009-08-10 | 2011-03-30 | 索尼公司 | Valuation method of dielectric breakdown lifetime of gate insulating film, valuation device of dielectric breakdown lifetime of gate insulating film and program for evaluating dielectric breakdown lifetime of gate insulating film |
| US20130314119A1 (en) * | 2012-05-23 | 2013-11-28 | International Business Machines Corporation | Testing structure and method of using the testing structure |
| CN103852701A (en) * | 2012-12-04 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | MOS transistor testing circuit and corresponding testing method |
| CN103913358A (en) * | 2014-04-10 | 2014-07-09 | 武汉新芯集成电路制造有限公司 | Preparation method and failure analysis method for transmission electron microscope (TEM) sample |
| CN104078343A (en) * | 2014-07-02 | 2014-10-01 | 武汉新芯集成电路制造有限公司 | Failure analysis method for gate oxide defect original appearance |
| CN105045425A (en) * | 2015-08-10 | 2015-11-11 | 京东方科技集团股份有限公司 | Touch display panel, driving method thereof, and touch display apparatus |
| CN205229635U (en) * | 2015-12-18 | 2016-05-11 | 京东方科技集团股份有限公司 | Pixel structure, array substrate and display device |
| CN107170743A (en) * | 2016-03-08 | 2017-09-15 | 瑞萨电子株式会社 | Semiconductor equipment and its manufacture method |
-
2018
- 2018-08-29 CN CN201810995027.7A patent/CN109116198B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101995536A (en) * | 2009-08-10 | 2011-03-30 | 索尼公司 | Valuation method of dielectric breakdown lifetime of gate insulating film, valuation device of dielectric breakdown lifetime of gate insulating film and program for evaluating dielectric breakdown lifetime of gate insulating film |
| US20130314119A1 (en) * | 2012-05-23 | 2013-11-28 | International Business Machines Corporation | Testing structure and method of using the testing structure |
| CN103852701A (en) * | 2012-12-04 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | MOS transistor testing circuit and corresponding testing method |
| CN103913358A (en) * | 2014-04-10 | 2014-07-09 | 武汉新芯集成电路制造有限公司 | Preparation method and failure analysis method for transmission electron microscope (TEM) sample |
| CN104078343A (en) * | 2014-07-02 | 2014-10-01 | 武汉新芯集成电路制造有限公司 | Failure analysis method for gate oxide defect original appearance |
| CN105045425A (en) * | 2015-08-10 | 2015-11-11 | 京东方科技集团股份有限公司 | Touch display panel, driving method thereof, and touch display apparatus |
| CN205229635U (en) * | 2015-12-18 | 2016-05-11 | 京东方科技集团股份有限公司 | Pixel structure, array substrate and display device |
| CN107170743A (en) * | 2016-03-08 | 2017-09-15 | 瑞萨电子株式会社 | Semiconductor equipment and its manufacture method |
Non-Patent Citations (2)
| Title |
|---|
| CHUNJUAN LIU等: "《Electrical performance of static induction transistor with transverse structure》", 《 SPRINGER NATURE JOURNAL》 * |
| 曹玉峰: "《基于新型硬件闭环法的晶体管击穿电压和漏电流测试》", 《计量技术》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109946589A (en) * | 2019-04-08 | 2019-06-28 | 京东方科技集团股份有限公司 | A kind of undesirable method and device of detection display panel electricity |
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