CN109103303A - A kind of preparation method and LED epitaxial slice of LED epitaxial slice - Google Patents
A kind of preparation method and LED epitaxial slice of LED epitaxial slice Download PDFInfo
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- CN109103303A CN109103303A CN201810698820.0A CN201810698820A CN109103303A CN 109103303 A CN109103303 A CN 109103303A CN 201810698820 A CN201810698820 A CN 201810698820A CN 109103303 A CN109103303 A CN 109103303A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
Abstract
The invention discloses a kind of preparation method of LED epitaxial slice and LED epitaxial slices, belong to technical field of semiconductors.The preparation method includes: to provide a substrate；Successively grown buffer layer, n type semiconductor layer, active layer, low temperature P-type layer and high temperature P-type layer, the growth temperature of the low temperature P-type layer are lower than the growth temperature of the high temperature P-type layer over the substrate；Wherein, at least one of the low temperature P-type layer and the high temperature P-type layer are superlattice structure, the superlattice structure includes the multiple sublayers stacked gradually, and each sublayer is formed in the following way: being continually fed into indium source, gallium source, ammonia and carrier gas, forms gallium indium nitride layer；Stopping is passed through indium source and gallium source, while continuing to be passed through ammonia and carrier gas, handles the gallium indium nitride layer；Start to be passed through magnesium source, while continuing to be passed through ammonia and carrier gas, forms magnesium nitride layer on the gallium indium nitride layer.The concentration in hole in superlattice structure can be improved in the present invention.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to the preparation method of a kind of LED epitaxial slice and shine
Diode epitaxial slice.
Background technique
Light emitting diode (English: Light Emitting Diode, referred to as: LED) it is a kind of semi-conductor electricity that can be luminous
Subcomponent.As a kind of New Solid lighting source efficiently, environmentally friendly, green, LED is becoming widely adopted in illumination, display
The fields such as screen, signal lamp, backlight, toy.In the development of light emitting diode industry, broad-band gap (Eg > 2.3eV) semiconductor
The development of material gallium nitride (GaN) is very rapid.
Epitaxial wafer is the primary finished product in LED preparation process.Existing LED epitaxial wafer includes substrate, buffer layer, N-type half
Conductor layer, active layer and p type semiconductor layer, buffer layer, n type semiconductor layer, active layer and p type semiconductor layer are sequentially laminated on lining
On bottom.P type semiconductor layer is used to provide the hole for carrying out recombination luminescence, and n type semiconductor layer, which is used to provide, carries out recombination luminescence
Electronics, the radiation recombination that active layer is used to carry out electrons and holes shine, and substrate is used to provide growing surface for epitaxial material；Lining
The material at bottom generally selects sapphire, and the material of n type semiconductor layer etc. generally selects gallium nitride, and sapphire and gallium nitride are heterogeneous
, there is biggish lattice mismatch in material, the lattice that buffer layer is used to alleviate between substrate and n type semiconductor layer loses between the two
Match.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems:
Having very high background election concentration in the intrinsic gallium nitride of unintentional doping, (electron concentration is up to 1016/cm3),
Therefore N-type is presented in intrinsic gallium nitride, causes the difficulty for obtaining p-type gallium nitride more much larger than the difficulty for obtaining n type gallium nitride, and
The activation rate of p type impurity is very low in p-type gallium nitride, therefore to be difficult to realize high hole dense for the p type semiconductor layer that is formed of p-type gallium nitride
Degree, the number of cavities that p type semiconductor layer can be provided is less, so that carrying out the hole of recombination luminescence in active layer with electronics
Negligible amounts, limit the recombination luminescence efficiency in active layer, and the luminous efficiency for ultimately causing LED is lower.
Summary of the invention
The embodiment of the invention provides a kind of preparation method of LED epitaxial slice and LED epitaxial slice, energy
It enough solves prior art p type semiconductor layer and is difficult to realize high hole concentration, ultimately cause the lower problem of the luminous efficiency of LED.
The technical solution is as follows:
On the one hand, the embodiment of the invention provides a kind of preparation method of LED epitaxial slice, the preparation methods
Include:
One substrate is provided；
Successively grown buffer layer, n type semiconductor layer, active layer, low temperature P-type layer and high temperature P-type layer over the substrate, institute
The growth temperature for stating low temperature P-type layer is lower than the growth temperature of the high temperature P-type layer；
Wherein, at least one of the low temperature P-type layer and the high temperature P-type layer are superlattice structure, the superlattices
Structure includes the multiple sublayers stacked gradually, and each sublayer is formed in the following way:
It is continually fed into indium source, gallium source, ammonia and carrier gas, forms gallium indium nitride layer；
Stopping is passed through indium source and gallium source, while continuing to be passed through ammonia and carrier gas, handles the gallium indium nitride layer；
Start to be passed through magnesium source, while continuing to be passed through ammonia and carrier gas, forms magnesium nitride layer on the gallium indium nitride layer.
Optionally, the carrier gas is the mixed gas of nitrogen and hydrogen, grows when the low temperature P-type layer hydrogen in the carrier gas
Ratio shared by hydrogen in carrier gas when ratio shared by gas is less than the growth high temperature P-type layer.
Optionally, the quantity of the sublayer is 5~30.
Optionally, the gallium indium nitride layer with a thickness of 10nm~50nm.
Optionally, the processing time of the gallium indium nitride layer is 5s~30s.
Optionally, the formation time of the magnesium nitride layer is 10s~5min.
Optionally, growth temperature remains unchanged in the forming process of the single sublayer.
Optionally, the growth temperature of the low temperature P-type layer is 750 DEG C~800 DEG C.
Optionally, the growth temperature of the high temperature P-type layer is 950 DEG C~1000 DEG C.
On the other hand, the embodiment of the invention provides a kind of LED epitaxial slice, the LED epitaxial slices
Including substrate, buffer layer, n type semiconductor layer, active layer, low temperature P-type layer and high temperature P-type layer, the buffer layer, the N-type half
Conductor layer, the active layer, the low temperature P-type layer and the high temperature P-type layer stack gradually over the substrate, the low temperature P
The growth temperature of type layer is lower than the growth temperature of the high temperature P-type layer；In the low temperature P-type layer and the high temperature P-type layer extremely
Few one is superlattice structure, and the superlattice structure includes the multiple sublayers stacked gradually, and each sublayer includes successively
The gallium indium nitride layer and magnesium nitride layer of stacking, the gallium indium nitride layer are passed through ammonia and carrier gas before the magnesium nitride layer stackup
It is treated.
Technical solution provided in an embodiment of the present invention has the benefit that
By being initially formed gallium indium nitride layer, the indium component in gallium indium nitride layer can reduce the incorporation efficiency of gallium, reduce nitrogen
Vacancy (group Ⅴ element vacancy) increases by III race's element vacancy, is conducive to being incorporated to for magnesium, hole is dense in raising superlattice structure
Degree.Gallium indium nitride layer is handled by nitrogen and carrier gas again, the part gallium atom on gallium indium nitride layer surface can be made to be desorbed,
Gallium vacancy is formed, is conducive to magnesium atom and is incorporated to, further increase the concentration in hole in superlattice structure.Finally in gallium indium nitride layer
Upper formation magnesium nitride layer, gallium indium nitride layer interruption of growth when due to the growth of magnesium nitride layer, forms on gallium indium nitride layer
Magnesium nitride layer is equivalent to after group Ⅲ-Ⅴ compound semiconductor stops growing mixes magnesium again, and the discontinuous growth of gallium nitride
The formation that stacking dislocation can effectively be inhibited when magnesium atom mixes gallium nitride, reduces defect concentration, reduces self-compensation mechanism, mention
High-crystal quality, the final concentration for improving hole in superlattice structure.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of flow chart of the preparation method of LED epitaxial slice provided in an embodiment of the present invention；
Fig. 2 is the flow chart of the generation type of single sublayer provided in an embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram of LED epitaxial slice provided in an embodiment of the present invention；
Fig. 4 is the structural schematic diagram of superlattice structure provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
The embodiment of the invention provides a kind of preparation method of LED epitaxial slice, Fig. 1 mentions for the embodiment of the present invention
A kind of flow chart of the preparation method of the LED epitaxial slice supplied, referring to Fig. 1, which includes:
Step 101: a substrate is provided.
Specifically, the material of substrate can use one of sapphire, silicon, silicon carbide.
Optionally, before step 101, which can also include:
Controlled at 1000 DEG C~1200 DEG C (preferably 1100 DEG C), in hydrogen atmosphere to substrate carry out 1 minute~
The annealing of 10 minutes (preferably 8 minutes)；
Nitrogen treatment is carried out to substrate.
It is cleaned using surface of the above-mentioned steps to substrate, avoids influencing whole crystal in impurity incorporation epitaxial wafer
Quality reduces the luminous efficiency of LED.
Step 102: successively grown buffer layer, n type semiconductor layer, active layer, low temperature P-type layer and high temperature p-type on substrate
Layer.
In the present embodiment, the growth temperature of low temperature P-type layer is lower than the growth temperature of high temperature P-type layer.
The growth temperature of low temperature P-type layer is lower, it is possible to prevente effectively from the indium nitrogen key in active layer is broken at high temperature and makes
It is precipitated at indium, active layer is protected not to be destroyed.The growth temperature of high temperature P-type layer is higher simultaneously, it is ensured that the crystalline substance of high temperature P-type layer
Weight is preferable, avoids the crystal quality for influencing epitaxial wafer entirety poor and then influences the luminous efficiency of LED, and also helps
Improve the concentration in hole in superlattice structure.
Correspondingly, in low temperature P-type layer indium component molar content be less than high temperature P-type layer in indium component molar content.
Optionally, the growth temperature of low temperature P-type layer can be 750 DEG C~800 DEG C, preferably 760 DEG C.
If the growth temperature of low temperature P-type layer is lower than 750 DEG C, may since the growth temperature of low temperature P-type layer is too low and
It causes the growth quality of low temperature P-type layer too poor, causes the crystal quality of epitaxial wafer entirety poor, influence the compound of electrons and holes
It shines, reduces the luminous efficiency of LED；If the growth temperature of low temperature P-type layer is higher than 800 DEG C, may be due to low temperature P-type layer
Growth temperature is too high and causes low temperature P-type layer that can not protect to active layer, causes indium nitrogen key in active layer at high temperature
It is broken and indium is caused to be precipitated, influence the recombination luminescence of electrons and holes, reduce the luminous efficiency of LED.
Optionally, the growth temperature of high temperature P-type layer can be 950 DEG C~1000 DEG C, preferably 970 DEG C.
If the growth temperature of high temperature P-type layer is lower than 950 DEG C, may since the growth temperature of high temperature P-type layer is too low and
It causes the growth quality of high temperature P-type layer too poor, causes the crystal quality of epitaxial wafer entirety poor, influence the compound of electrons and holes
It shines, reduces the luminous efficiency of LED；If the growth temperature of high temperature P-type layer is higher than 1000 DEG C, may be due to high temperature P-type layer
Growth temperature it is too high and active layer is damaged, the indium nitrogen key in active layer is broken at high temperature and indium is caused to be precipitated, shadow
The recombination luminescence for ringing electrons and holes, reduces the luminous efficiency of LED.
In the present embodiment, at least one of low temperature P-type layer and high temperature P-type layer are superlattice structure, superlattice structure
Including the multiple sublayers stacked gradually.
Specifically, can be low temperature P-type layer is superlattice structure, and high temperature P-type layer is single layer structure；It is also possible to low temperature
P-type layer is single layer structure, and high temperature P-type layer is superlattice structure；It can also be that low temperature P-type layer is superlattice structure, high temperature P-type layer
For superlattice structure.Wherein, single layer structure can be p-type gallium nitride layer.
Fig. 2 is the flow chart of the generation type of single sublayer, and referring to fig. 2, each sublayer is formed in the following way:
Step S1: being continually fed into indium source, gallium source, ammonia and carrier gas, forms gallium indium nitride layer；
Step S2: stopping is passed through indium source and gallium source, while continuing to be passed through ammonia and carrier gas, at gallium indium nitride layer
Reason；
Step S3: start to be passed through magnesium source, while continuing to be passed through ammonia and carrier gas, form magnesium nitride on gallium indium nitride layer
Layer.
For the embodiment of the present invention by being initially formed gallium indium nitride layer, the indium component in gallium indium nitride layer can reduce being incorporated to for gallium
Efficiency is reduced in nitrogen vacancy (group Ⅴ element vacancy), increases by III race's element vacancy, is conducive to being incorporated to for magnesium, improves superlattice structure
The concentration in middle hole.
Gallium indium nitride layer is handled by nitrogen and carrier gas again, the part gallium atom on gallium indium nitride layer surface can be made
Desorption forms gallium vacancy, is conducive to magnesium atom and is incorporated to, further increase the concentration in hole in superlattice structure.
Finally on gallium indium nitride layer formed magnesium nitride layer, due to magnesium nitride layer growth when gallium indium nitride layer in medium well
It is long, therefore form magnesium nitride layer on gallium indium nitride layer and be equivalent to and mixed again after group Ⅲ-Ⅴ compound semiconductor stops growing
Enter magnesium, and the discontinuous growth of gallium nitride can effectively inhibit the formation of stacking dislocation when magnesium atom mixes gallium nitride, reduce
Defect concentration reduces self-compensation mechanism, improves crystal quality, the final concentration for improving hole in superlattice structure.
In specific implementation, each sublayer in superlattice structure successively executes step S1~step S3 and is formed, that is, exists
When forming superlattice structure, step S1~step S3 is first successively executed, first sublayer is formed；Step S1~step is successively executed again
Rapid S3 forms second sublayer；Then step S1~step S3 is successively executed, third sublayer ... so circulation is formed and executes
Step S1~step S3, until forming sublayer all in superlattice structure.
Specifically, growth temperature can remain unchanged in the forming process of single sublayer.
Similarly, carrier gas can also remain unchanged in the forming process of single sublayer.
By using process conditions, on the one hand can guarantee the stability of growing environment in sublayer forming process, avoid
Negatively influencing is caused since process conditions change, is on the other hand also convenient for realizing.
Optionally, carrier gas can be the mixed gas of nitrogen and hydrogen, when growing low temperature P-type layer in carrier gas shared by hydrogen
Ratio shared by hydrogen in carrier gas when ratio can be less than growth high temperature P-type layer.
Ratio shared by hydrogen is smaller in carrier gas when growing low temperature P-type layer, i.e., growing low temperature P-type layer when the amounts of hydrogen that is passed through
It is less, avoid hydrogen from destroying active layer under etching effect.Simultaneously when growing high temperature P-type layer in carrier gas ratio shared by hydrogen compared with
Greatly, that is, the amounts of hydrogen being passed through when growing high temperature P-type layer is more, and the crystal quality of high temperature P-type layer can be improved, and avoids influencing extension
The crystal quality of piece entirety is poor and then influences the luminous efficiency of LED, and also advantageously improves hole in superlattice structure
Concentration.
Preferably, the volume ratio of nitrogen and hydrogen can be 3:1 in carrier gas when growing low temperature P-type layer, grow high temperature P-type layer
The volume ratio of nitrogen and hydrogen can be 3:2 in Shi Zaiqi.
Optionally, the quantity of sublayer can be 5~30.
If the quantity of sublayer is less than 5, the compound hair of electrons and holes may be influenced due to number of cavities deficiency
Light, or even the problem for causing the qualities such as optical attenuation bad；If the quantity of sublayer is more than 30, may be due to P-type layer thickness
It is too thick, influence light extraction efficiency.
Preferably, the quantity of sublayer can be greater than the quantity of sublayer in high temperature P-type layer in low temperature P-type layer.
Due to low temperature P-type layer be it is main the structure in hole is provided, the quantity of sublayer is more in low temperature P-type layer, can be with
Guarantee the number of cavities of injection active layer；And in high temperature P-type layer sublayer negligible amounts, it is possible to prevente effectively from due to high temperature p-type
Layer is too thick and influences light out, reduces light extraction efficiency.
It is highly preferred that the quantity of sublayer can be 30 in low temperature P-type layer, the quantity of sublayer can be 5 in high temperature P-type layer
It is a.
Optionally, the thickness of gallium indium nitride layer can be 10nm~50nm, preferably 30nm.
If the thickness of gallium indium nitride layer is less than 10nm, it can not may be magnesium since the thickness of gallium indium nitride layer is too small
Be incorporated to enough spaces be provided, the number of cavities of superlattice structure offer is provided, limitation active layer electrons and holes it is compound
It shines, causes the luminous efficiency of LED lower；If the thickness of gallium indium nitride layer is greater than 50nm, may be due to gallium indium nitride layer
Thickness it is too big and influence the growth quality of superlattice structure, cause the crystal quality of epitaxial wafer entirety poor, influence electronics with
The recombination luminescence in hole reduces the luminous efficiency of LED.
Optionally, the molar content of indium component can be 1%~10%, preferably 5% in gallium indium nitride layer.
It, may be due to indium component in gallium indium nitride layer if the molar content of indium component is less than 1% in gallium indium nitride layer
Molar content it is too small and cause the indium component in gallium indium nitride layer that the incorporation efficiency of gallium can not be effectively reduced, it is super that raising is not achieved
The effect of hole concentration in lattice structure；It, may be due to if the molar content of indium component is greater than 10% in gallium indium nitride layer
The molar content of indium component is too big and influence the growth quality of superlattice structure in gallium indium nitride layer, leads to the crystalline substance of epitaxial wafer entirety
Weight is poor, influences the recombination luminescence of electrons and holes, reduces the luminous efficiency of LED.
Optionally, the processing time of gallium indium nitride layer can be 5s~30s, preferably 10s.
If the processing time of gallium indium nitride layer is less than 5s, may be led since the processing time of gallium indium nitride layer is too short
The gallium atom of InGaN layer surface cannot be desorbed for cause processing, and the effect for improving hole concentration in superlattice structure is not achieved；
If the processing time of gallium indium nitride layer be greater than 30s, may it is too long due to the processing time of gallium indium nitride layer and destroy nitridation
The structure of indium gallium layer is unfavorable for improving hole concentration in superlattice structure.
Optionally, the formation time of magnesium nitride layer can be 10s~5min, preferably 3min.
If the formation time of magnesium nitride layer is less than 10s, may be caused since the formation time of magnesium nitride layer is too short
Do not have to influence the number of cavities of superlattice structure offer, limitation active layer electrons and holes are answered in enough magnesium incorporation sublayers
It closes and shines, cause the luminous efficiency of LED lower；If the formation time of magnesium nitride layer is more than 5min, may be due to magnesium nitride
The formation time of layer is too long and introduces unnecessary defect, influences the growth quality of superlattice structure, leads to epitaxial wafer entirety
Crystal quality is poor, influences the recombination luminescence of electrons and holes, reduces the luminous efficiency of LED.
Further, the flow in magnesium source can be 1 μm of ol/min~5 μm ol/min, preferably 3.8 μm of ol/min.
If less than 1 μm ol/min of the flow in magnesium source, may cause not enough since the flow in magnesium source is too small
Magnesium mixes in sublayer, influences the number of cavities of superlattice structure offer, limits the recombination luminescence of active layer electrons and holes, causes
The luminous efficiency of LED is lower；If the flow in magnesium source is greater than 5 μm of ol/min, may be introduced since the flow in magnesium source is too many
Unnecessary defect influences the growth quality of superlattice structure, causes the crystal quality of epitaxial wafer entirety poor, influence electronics and
The recombination luminescence in hole reduces the luminous efficiency of LED.
Specifically, the material of buffer layer can use aluminium nitride (AlN) or gallium nitride (GaN).The material of n type semiconductor layer
Material can use the gallium nitride of n-type doping, and n-type doping can be silicon (Si) doping or germanium (Ge) doping.The material of Quantum Well
InGaN (InGaN) can be used, the material that quantum is built can use gallium nitride.
Further, which may include:
The first step, using physical vapour deposition (PVD) (English: Physical Vapor Deposition, abbreviation: PVD) technology
It is formed on the substrate with a thickness of the buffer layer of 15nm~35nm (preferably 25nm)；
Second step, controlled at 1000 DEG C~1100 DEG C (preferably 1050 DEG C), pressure is 200torr~300torr
(preferably 250torr), growth thickness is the n type semiconductor layer of 1 μm~5 μm (preferably 3 μm) on the buffer layer, and N-type is partly led
The doping concentration of N type dopant is 10 in body layer18cm-3~1019cm-3(preferably 5*1018cm-3)；
Third step, control pressure are 100torr~500torr (preferably 300torr), are grown on n type semiconductor layer
Active layer, active layer include that multiple Quantum Well of alternating growth and multiple quantum are built；The quantity that the quantity and quantum of Quantum Well are built
Identical, the quantity that quantum is built is 5~15 (preferably 10)；Quantum Well with a thickness of 2.5nm~3.5nm (preferably
3nm), the growth temperature of Quantum Well is 720 DEG C~829 DEG C (preferably 770 DEG C)；Quantum build with a thickness of 9nm~20nm (preferably
For 15nm), the growth temperature that quantum is built is 850 DEG C~959 DEG C (preferably 900 DEG C)；
4th step, the growing low temperature P-type layer on active layer；
5th step grows high temperature P-type layer in low temperature P-type layer.
Optionally, before second step, which can also include:
Undoped gallium nitride layer is grown on the buffer layer.
Correspondingly, n type semiconductor layer is grown on undoped gallium nitride layer.
Specifically, undoped gallium nitride layer is grown on the buffer layer, may include:
Controlled at 800 DEG C~1180 DEG C (preferably 1040 DEG C), pressure be 120torr~600torr (preferably
360torr), on the buffer layer growth thickness be 1 μm~5 μm (preferably 3 μm) undoped gallium nitride layer.
In specific implementation, buffer layer is the gallium nitride of the layer of low-temperature epitaxy on substrate first, therefore also referred to as
For low temperature buffer layer.The longitudinal growth for carrying out gallium nitride in low temperature buffer layer again will form multiple mutually independent three-dimensional islands
Structure, referred to as three-dimensional nucleating layer；Then gallium nitride is carried out between each three-dimensional island structure on all three-dimensional island structures
Cross growth, form two-dimension plane structure, referred to as two-dimentional retrieving layer；It is finally one layer of high growth temperature thicker on two-dimensional growth layer
Gallium nitride, referred to as high temperature buffer layer.Three-dimensional nucleating layer, two-dimentional retrieving layer and high temperature buffer layer are referred to as not in the present embodiment
Doped gallium nitride layer.
Optionally, before third step, which can also include:
The growth stress releasing layer on n type semiconductor layer.
Correspondingly, active layer is grown on stress release layer.
Specifically, stress release layer may include multiple first sublayers and multiple second sublayers, multiple first sublayers and more
A alternately laminated setting of second sublayer；The material of first sublayer can use InGaN, and the material of the second sublayer can use
Gallium nitride.The thickness of gallium indium nitride layer can be 1nm~3nm, preferably 2nm；The thickness of gallium nitride layer can for 20nm~
40nm, preferably 30nm；The quantity of gallium indium nitride layer and the quantity of gallium nitride layer are identical, and the quantity of gallium nitride layer can be 3
~9, preferably 6.
Further, the growth stress releasing layer on n type semiconductor layer may include:
Controlled at 550 DEG C~900 DEG C (preferably 755 DEG C), pressure be 50torr~500torr (preferably
400torr), the growth stress releasing layer on n type semiconductor layer.
Optionally, before the 5th step, which can also include:
Electronic barrier layer is grown in low temperature P-type layer.
Correspondingly, high temperature P-type layer is grown on electronic barrier layer.
Specifically, the material of electronic barrier layer can be using the aluminium gallium nitride alloy (AlGaN) of p-type doping, such as AlyGa1-yN,
0.1 < y < 0.5.
Further, electronic barrier layer is grown in low temperature P-type layer, may include:
Controlled at 900 DEG C~1000 DEG C (preferably 950 DEG C), pressure be 100torr~600torr (preferably
350torr), in low temperature P-type layer growth thickness be 50nm~150nm (preferably 100nm) electronic barrier layer.
Preferably, before growing electronic barrier layer on active layer, which can also include:
The growing low temperature P-type layer on active layer.
Correspondingly, electronic barrier layer is grown in low temperature P-type layer.
Specifically, the growing low temperature P-type layer on active layer may include:
Controlled at 700 DEG C~900 DEG C (preferably 800 DEG C), pressure be 150torr~250torr (preferably
200torr), the growing low temperature P-type layer on active layer.
Optionally, after the 5th step, which can also include:
The growing P-type contact layer in high temperature P-type layer.
Specifically, the material of p-type contact layer can be using the gallium nitride and N-type that the InGaN of p-type doping, p-type are adulterated
One of gallium nitride of doping, to reduce the potential barrier of Ohmic contact between epitaxial material and chip structure.
Further, the growing P-type contact layer in high temperature P-type layer may include:
Controlled at 700 DEG C~800 DEG C (preferably 750 DEG C), pressure be 300torr~600torr (preferably
450torr), the growing P-type contact layer in high temperature P-type layer.
It should be noted that after above-mentioned epitaxial growth terminates, can first by temperature be reduced to 500 DEG C~900 DEG C (preferably
It is 800 DEG C), the annealing of 5 minutes~15 minutes (preferably 10 minutes) is carried out to epitaxial wafer in nitrogen atmosphere, then again
The temperature of epitaxial wafer is reduced to room temperature, terminates epitaxy technique growth.
Control temperature, pressure each mean temperature, pressure, such as model in the reaction chamber of control growth epitaxial wafer
Metallo-organic compound chemical gaseous phase deposition (the English: Metal Organic Chemical Vapor of VeecoK465i C4
Deposition, referred to as: MOCVD) temperature, the pressure in equipment.With high-purity hydrogen or high pure nitrogen or hydrogen when realization
The mixed gas of gas and nitrogen is as carrier gas, and high-purity ammonia is as nitrogen source, trimethyl gallium or triethyl-gallium as gallium source, trimethyl
Indium is as indium source, and trimethyl aluminium is as silicon source, and silane is as N type dopant, and two luxuriant magnesium are as P-type dopant.
The embodiment of the invention provides a kind of LED epitaxial slice, it is suitable for using preparation method system shown in FIG. 1
It is standby to form.Fig. 3 is a kind of structural schematic diagram of LED epitaxial slice provided in an embodiment of the present invention, and referring to Fig. 3, this shines
Diode epitaxial slice includes substrate 10, buffer layer 20, n type semiconductor layer 30, active layer 40, low temperature P-type layer 50 and high temperature P-type layer
60, buffer layer 20, n type semiconductor layer 30, active layer 40, low temperature P-type layer 50 and high temperature P-type layer 60 are sequentially laminated on substrate 10
On.
In the present embodiment, the growth temperature of low temperature P-type layer 50 is lower than the growth temperature of high temperature P-type layer 60.Low temperature P-type layer
At least one of 50 and high temperature P-type layer 60 are superlattice structure, and Fig. 4 is the knot of superlattice structure provided in an embodiment of the present invention
Structure schematic diagram, referring to fig. 4, superlattice structure 100 include the multiple sublayers 200 stacked gradually, and each sublayer 200 includes successively layer
Folded gallium indium nitride layer 300 and magnesium nitride layer 400, gallium indium nitride layer 300 are passed through ammonia and load before the stacking of magnesium nitride layer 400
Gas is treated.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of preparation method of LED epitaxial slice, which is characterized in that the preparation method includes:
One substrate is provided；
Successively grown buffer layer, n type semiconductor layer, active layer, low temperature P-type layer and high temperature P-type layer over the substrate are described low
The growth temperature of warm P-type layer is lower than the growth temperature of the high temperature P-type layer；
Wherein, at least one of the low temperature P-type layer and the high temperature P-type layer are superlattice structure, the superlattice structure
Including the multiple sublayers stacked gradually, each sublayer is formed in the following way:
It is continually fed into indium source, gallium source, ammonia and carrier gas, forms gallium indium nitride layer；
Stopping is passed through indium source and gallium source, while continuing to be passed through ammonia and carrier gas, handles the gallium indium nitride layer；
Start to be passed through magnesium source, while continuing to be passed through ammonia and carrier gas, forms magnesium nitride layer on the gallium indium nitride layer.
2. preparation method according to claim 1, which is characterized in that the carrier gas is the mixed gas of nitrogen and hydrogen,
It grows when ratio shared by hydrogen is less than the growth high temperature P-type layer in the carrier gas when low temperature P-type layer in the carrier gas
Ratio shared by hydrogen.
3. preparation method according to claim 1 or 2, which is characterized in that the quantity of the sublayer is 5~30.
4. preparation method according to claim 1 or 2, which is characterized in that the gallium indium nitride layer with a thickness of 10nm~
50nm。
5. preparation method according to claim 1 or 2, which is characterized in that the processing time of the gallium indium nitride layer is 5s
~30s.
6. preparation method according to claim 1 or 2, which is characterized in that the formation time of the magnesium nitride layer be 10s~
5min。
7. preparation method according to claim 1 or 2, which is characterized in that formation of the growth temperature in the single sublayer
It remains unchanged in the process.
8. preparation method according to claim 1 or 2, which is characterized in that the growth temperature of the low temperature P-type layer is 750
DEG C~800 DEG C.
9. preparation method according to claim 1 or 2, which is characterized in that the growth temperature of the high temperature P-type layer is 950
DEG C~1000 DEG C.
10. a kind of LED epitaxial slice, the LED epitaxial slice include substrate, buffer layer, n type semiconductor layer,
Active layer, low temperature P-type layer and high temperature P-type layer, the buffer layer, the n type semiconductor layer, the active layer, the low temperature p-type
Layer and the high temperature P-type layer stack gradually over the substrate, and the growth temperature of the low temperature P-type layer is lower than the high temperature p-type
The growth temperature of layer；It is characterized in that, at least one of the low temperature P-type layer and the high temperature P-type layer are superlattice structure,
The superlattice structure includes the multiple sublayers stacked gradually, and each sublayer includes the gallium indium nitride layer and nitrogen stacked gradually
Change magnesium layer, the gallium indium nitride layer is passed through ammonia before the magnesium nitride layer stackup and carrier gas is treated.
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| CN114639759A (en) * | 2022-05-11 | 2022-06-17 | 江西兆驰半导体有限公司 | Light emitting diode epitaxial wafer and preparation method thereof |
| CN116454184A (en) * | 2023-06-16 | 2023-07-18 | 江西兆驰半导体有限公司 | High-light-efficiency LED epitaxial wafer, preparation method thereof and LED |
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