CN109103238A - Groove MOSFET and its manufacturing method - Google Patents
Groove MOSFET and its manufacturing method Download PDFInfo
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- CN109103238A CN109103238A CN201810919959.3A CN201810919959A CN109103238A CN 109103238 A CN109103238 A CN 109103238A CN 201810919959 A CN201810919959 A CN 201810919959A CN 109103238 A CN109103238 A CN 109103238A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 129
- 229920005591 polysilicon Polymers 0.000 claims abstract description 118
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 86
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 86
- 239000010703 silicon Substances 0.000 claims abstract description 86
- 238000010276 construction Methods 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims description 185
- 239000000758 substrate Substances 0.000 claims description 49
- 229910052751 metal Inorganic materials 0.000 claims description 47
- 239000002184 metal Substances 0.000 claims description 47
- 239000011229 interlayer Substances 0.000 claims description 45
- 238000000034 method Methods 0.000 claims description 34
- 230000008569 process Effects 0.000 claims description 26
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 21
- 229910052721 tungsten Inorganic materials 0.000 claims description 21
- 239000010937 tungsten Substances 0.000 claims description 21
- 238000000407 epitaxy Methods 0.000 claims description 13
- 239000012790 adhesive layer Substances 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 230000001413 cellular effect Effects 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 238000003701 mechanical milling Methods 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 description 18
- 230000006872 improvement Effects 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000009415 formwork Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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Abstract
The invention discloses a kind of groove MOSFETs, groove MOSFET is made of multiple device unit constructions, the groove of trench gate is defined using hard mask layer, the definition of the autoregistration to the first contact hole across source region between groove is able to achieve by carrying out lateral etching to hard mask layer after etching groove, it is by progress after filling polysilicon in the trench using polysilicon gate as the etching of the hard mask layer of exposure mask and gate oxide that the autoregistration of first contact hole, which defines, polysilicon is filled in the opening of the first contact hole using gate oxide as the silicon etching of exposure mask and by exposure mask of gate oxide to realize.The invention also discloses a kind of manufacturing methods of groove MOSFET.The present invention autoregistration can define the contact hole across source region between trench gate, can reduce the size of device, increase gully density and reduce conducting resistance.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing fields, more particularly to a kind of groove MOSFET.The present invention also relates to
And a kind of manufacturing method of groove MOSFET.
Background technique
In semiconductor integrated circuit, at present the common lesser groove MOSFET of cellular size structure as shown in Figure 1,
This structure is generally used in 1.0 microns to 1.8 microns cellular size designs.It is formed in semiconductor substrate such as silicon substrate 101
There is semiconductor epitaxial layers such as silicon epitaxy layer 102, is sequentially formed with 105 He of body area (body) on the surface of semiconductor epitaxial layers 102
Source region 106；Be formed with multiple gate trench in the semiconductor epitaxial layers 102, the gate trench bottom surface and
Side is formed with gate dielectric layer such as gate oxide 103, is filled in the gate trench for being formed with the gate dielectric layer 103
Polysilicon gate 104.
It is formed with interlayer film 107 on 102 surface of semiconductor epitaxial layers, contact hole 109 passes through interlayer film 107 and bottom
Source region 106 or polysilicon gate 104 connect.The bottom of contact hole 109 corresponding to source region 106 is also formed with body area draw-out area
108.Only used by the contact hole 109 at the top of the polysilicon gate being located at outside device area and the corresponding polysilicon gate of contact hole 109
104a is marked, and gate dielectric layer is marked with 103a, and polysilicon gate 104a is connected with the polysilicon gate 104 in device area.
It is formed with front metal layer 110 on the surface of interlayer film 107, front metal layer 110 graphically forms source electrode and grid
Pole.Wherein grid is connected with the polysilicon gate 104a outside device area by contact hole 109 and by polysilicon gate 104 and device
Polysilicon gate 104 in part region is connected；Source electrode passes through 108 phase of source region 106 and body area draw-out area of contact hole 109 and bottom
Even, body area draw-out area 108 is connected with body area 05.
In order to further enhance gully density, reduce device on-resistance (Rdon), simplest way is further to contract
Small cellular size design；During design size reduces, groove is further reduced since equipment (cost) and grid form work
The factors such as skill difficulty increase have basically reached the limit, and reduce the spacing that cellular size needs to reduce contact hole to groove merely,
Existing method will meet with not caused enough the grid source short circuit fault of alignment precision between contact hole and gate trench and fail, and channel doping is dense
Degree, which is influenced difference greatly by contact hole injection, leads to problems such as channel cut-in voltage uniformity poor, can not mass production.Specifically
Be described as follows: in the prior art, contact hole 109 is defined using photoetching process, namely defines contact hole by photoetching process
109 size and location, and gate trench and grid, which draw groove, to be defined by photoetching process, due to photoetching process
It is limited with certain precision, contact hole 109 and gate trench and grid, which draw the position of groove and width, to be had in photoetching process
Accuracy rating in deviation, the precision bring deviation of this photoetching process make when making trench-gate power transistor need
The register redundancy between groove, contact hole 109 are drawn in view of contact hole 109 and the groove such as gate trench and grid of bottom
Gap between groove, which wants sufficiently large, can just prevent threshold voltage i.e. channel cut-in voltage caused by covering partially because of the exposure of contact hole 109
The problems such as drift.Which limits increase gully density by platform size between reduction of gate groove to reduce conducting resistance
Possibility.Namely the spacing between the gate trench of the prior art has a limiting value relevant with photoetching process, Bu Nengzai
It reduces, so that gully density can not be increased by the spacing between reduction of gate groove further to reduce electric conduction
Resistance.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of groove MOSFETs, autoregistration can define between trench gate
Out across the contact hole of source region, the size of device can be reduced, increase gully density and reduces conducting resistance.For this purpose, the present invention is also
A kind of manufacturing method of groove MOSFET is provided.
In order to solve the above technical problems, groove MOSFET provided by the invention is made of multiple device unit constructions.
Each device unit construction all includes:
Trench gate, the trench gate include groove, the gate oxide for being formed in the groove side surface and bottom surface and fill out
Fill the polysilicon gate in the groove.
The groove is formed on silicon substrate, is formed with the body area of the second conduction type doping, institute on the silicon substrate
Groove is stated across the body area, is formed with the source region of the first conduction type heavy doping on the surface in the body area.
The arrangement architecture of each device unit construction in the groove MOSFET are as follows:
Each trench gate is arranged in parallel, and the source region and the body area between the two neighboring trench gate share,
The first contact hole is formed between the two neighboring trench gate, first contact hole passes through the corresponding source region and institute
The area Shu Ti.
First contact hole has following self-alignment structure:
The groove is defined by the hard mask layer for being formed in the surface of silicon, and the hard mask layer is unfolded into
The first opening define the forming region of the groove, after forming the groove, the hard mask layer by transverse direction
The second opening for etching and first enlarged open being made to form the width for being greater than the groove, the gate oxide and described more
Crystal silicon grid are formed in the groove and second opening.
The hard mask layer and the grid between lower second opening are defined in the autoregistration of the polysilicon gate
Oxide layer is removed and is formed third opening, and the third opening exposes the surface of the silicon substrate.
Comprehensive silicon etching, which is carried out, as exposure mask using the gate oxide forms described first in the bottom that the third is open
Corresponding 4th opening of contact hole, which simultaneously returns the polysilicon gate, to be carved into below the top surface of the groove and institute
State the bottom surface of source region or more.
The second polysilicon layer, which is filled up completely, in the 4th opening as exposure mask autoregistration using the gate oxide forms institute
It states the first contact hole and is superimposed second polysilicon layer in the polycrystalline silicon gate surface simultaneously.
Interlayer film is filled in the groove at the top of the polysilicon gate, the interlayer film is by outside with the groove
The surface of silicon be stop-layer return carving technology autoregistration be located in the groove and and the groove outside the silicon
Substrate surface is equal, and the remaining gate oxide returns carving technology removal also by the interlayer film outside the groove.
The groove of each device unit construction is connected together and polysilicon gate all links together, in selected institute
It states and is formed with the second contact hole at the top of the polysilicon gate of device unit construction, second contact hole passes through the interlayer
Film.
The graphic structure composition grid and source electrode of front metal layer, the corresponding front metal layer of the grid are covered on described
It is connected in the corresponding interlayer film surface of second contact hole and by second contact hole with the polysilicon gate, the source
Extremely corresponding front metal layer is covered on the table of the source region except the grid, the interlayer film and first contact hole
Face, has interval between the corresponding front metal layer of source electrode and the corresponding front metal layer of the grid, the source electrode is logical
It crosses first contact hole and connects the source region and the body area.
A further improvement is that the drain region of the first conduction type heavy doping is formed at the back side of the silicon substrate, in institute
State the silicon substrate composition drift region between drain region and the body area.
The drain electrode being made of metal layer on back is formed at the back side in the drain region.
A further improvement is that being formed with the silicon epitaxy layer of the first conduction type, the body on the surface of the silicon substrate
Area, the source region and the drift region are formed in the silicon epitaxy layer.
A further improvement is that the material of the hard mask layer is oxide layer.
A further improvement is that being filled with tungsten layer in second contact hole.
A further improvement is that being formed with barrier layer and adhesive layer between the tungsten layer and silicon of second contact hole.
A further improvement is that groove MOSFET is N-type device, the first conduction type is N-type, and the second conduction type is P
Type；Alternatively, groove MOSFET is P-type device, the first conduction type is p-type, and the second conduction type is N-type.
In order to solve the above technical problems, the manufacturing method of groove MOSFET provided by the invention includes the following steps:
Step 1: forming hard mask layer in surface of silicon.
Step 2: carry out chemical wet etching forms the first opening in the hard mask layer, first opening is defined
The forming region of groove.
Step 3: being performed etching as exposure mask to the silicon substrate using the hard mask layer and at the bottom of first opening
Portion forms the groove；Groove MOSFET is made of multiple device unit constructions, and each device unit construction all includes
Groove is stated, each groove is arranged in parallel.
It is greater than the groove Step 4: carrying out lateral etching to the hard mask layer and forming first enlarged open
Width second opening.
Step 5: forming gate oxide, the gate oxide is located at the inner surface of the groove and extends to the ditch
The surface of the silicon substrate of second open bottom outside slot.
It is carved Step 6: using polycrystalline silicon deposit and being returned using the hard mask layer as the chemical mechanical milling tech of stop-layer
Polysilicon gate is formed, the polysilicon gate is filled in the groove and second opening.
Step 7: using the polysilicon gate as autoregistration exposure mask by it is described second opening between the hard mask layer and
The gate oxide removes and is formed third opening, and the third opening exposes the surface of the silicon substrate.
Step 8: carrying out comprehensive silicon etching as exposure mask using the gate oxide forms the in the bottom that the third is open
Four openings, which simultaneously return the polysilicon gate, to be carved into below the top surface of the groove.
Step 9: being filled up completely the second polysilicon layer in the 4th opening using the gate oxide as exposure mask autoregistration
It forms first contact hole and is superimposed second polysilicon layer in the polycrystalline silicon gate surface simultaneously.
Step 10: forming the body area of the second conduction type doping on the silicon substrate, formed on the surface in the body area
The source region of first conduction type heavy doping；The groove passes through the body area, the source region between the two neighboring groove
It is shared with the body area, the top surface of the polysilicon gate is located at the bottom surface of the source region or more, the 4th opening
Across the corresponding source region.
11, deposit forms interlayer film；The surface of silicon outside using the groove carries out the interlayer as stop-layer
Film return carve, the interlayer film autoregistration of Hui Kehou be located in the groove and and the groove outside the surface of silicon
Equal, the remaining gate oxide returns carving technology removal also by the interlayer film outside the groove.
Step 12: the groove of each device unit construction is connected together and polysilicon gate all links together,
The second contact hole is formed at the top of the polysilicon gate of the selected device unit construction, second contact hole passes through
The interlayer film.
Step 13: forming front metal layer, shape is patterned to the front metal layer using lithographic etch process
At grid and source electrode, the corresponding front metal layer of the grid is covered on the corresponding interlayer film surface of second contact hole
Upper and connected by second contact hole with the polysilicon gate, the corresponding front metal layer of the source electrode is covered on the grid
The surface of the source region, the interlayer film and first contact hole except pole, the corresponding front metal layer of the source electrode and
There is interval between the corresponding front metal layer of the grid, the source electrode by first contact hole connect the source region with
The body area.
A further improvement is that further including following back process after the patterning process of the front metal layer is completed:
Form the drain region of the first conduction type heavy doping at the back side of the silicon substrate, the drain region and the body area it
Between the silicon substrate form drift region；
Metal layer on back is formed at the back side in the drain region and drain electrode is formed by metal layer on back.
A further improvement is that being formed with the silicon epitaxy layer of the first conduction type, the body on the surface of the silicon substrate
Area, the source region and the drift region are formed in the silicon epitaxy layer.
A further improvement is that step 9 include it is following step by step:
Step 9a, deposit forms the second polysilicon layer and is filled up completely the 4th opening, and second polysilicon layer is also
It is formed in the side of the groove at the top of the polycrystalline silicon gate surface and the polysilicon gate, second polysilicon layer is also
Extend to the surface of the 4th opening and the gate oxide outside the groove；
Step 9b, carrying out polysilicon time quarter will be positioned at the gate oxide outside the 4th opening and the groove
Second polysilicon layer of surface and the groove side surface at the top of the polysilicon gate all removes, the institute of Hui Kehou
First contact hole will be filled up completely and formed in the 4th opening by stating the second polysilicon layer, in the polycrystalline silicon gate surface
Also it is superimposed with second polysilicon layer.
A further improvement is that the material of the hard mask layer is oxide layer.
A further improvement is that step 12 include it is following step by step:
Step 12a, the 5th opening is formed in the forming region of second contact hole using lithographic etch process；
Step 12b, it carries out tungsten deposition and returning for tungsten is engraved in filling tungsten in the 5th opening and forms second contact
Hole.
A further improvement is that further including the step to form barrier layer and adhesive layer before the tungsten deposition for carrying out step 12b
Suddenly.
A further improvement is that groove MOSFET is N-type device, the first conduction type is N-type, and the second conduction type is P
Type；Alternatively, groove MOSFET is P-type device, the first conduction type is p-type, and the second conduction type is N-type.
The present invention using define groove hard mask layer come between groove autoregistration define the contact across source region
Hole i.e. the first contact hole is mainly open by the first enlarged open and formation second that will define the hard mask layer of groove,
After forming gate oxide and polysilicon gate in groove and the second opening, hard mask layer and gate oxidation between the second opening
Layer can do exposure mask by the polysilicon gate in the second opening and autoregistration removal beats the region of the first contact hole to be formed
The third opening opened；Later, the can be formed in the bottom that third is open by carrying out comprehensive silicon etching as exposure mask using gate oxide
One contact hole the corresponding 4th is open and polysilicon gate time is carved into the top surface lower than groove, subsequent still with gate oxidation
Layer is that the autoregistration of exposure mask energy is filled up completely the second polysilicon layer the first contact hole of formation and simultaneously in polysilicon in the 4th opening
Grid surface is superimposed the second polysilicon layer；It is subsequent only to be filled out in the groove at the top of polysilicon gate by depositing and returning the method carved
Interlayer film is filled, the autoregistration between trench gate can be thus fully achieved and define contact hole across source region, can finally reduce
The size of device increases gully density and reduces conducting resistance.
In addition, since the first contact hole of the invention does not need to use lithographic definition, therefore one layer of light shield can also be saved, it can drop
Low process costs.
In addition, the first contact hole of the invention uses the structure of polysilicon filling, the formation work of body area and source region can be facilitated
Skill enables the formation process of the area Zhong Ti of the present invention and source region to be placed on after the first contact hole is formed and carries out.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the structural schematic diagram of existing groove MOSFET；
Fig. 2 is the structural schematic diagram of groove MOSFET of the embodiment of the present invention；
Fig. 3 A- Fig. 3 V is the device architecture schematic diagram in each step of manufacturing method of groove MOSFET of the embodiment of the present invention.
Specific embodiment
As shown in Fig. 2, being the structural schematic diagram of groove MOSFET of the embodiment of the present invention；Groove MOSFET of the embodiment of the present invention
It is made of multiple device unit constructions.Each device unit construction all includes:
Trench gate, the trench gate include groove 302, the gate oxidation for being formed in groove 302 side and bottom surface
Layer 4 and the polysilicon gate 5 being filled in the groove 302.Groove 302 please refers to shown in Fig. 3 D.
The groove 302 is formed on silicon substrate 1, and the body of the second conduction type doping is formed on the silicon substrate 1
Area 2, the groove 302 pass through the body area 2, are formed with the source region of the first conduction type heavy doping on the surface in the body area 2
3。
The arrangement architecture of each device unit construction in the groove MOSFET are as follows:
Each trench gate is arranged in parallel, and the source region 3 and the body area 2 between the two neighboring trench gate are total
With being formed with the first contact hole 6 between the two neighboring trench gate, first contact hole 6 passes through the corresponding source
Area 3 and the body area 2.
First contact hole 6 has following self-alignment structure:
The groove 302 is defined by the hard mask layer 201 for being formed in 1 surface of silicon substrate, the hard mask layer
201 the first openings 301 being unfolded into define the forming region of the groove 302, after forming the groove 302, institute
That states hard mask layer 201 is made 301 expansion of the first opening form the width for being greater than the groove 302 by lateral etching
Second opening 303, the gate oxide 4 and the polysilicon gate 5 are formed in the groove 302 and second opening 303.
First opening 301 please refers to shown in Fig. 3 C, and second opening 303 please refers to shown in Fig. 3 E.
201 He of the hard mask layer between lower second opening 303 is defined in the autoregistration of the polysilicon gate 5
The gate oxide 4 is removed and is formed third opening 304, and the third opening 304 exposes the surface of the silicon substrate 1.
The third opening 304 please refers to shown in Fig. 3 I.
With the gate oxide 4 be exposure mask carry out comprehensive silicon etching formed in the bottom of third opening 304 it is described
The polysilicon gate 5 is returned the top table being carved into positioned at the groove 302 simultaneously by corresponding 4th opening 305 of the first contact hole 6
Below face and more than the bottom surface of the source region 3.The third opening 304 please refers to shown in Fig. 3 J.
It is that exposure mask autoregistration is filled up completely 6 shape of the second polysilicon layer in the 4th opening 305 with the gate oxide 4
At first contact hole 6 and simultaneously in 5 surface of polysilicon gate superposition, second polysilicon layer 6.In Fig. 2, described
The second polysilicon layer and first contact hole filled in four openings 305 all use label 6 to indicate.
It is filled with interlayer film 7 in the groove 302 at 5 top of the polysilicon gate, the interlayer film 7 is by with described
1 surface of the silicon substrate outside groove 302 is located in the groove 302 for time carving technology autoregistration of stop-layer and and the ditch
1 surface of the silicon substrate outside slot 302 is equal, and the remaining gate oxide 4 is also by the interlayer film outside the groove 302
7 carving technology that returns removes.
The groove 302 of each device unit construction is connected together and polysilicon gate 5 all links together, selected
The top of the polysilicon gate 5 of the device unit construction be formed with the second contact hole 9, second contact hole 9 passes through
The interlayer film 7.
The graphic structure composition grid and source electrode of front metal layer 10, the corresponding front metal layer 10 of the grid are covered on
Connect on corresponding 7 surface of interlayer film of second contact hole 9 and by second contact hole 9 and the polysilicon gate 5
It connects, the corresponding front metal layer 10 of the source electrode is covered on the source region 3 except the grid, the interlayer film 7 and described
The surface of first contact hole 6, between the corresponding front metal layer 10 of source electrode and the corresponding front metal layer 10 of the grid
With interval, the source electrode connects the source region 3 and the body area 2 by first contact hole 6.
It is formed with the drain region of the first conduction type heavy doping at the back side of the silicon substrate 1, in the drain region and the body
The silicon substrate 1 between area 2 forms drift region.
The drain electrode being made of metal layer on back 11 is formed at the back side in the drain region.
The silicon epitaxy layer of the first conduction type, the body area 2,3 and of the source region are formed on the surface of the silicon substrate 1
The drift region is formed in the silicon epitaxy layer.
The material of the hard mask layer 201 is oxide layer.
Tungsten layer is filled in second contact hole 9.In the embodiment of the present invention, second contact hole and the tungsten layer are all
It is indicated using label 9.
Barrier layer and adhesive layer 8 are formed between the tungsten layer 9 and silicon of second contact hole 9, barrier layer and adhesive layer 8 are
Alternative construction can not also form barrier layer and adhesive layer 8, not show in Fig. 2 and be formed with barrier layer and adhesive layer 8.
In the embodiment of the present invention, groove MOSFET is N-type device, and the first conduction type is N-type, and the second conduction type is P
Type.Also can in other embodiments are as follows: groove MOSFET is P-type device, and the first conduction type is p-type, and the second conduction type is N
Type.
The embodiment of the present invention using define groove 302 hard mask layer 201 come between groove 302 autoregistration define
Across contact hole i.e. the first contact hole 6 of source region 3, mainly by being opened the first of the hard mask layer 201 for defining groove 302
Mouthfuls 301 expand and simultaneously form the second opening 303, formed in groove 302 and the second opening 303 gate oxide 4 and polysilicon gate 5 it
Afterwards, the hard mask layer 201 between the second opening 303 and gate oxide 4 can pass through the polysilicon gate 5 in the second opening 303
Exposure mask and autoregistration removal are done to form the third for opening the region of the first contact hole 6 opening 304；Later, with gate oxidation
Layer 4, which carries out comprehensive silicon etching for exposure mask, to form corresponding 4th opening of the first contact hole 6 in the bottom of third opening 304
305 and polysilicon gate 5 is returned to the top surface being carved into lower than groove 302, subsequent is still that exposure mask can be from right with gate oxide 4
Standard is filled up completely the second polysilicon layer 6 in the 4th opening 305 and forms the first contact hole 6 and fold simultaneously on 5 surface of polysilicon gate
Add the second polysilicon layer 6；It is subsequent only to be filled in the groove 302 at 5 top of polysilicon gate by depositing and returning the method carved
Interlayer film 7 can thus fully achieve the autoregistration between trench gate and define the contact hole across source region 3, can finally reduce
The size of device increases gully density and reduces conducting resistance.
In addition, since the first contact hole 6 of the embodiment of the present invention does not need to use lithographic definition, therefore one layer of light can also be saved
Cover, can reduce process costs.
In addition, the first contact hole 6 of the embodiment of the present invention can facilitate body area 2 and source region 3 using the structure of polysilicon filling
Formation process, enable the formation process of the area Zhong Ti of the embodiment of the present invention 2 and source region 3 to be placed on 6 formation of the first contact hole
After carry out.
In addition, the first contact hole of the embodiment of the present invention uses the structure of polysilicon filling, body area and source region can be facilitated
Formation process enables the formation process of the area Zhong Ti of the embodiment of the present invention and source region to be placed on the laggard of the first contact hole formation
Row.
It is the device architecture in each step of manufacturing method of groove MOSFET of the embodiment of the present invention as shown in Fig. 3 A to Fig. 3 V
The manufacturing method of schematic diagram, groove MOSFET of the embodiment of the present invention includes the following steps:
Step 1: as shown in Figure 3A, forming hard mask layer 201 on 1 surface of silicon substrate.
The material of the hard mask layer 201 is oxide layer.
Step 2: as shown in Figure 3B, carrying out photoetching process and forming photoetching offset plate figure 202；As shown in Figure 3 C, with the photoetching
Glue pattern 202 is that exposure mask performs etching the first opening 301 of formation in the hard mask layer 201, and first opening 301 is fixed
Justice goes out the forming region of groove 302.The photoetching offset plate figure 202 is removed later.
Step 3: as shown in Figure 3D, with the hard mask layer 201 be exposure mask the silicon substrate 1 is performed etching and
The groove 302 is formed on the bottom of first opening 301.
Groove MOSFET is made of multiple device unit constructions, and each device unit construction all includes the groove
302, each groove 302 is arranged in parallel.
Step 4: as shown in FIGURE 3 E, carrying out lateral etching to the hard mask layer 201 expands first opening 301
Big the second opening 303 for forming the width for being greater than the groove 302.
Step 5: as illustrated in Figure 3 F, forming gate oxide 4, the gate oxide 4 is located at the inside table of the groove 302
Face and extend to outside the groove 302 it is described second opening 303 bottoms the silicon substrate 1 surface.
Step 6: as shown in Figure 3 G, carrying out polycrystalline silicon deposit and forming polysilicon layer 5a.
As shown in figure 3h, the chemical mechanical milling tech with the hard mask layer 202 for stop-layer, which returns to carve, forms polycrystalline
Si-gate 5, the polysilicon gate 5 are filled in the groove 302 and second opening 303.
Step 7: being that autoregistration exposure mask will be between second opening 303 with the polysilicon gate 5 as shown in fig. 31
The hard mask layer 201 and the gate oxide 4 remove and simultaneously form third opening 304, and the third opening 304 is by the silicon
Expose on the surface of substrate 1.
Step 8: being that the comprehensive silicon etching of exposure mask progress is open in the third with the gate oxide 4 as shown in figure 3j
304 bottom formed the 4th opening 305 polysilicon gate 5 is returned simultaneously be carved into top surface positioned at the groove 302 with
Under.
Step 9: being that exposure mask autoregistration is filled up completely the second polycrystalline in the 4th opening 305 with the gate oxide 4
Silicon layer 6 forms first contact hole 6 and is superimposed second polysilicon layer 6 on 5 surface of polysilicon gate simultaneously.
Step 9 include it is following step by step:
Step 9a, as shown in Fig. 3 K, deposit forms the second polysilicon layer 6a and is filled up completely the 4th opening 305, institute
State the groove 302 that the second polysilicon layer 6a is also formed at the top of 5 surface of polysilicon gate and the polysilicon gate 5
Side, the second polysilicon layer 6a also extend into the gate oxide outside the 4th opening 305 and the groove 302
4 surface.
Step 9b, it as shown in figure 3l, carries out that the 4th opening 305 and the groove 302 will be located at polysilicon time quarter
More than described the second of the surface of the outer gate oxide 4 and 302 side of the groove positioned at 5 top of the polysilicon gate
Crystal silicon layer 6a is removed, and the second polysilicon layer 6a of Hui Kehou will be filled up completely in the 4th opening 305 and form institute
The first contact hole 6 is stated, is also superimposed with the second polysilicon layer 6a on 5 surface of polysilicon gate.
Step 10: as shown in fig.3m, forming the body area 2 of the second conduction type doping on the silicon substrate 1.The body area
2 add annealing to promote using comprehensive ion implanting forms.
As shown in Fig. 3 N, the source region 3 of the first conduction type heavy doping is formed on the surface in the body area 2.It carries out comprehensive
Source ion injection injects to form the source region 3 using lithographic definition in selection area progress source ion.
The groove 302 passes through the body area 2, the source region 3 and the body area between the two neighboring groove 302
2 share, and the top surface of the polysilicon gate 5 is located at the bottom surface of the source region 3 or more, and the 4th opening 305 passes through
The corresponding source region 3.
11, as shown in Fig. 3 O, deposit forms interlayer film 7.
As shown in Fig. 3 P, the interlayer film 7 is carried out as stop-layer using 1 surface of the silicon substrate outside the groove 302
Return and carve, 7 autoregistration of the interlayer film of Hui Kehou be located in the groove 302 and with the silicon substrate 1 outside the groove 302
Surface is equal, and the remaining gate oxide 4 returns carving technology removal also by the interlayer film 7 outside the groove 302.
The carving technology that returns of the interlayer film 7 includes etching and chemical mechanical milling tech.
Step 12: the groove 302 of each device unit construction is connected together and polysilicon gate as shown in Fig. 3 Q
5 all link together, and form the second contact hole 9, institute at the top of the polysilicon gate 5 of the selected device unit construction
The second contact hole 9 is stated across the interlayer film 7.
Step 12a, as shown in Fig. 3 Q, photoetching offset plate figure 203 is formed using photoetching process.
It is that exposure mask performs etching to form the 5th in the forming region of second contact hole 9 with photoetching offset plate figure 203
Opening 306；
As shown in Fig. 3 R, photoetching offset plate figure 204 is removed.
Step 12b, it as shown in Fig. 3 T, carries out tungsten deposition and returning for tungsten is engraved in filling tungsten and shape in the 5th opening 306
At second contact hole 9.
In other embodiments, moreover it is possible to include the following steps:
As shown in Fig. 3 S, barrier layer is formed and the step of adhesive layer 8.Barrier layer and adhesive layer 8 are for example, by using Ti's and TiN
Superimposed layer.
As shown in Fig. 3 T, returning to be engraved in and filling tungsten in the 5th opening 306 and form described for tungsten deposition and tungsten is carried out
Two contact holes 9.
Step 13: forming front metal layer 10 as shown in Fig. 3 U.
As shown in Fig. 3 V, photoetching offset plate figure 204 is formed using photoetching process.
It uses and shape is patterned to the front metal layer 10 for the etching technics of exposure mask with the photoetching offset plate figure 204
At grid and source electrode, the corresponding front metal layer 10 of the grid is covered on the corresponding interlayer film 7 of second contact hole 9
It is connected on surface and by second contact hole 9 and the polysilicon gate 5, the corresponding front metal layer 10 of the source electrode covers
The surface of the source region 3, the interlayer film 7 and first contact hole 6 except the grid, the source electrode are corresponding just
There is interval, the source electrode passes through first contact hole between face metal layer 10 and the corresponding front metal layer 10 of the grid
6 connect the source region 3 and the body area 2.
Further include following back process after the patterning process of the front metal layer 10 is completed:
As shown in Fig. 2, the drain region of the first conduction type heavy doping is formed at the back side of the silicon substrate 1, in the drain region
The silicon substrate 1 between the body area 2 forms drift region.
Metal layer on back 11 is formed at the back side in the drain region and drain electrode is formed by metal layer on back 11.
In present invention method, the silicon epitaxy layer of the first conduction type, institute are formed on the surface of the silicon substrate 1
The area Shu Ti 2, the source region 3 and the drift region are formed in the silicon epitaxy layer.
In present invention method, groove MOSFET is N-type device, and the first conduction type is N-type, the second conductive-type
Type is p-type.Also can in other embodiments method are as follows: groove MOSFET is P-type device, and the first conduction type is p-type, and second leads
Electric type is N-type.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of groove MOSFET, it is characterised in that: groove MOSFET is made of multiple device unit constructions；
Each device unit construction all includes:
Trench gate, the trench gate include groove, the gate oxide for being formed in the groove side surface and bottom surface and are filled in
Polysilicon gate in the groove；
The groove is formed on silicon substrate, is formed with the body area of the second conduction type doping, the ditch on the silicon substrate
Slot passes through the body area, is formed with the source region of the first conduction type heavy doping on the surface in the body area；
The arrangement architecture of each device unit construction in the groove MOSFET are as follows:
Each trench gate is arranged in parallel, and the source region and the body area between the two neighboring trench gate share, in phase
The first contact hole is formed between adjacent two trench gates, first contact hole passes through the corresponding source region and the body
Area；
First contact hole has following self-alignment structure:
The groove is defined by the hard mask layer for being formed in the surface of silicon, the hard mask layer be unfolded into
One opening defines the forming region of the groove, after forming the groove, the hard mask layer by lateral etching
And so that first enlarged open is formed the second of the width for being greater than the groove and be open, the gate oxide and the polysilicon
Grid are formed in the groove and second opening；
The hard mask layer and the gate oxidation between lower second opening are defined in the autoregistration of the polysilicon gate
Layer is removed and is formed third opening, and the third opening exposes the surface of the silicon substrate；
Comprehensive silicon etching, which is carried out, as exposure mask using the gate oxide forms first contact in the bottom that the third is open
Corresponding 4th opening in hole, which simultaneously returns the polysilicon gate, to be carved into below the top surface of the groove and the source
It is more than the bottom surface in area；
The second polysilicon layer, which is filled up completely, in the 4th opening as exposure mask autoregistration using the gate oxide forms described the
One contact hole is simultaneously superimposed second polysilicon layer in the polycrystalline silicon gate surface simultaneously；
Interlayer film is filled in the groove at the top of the polysilicon gate, the interlayer film passes through the institute outside with the groove
State surface of silicon be stop-layer return carving technology autoregistration be located in the groove and and the groove outside the silicon substrate
Surface is equal, and the remaining gate oxide returns carving technology removal also by the interlayer film outside the groove；
The groove of each device unit construction is connected together and polysilicon gate all links together, in the selected device
The second contact hole is formed at the top of the polysilicon gate of part cellular construction, second contact hole passes through the interlayer film；
The graphic structure composition grid and source electrode of front metal layer, the corresponding front metal layer of the grid are covered on described second
It is connected in the corresponding interlayer film surface of contact hole and by second contact hole with the polysilicon gate, the source electrode pair
The front metal layer answered is covered on the surface of the source region except the grid, the interlayer film and first contact hole,
There is interval, the source electrode passes through institute between the corresponding front metal layer of source electrode and the corresponding front metal layer of the grid
It states the first contact hole and connects the source region and the body area.
2. groove MOSFET as described in claim 1, it is characterised in that: be formed with the first conduction at the back side of the silicon substrate
The drain region of type heavy doping, the silicon substrate between the drain region and the body area form drift region；
The drain electrode being made of metal layer on back is formed at the back side in the drain region.
3. groove MOSFET as claimed in claim 2, it is characterised in that: be formed with the first conduction on the surface of the silicon substrate
The silicon epitaxy layer of type, the body area, the source region and the drift region are formed in the silicon epitaxy layer.
4. groove MOSFET as described in claim 1, it is characterised in that: the material of the hard mask layer is oxide layer.
5. groove MOSFET as described in claim 1, it is characterised in that: be filled with tungsten layer in second contact hole.
6. groove MOSFET as claimed in claim 5, it is characterised in that: formed between the tungsten layer and silicon of second contact hole
There are barrier layer and adhesive layer.
7. groove MOSFET as described in claim 1, it is characterised in that: groove MOSFET is N-type device, the first conduction type
For N-type, the second conduction type is p-type；Alternatively, groove MOSFET is P-type device, the first conduction type is p-type, the second conductive-type
Type is N-type.
8. a kind of manufacturing method of groove MOSFET, which comprises the steps of:
Step 1: forming hard mask layer in surface of silicon；
Step 2: carry out chemical wet etching forms the first opening in the hard mask layer, first opening defines groove
Forming region；
Step 3: being performed etching as exposure mask to the silicon substrate using the hard mask layer and in the bottom shape of first opening
At the groove；Groove MOSFET is made of multiple device unit constructions, and each device unit construction all includes the ditch
Slot, each groove are arranged in parallel；
First enlarged open is set to form the width greater than the groove Step 4: carrying out lateral etching to the hard mask layer
Second opening of degree；
Step 5: forming gate oxide, the gate oxide is located at the inner surface of the groove and extends to outside the groove
Second open bottom the silicon substrate surface；
It is formed Step 6: using polycrystalline silicon deposit and returning to carve as the chemical mechanical milling tech of stop-layer using the hard mask layer
Polysilicon gate, the polysilicon gate are filled in the groove and second opening；
Step 7: being autoregistration exposure mask by the hard mask layer and described between second opening using the polysilicon gate
Gate oxide removes and is formed third opening, and the third opening exposes the surface of the silicon substrate；
It is opened Step 8: carrying out comprehensive silicon etching using the gate oxide as exposure mask and forming the 4th in the bottom that the third is open
The polysilicon gate is returned be carved into below the top surface of the groove simultaneously by mouth；
It is formed Step 9: being filled up completely the second polysilicon layer in the 4th opening as exposure mask autoregistration using the gate oxide
First contact hole is simultaneously superimposed second polysilicon layer in the polycrystalline silicon gate surface simultaneously；
Step 10: forming the body area of the second conduction type doping on the silicon substrate, first is formed on the surface in the body area
The source region of conduction type heavy doping；The groove passes through the body area, the source region and institute between the two neighboring groove
The area Shu Ti shares, and the top surface of the polysilicon gate is located at the bottom surface of the source region or more, the described 4th be open across
The corresponding source region；
11, deposit forms interlayer film；The surface of silicon outside using the groove carries out the interlayer film as stop-layer
Return carve, the interlayer film autoregistration of Hui Kehou be located in the groove and and the groove outside the surface of silicon phase
Flat, the remaining gate oxide returns carving technology removal also by the interlayer film outside the groove；
Step 12: the groove of each device unit construction is connected together and polysilicon gate all links together, selecting
Second contact hole is formed on the top of the polysilicon gate of the fixed device unit construction, and second contact hole passes through described
Interlayer film；
Step 13: forming front metal layer, the front metal layer is patterned to form grid using lithographic etch process
Pole and source electrode, the corresponding front metal layer of the grid be covered in the corresponding interlayer film surface of second contact hole and
Connected by second contact hole with the polysilicon gate, the corresponding front metal layer of the source electrode be covered on the grid it
The surface of the outer source region, the interlayer film and first contact hole, the corresponding front metal layer of the source electrode and described
There is interval, the source electrode passes through first contact hole connection source region and described between the corresponding front metal layer of grid
Body area.
9. the manufacturing method of groove MOSFET as claimed in claim 8, it is characterised in that: the front metal layer it is graphical
Further include following back process after technique is completed:
The drain region of the first conduction type heavy doping is formed at the back side of the silicon substrate, between the drain region and the body area
The silicon substrate forms drift region；
Metal layer on back is formed at the back side in the drain region and drain electrode is formed by metal layer on back.
10. the manufacturing method of groove MOSFET as claimed in claim 9, it is characterised in that: in the surface shape of the silicon substrate
At the silicon epitaxy layer for having the first conduction type, the body area, the source region and the drift region are formed in the silicon epitaxy layer
In.
11. the manufacturing method of groove MOSFET as claimed in claim 8, it is characterised in that: step 9 include it is following step by step:
Step 9a, deposit forms the second polysilicon layer and is filled up completely the 4th opening, and second polysilicon layer is also formed
The side of the groove at the top of the polycrystalline silicon gate surface and the polysilicon gate, second polysilicon layer also extend
To the surface of the gate oxide outside the 4th opening and the groove；
Step 9b, it carries out polysilicon and goes back to the surface that will be located at the 4th opening and the gate oxide outside the groove quarter
And second polysilicon layer of the groove side surface at the top of the polysilicon gate all removes, described the of Hui Kehou
Two polysilicon layers will be filled up completely and formed first contact hole in the 4th opening, also fold in the polycrystalline silicon gate surface
Added with second polysilicon layer.
12. the manufacturing method of groove MOSFET as claimed in claim 8, it is characterised in that: the material of the hard mask layer
For oxide layer.
13. the manufacturing method of groove MOSFET as claimed in claim 8, it is characterised in that: step 12 includes following substep
It is rapid:
Step 12a, the 5th opening is formed in the forming region of second contact hole using lithographic etch process；
Step 12b, it carries out tungsten deposition and returning for tungsten is engraved in filling tungsten in the 5th opening and forms second contact hole.
14. the manufacturing method of groove MOSFET as claimed in claim 13, it is characterised in that: heavy in the tungsten for carrying out step 12b
Further include the steps that forming barrier layer and adhesive layer before product.
15. the manufacturing method of groove MOSFET as claimed in claim 8, it is characterised in that: groove MOSFET is N-type device,
First conduction type is N-type, and the second conduction type is p-type；Alternatively, groove MOSFET is P-type device, the first conduction type is P
Type, the second conduction type are N-type.
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| CN112530867A (en) * | 2019-09-17 | 2021-03-19 | 华润微电子（重庆）有限公司 | Groove type field effect transistor structure and preparation method thereof |
| CN117238770A (en) * | 2023-11-01 | 2023-12-15 | 深圳市美浦森半导体有限公司 | Trench gate MOSFET device and manufacturing method thereof |
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