CN109087921A - Array substrate and its manufacturing method, display device - Google Patents
Array substrate and its manufacturing method, display device Download PDFInfo
- Publication number
- CN109087921A CN109087921A CN201810934010.0A CN201810934010A CN109087921A CN 109087921 A CN109087921 A CN 109087921A CN 201810934010 A CN201810934010 A CN 201810934010A CN 109087921 A CN109087921 A CN 109087921A
- Authority
- CN
- China
- Prior art keywords
- layer
- electrode
- underlay substrate
- source
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 199
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000009413 insulation Methods 0.000 claims abstract description 29
- 238000002161 passivation Methods 0.000 claims abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims description 113
- 238000000034 method Methods 0.000 claims description 68
- 229910052751 metal Inorganic materials 0.000 claims description 39
- 239000002184 metal Substances 0.000 claims description 39
- 230000008569 process Effects 0.000 claims description 38
- 239000007769 metal material Substances 0.000 claims description 36
- 239000011347 resin Substances 0.000 claims description 35
- 229920005989 resin Polymers 0.000 claims description 35
- 238000000059 patterning Methods 0.000 claims description 27
- 239000012780 transparent material Substances 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 18
- 230000005611 electricity Effects 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000008859 change Effects 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 4
- 239000000463 material Substances 0.000 description 43
- 238000010586 diagram Methods 0.000 description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 21
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 12
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 10
- 238000001755 magnetron sputter deposition Methods 0.000 description 9
- 238000002207 thermal evaporation Methods 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 229910052750 molybdenum Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 239000000956 alloy Substances 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 229910010272 inorganic material Inorganic materials 0.000 description 4
- 239000011147 inorganic material Substances 0.000 description 4
- 238000002834 transmittance Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 235000019504 cigarettes Nutrition 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The present invention discloses a kind of array substrate and its manufacturing method, display device, belongs to field of display technology.The array substrate includes: underlay substrate and the gate figure layer being successively set on underlay substrate, gate insulation layer, active layer, source and drain graph layer, public electrode, auxiliary electrode, passivation layer and pixel electrode, auxiliary electrode and common electrode contact, and orthographic projection of the auxiliary electrode on underlay substrate is located at gate figure layer and source and drain graph layer in the orthographic projection region on underlay substrate.The present invention helps to solve the problems, such as that the aperture opening ratio of array substrate is lower, guarantees the aperture opening ratio of array substrate.The present invention is used for LCD display device.
Description
Technical field
The present invention relates to field of display technology, in particular to a kind of array substrate and its manufacturing method, display device.
Background technique
The advanced super dimension field switch (English: High opening rate Advanced-Super of high aperture
Dimensional Switching；Referred to as: HADS) type display panel is a kind of typical liquid crystal display (English: Liquid
Crystal Display；Referred to as: LCD) display panel has many advantages, such as wide viewing angle, high-resolution and low-power consumption, extensively
Applied to display industry.
HADS type display panel includes and being filled in array substrate and coloured silk to the molding array substrate of box and color membrane substrates
Layer of liquid crystal molecule between ilm substrate.Array substrate includes underlay substrate and the gate figure that is successively set on underlay substrate
Layer, gate insulation layer, active layer, source and drain graph layer, passivation layer and pixel electrode, gate figure layer include grid and connect with grid
Grid line (English: Gate Line), source and drain graph layer include source electrode, drain electrode and connect with source electrode data line (it is English:
Data Line), drain electrode is connect with pixel electrode, and array substrate further includes the Com electrode (public electrode) formed using metal,
Com electrode can be located in gate figure layer, and Com electrode and data line overlap (that is to say Com electrode on underlay substrate completely
Orthographic projection be overlapped with orthographic projection of the data line on underlay substrate).Since Com electrode and data line are completely overlapping, number
According on line signal be easy Com voltage (that is to say the voltage on Com electrode) is had an impact, cause the fluctuation of Com voltage compared with
Greatly, the image quality of HADS type display panel is influenced.It in the related technology, can be by the width of increase Com electrode, to reduce
The resistance of Com electrode, to reduce the fluctuation of Com voltage.
But since Com electrode uses lighttight metal material to be formed, the width for increasing Com electrode will lead to array
The aperture opening ratio of substrate reduces, therefore the aperture opening ratio of array substrate is lower.
Summary of the invention
The present invention provides a kind of array substrate and its manufacturing method, display device, facilitates the opening for solving array substrate
The lower problem of rate.Technical scheme is as follows:
In a first aspect, providing a kind of array substrate, the array substrate includes:
Underlay substrate and the gate figure layer being successively set on the underlay substrate, gate insulation layer, active layer, source and drain figure
Shape layer, public electrode, auxiliary electrode, passivation layer and pixel electrode, the auxiliary electrode and the common electrode contact, and it is described
Orthographic projection of the auxiliary electrode on the underlay substrate is located at the gate figure layer and the source and drain graph layer in the substrate base
In orthographic projection region on plate.
Optionally, the array substrate further include: the tree between the source and drain graph layer and the public electrode is set
Rouge layer.
Optionally, the gate figure layer includes grid and the grid line that connect with the grid, the source and drain graph layer packet
Include source electrode, drain electrode and the data line connecting with the source electrode, orthographic projection position of the auxiliary electrode on the underlay substrate
In the grid line and the data line in the orthographic projection region on the underlay substrate.
Optionally, the public electrode and the auxiliary electrode are formed by same one-time process.
Optionally, the public electrode and the pixel electrode are transparent electrode, and the auxiliary electrode is metal electrode.
Optionally, the public electrode and the pixel electrode are oxidation cigarette tin (English: Indium Tin Oxide；
Referred to as: ITO) electrode.
Second aspect provides a kind of manufacturing method of array substrate, which comprises
Gate figure layer, gate insulation layer, active layer, source and drain graph layer, public electrode, auxiliary electricity are formed on underlay substrate
Pole, passivation layer and pixel electrode, the auxiliary electrode and the common electrode contact, and the auxiliary electrode is in the substrate base
Orthographic projection on plate is located at the gate figure layer and the source and drain graph layer in the orthographic projection region on the underlay substrate.
Optionally, described that gate figure layer, gate insulation layer, active layer, source and drain graph layer, common electrical are formed on underlay substrate
Pole, auxiliary electrode, passivation layer and pixel electrode, comprising:
Gate figure layer, gate insulation layer, active layer and source and drain graph layer, the gate figure layer are sequentially formed on underlay substrate
Including grid and the grid line connecting with the grid, the source and drain graph layer includes source electrode, drain electrode and connects with the source electrode
The data line connect；
Public electrode and auxiliary electrode, the auxiliary electrode are formed on the underlay substrate for being formed with the source and drain graph layer
It is located at the orthographic projection region of the grid line and the data line on the underlay substrate in the orthographic projection on the underlay substrate
It is interior；
Passivation layer and pixel electricity are sequentially formed on the underlay substrate for being formed with the public electrode and the auxiliary electrode
Pole.
It is optionally, described that public electrode and auxiliary electrode are formed on the underlay substrate for being formed with the source and drain graph layer,
Include:
Transparent material layer and metal material layer are sequentially formed on the underlay substrate for being formed with the source and drain graph layer；
The transparent material layer and metal material layer are handled by a patterning processes, obtain the public electrode
With the auxiliary electrode.
Optionally, described to pass through a patterning processes transparent material layer and metal material layer are handled, it obtains
The public electrode and the auxiliary electrode, comprising:
Photoresist layer is formed on the metal material layer；
After the photoresist layer is exposed, is developed using intermediate tone mask version, photoetching offset plate figure, the photoetching are obtained
Glue pattern includes: that the first photoresist area, the second photoresist area and photoresist completely remove area, first photoresist area it is corresponding to
The auxiliary electrode formed, first photoresist area and second photoresist area correspond to the common electrical to be formed
Pole, the photoresist completely remove area and correspond to other regions；
The corresponding metal material floor in area is completely removed to the photoresist and transparent material floor performs etching, is obtained initial auxiliary
Help electrode and the public electrode；
Remove the photoresist in second photoresist area；
The corresponding initial auxiliary electrode in second photoresist area is performed etching, the auxiliary electrode is obtained；
Remove the photoresist in first photoresist area.
Optionally, it is formed before public electrode and auxiliary electrode on the underlay substrate for being formed with the source and drain graph layer,
The method also includes: on the underlay substrate for being formed with the source and drain graph layer form resin layer；
It is described that public electrode and auxiliary electrode are formed on the underlay substrate for being formed with the source and drain graph layer, comprising:
It is formed on the underlay substrate of the resin layer and forms public electrode and auxiliary electrode.
Optionally, the public electrode and the pixel electrode are ITO electrode.
The third aspect provides a kind of display device, and the display device includes first aspect or any of first aspect can
Select array substrate described in mode
Technical solution provided by the invention has the benefit that
Array substrate and its manufacturing method provided by the invention, display device, it is auxiliary since array substrate includes auxiliary electrode
Electrode and common electrode contact are helped, and orthographic projection of the auxiliary electrode on underlay substrate is located at gate figure layer and source and drain graph layer exists
In orthographic projection region on underlay substrate, therefore the setting of auxiliary electrode can reduce the resistance of public electrode, and will not influence
The aperture opening ratio of array substrate.The present invention helps to solve the problems, such as that the aperture opening ratio of array substrate is lower, guarantees opening for array substrate
Mouth rate.
It should be understood that the above general description and the following detailed description are merely exemplary, this can not be limited
Invention.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of front view of array substrate provided in an embodiment of the present invention；
Fig. 2 is the sectional view at the position array substrate A-A ' provided in an embodiment of the present invention；
Fig. 3 is the sectional view at the position array substrate B-B ' provided in an embodiment of the present invention；
Fig. 4 is a kind of method flow diagram of the manufacturing method of array substrate provided in an embodiment of the present invention；
Fig. 5 is that one kind provided in an embodiment of the present invention sequentially forms gate figure layer, gate insulation layer, active on underlay substrate
Schematic diagram after layer and source and drain graph layer；
Fig. 6 be it is provided in an embodiment of the present invention it is a kind of on the underlay substrate for being formed with source and drain graph layer formed resin layer after
Schematic diagram；
Fig. 7 is provided in an embodiment of the present invention a kind of public electrode and auxiliary to be formed on the underlay substrate for be formed with resin layer
Schematic diagram after helping electrode；
Fig. 8 is provided in an embodiment of the present invention a kind of to form public electrode on the underlay substrate for being formed with source and drain graph layer
With the method flow diagram of auxiliary electrode；
Fig. 9 is provided in an embodiment of the present invention a kind of transparent material to be sequentially formed on the underlay substrate for be formed with resin layer
Schematic diagram after layer and metal material layer；
Figure 10 is that one kind provided in an embodiment of the present invention passes through a patterning processes to transparent material layer and metal material layer
The method flow diagram handled；
Figure 11 is a kind of schematic diagram formed after photoresist layer on metal material layer provided in an embodiment of the present invention；
Figure 12 is after a kind of use intermediate tone mask version provided in an embodiment of the present invention is exposed photoresist layer, develops
Schematic diagram；
Figure 13 is that a kind of pair of photoresist provided in an embodiment of the present invention completely removes the corresponding metal material floor in area and transparent
Material layers perform etching after schematic diagram；
Figure 14 is the schematic diagram after a kind of photoresist for removing the second photoresist area provided in an embodiment of the present invention；
Figure 15 is that one kind provided in an embodiment of the present invention performs etching the corresponding initial auxiliary electrode in the second photoresist area
Schematic diagram afterwards.
The drawings herein are incorporated into the specification and forms part of this specification, and shows and meets implementation of the invention
Example, and be used to explain the principle of the present invention together with specification.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention make into
It is described in detail to one step, it is clear that described embodiments are only a part of the embodiments of the present invention, rather than whole implementation
Example.Based on the embodiments of the present invention, obtained by those of ordinary skill in the art without making creative efforts
All other embodiment, shall fall within the protection scope of the present invention.
In the array substrate of HADS type display panel, Com electrode and data line are completely overlapping, and the signal on data line is easy
Com voltage is had an impact, causes Com voltage fluctuation larger, is had an impact to the image quality of HADS type display panel.Currently, big
Size thin-film transistor (English: Thin Film Transistor；Referred to as: TFT) LCD display panel especially television set (English
Text: television；In referred to as: TV), the resistance of Com electrode usually is reduced by increasing the width of Com electrode, to subtract
The fluctuation of small Com voltage, but the width for increasing Com electrode will affect the aperture opening ratio of array substrate, so that it is aobvious to influence HADS type
Show the light transmittance of panel.Scheme provided in an embodiment of the present invention passes through the gate figure layer and source and drain graph layer in array substrate
The top auxiliary electrode that contacts with Com electrode of setting reduces the resistance of Com electrode, can be in the fluctuation of reduction Com voltage
Meanwhile guaranteeing the aperture opening ratio of array substrate, to guarantee the light transmittance of HADS type display panel.Currently, some display product tools
Have the dual-layered liquid crystal screen being stacked, if the light transmittance of bottom liquid crystal display is lower, will lead to display product overall brightness compared with
Low, scheme provided in an embodiment of the present invention can guarantee the light transmittance of display screen, be particularly suitable for having the aobvious of dual-layered liquid crystal screen
Show product.The solution of the present invention please refers to following embodiments.
Fig. 1 is a kind of front view of array substrate provided in an embodiment of the present invention, and Fig. 2 is array substrate shown in FIG. 1
The sectional view at the position A-A ', Fig. 3 is the sectional view at the position B-B ' of array substrate shown in FIG. 1, referring to Fig. 1 to Fig. 3, array base
Plate includes: underlay substrate 00 and the gate figure layer 01 being successively set on underlay substrate 00, gate insulation layer 02, active layer (Fig. 1
Be not shown into Fig. 3), source and drain graph layer 03, public electrode 04, auxiliary electrode 05, passivation layer 06 and pixel electrode 07, auxiliary
Electrode 05 is contacted with public electrode 04, and orthographic projection of the auxiliary electrode 05 on underlay substrate 00 is located at gate figure layer 01 and source and drain
Graph layer 03 is in the orthographic projection region on underlay substrate 00.
In conclusion array substrate provided in an embodiment of the present invention, due to auxiliary electrode and common electrode contact, and assists
Orthographic projection of the electrode on underlay substrate is located at gate figure layer and source and drain graph layer in the orthographic projection region on underlay substrate, auxiliary
The resistance of public electrode can be reduced by helping the setting of electrode, and will not influence the aperture opening ratio of array substrate, therefore, help to solve
The lower problem of the aperture opening ratio of array substrate, guarantees the aperture opening ratio of array substrate.
Optionally, as shown in Figure 1 to Figure 3, gate figure layer 01 includes grid (Fig. 1 is not shown into Fig. 3) and and grid
Pole connection grid line 011, source and drain graph layer 03 include source electrode (Fig. 1 is not shown into Fig. 3), drain electrode (Fig. 1 into Fig. 3 not
Show) and the data line 031 that is connect with source electrode, orthographic projection of the auxiliary electrode 05 on underlay substrate 00 be located at 011 He of grid line
Data line 031 is in the orthographic projection region on underlay substrate 00.Optionally, orthographic projection of the auxiliary electrode 05 on underlay substrate 00
It is overlapped with the orthographic projection of grid line 011 and data line 031 on underlay substrate 00.It should be noted that in practical application, grid,
Gate insulation layer 02, active layer, source electrode and drain electrode constitute a TFT, and via hole is provided on passivation layer 06, and pixel electrode 07 passes through blunt
The via hole changed on layer 06 is connect with the drain electrode in source and drain graph layer 03, and grid controls the opening and closing of TFT, when TFT is opened,
Active layer conducting, the signal on data line 031 flow to pixel electrode 07 by source electrode, active layer and drain electrode, with to pixel electrode
Apply data-signal.
Further, please continue to refer to Fig. 2 and Fig. 3, the array substrate further include: setting source and drain graph layer 03 with it is public
Resin layer 08 between electrode 04.The resin layer 08 can be formed using organic resin material, and the setting of the resin layer 08 can be with
Reduce the overlap capacitance of data line 031 and public electrode 04, the signal on reduction data line 031 is to the voltage of public electrode 04
It influences.
Optionally, public electrode 04 and auxiliary electrode 05 can be formed by same one-time process.
Optionally, underlay substrate 00 can be transparent substrate, and can be is had using glass, quartz or transparent resin etc.
Substrate made of the leaded light and nonmetallic materials of certain robustness.Gate figure layer 01 can be using metal Mo (Chinese: molybdenum), metal
Cu (Chinese: copper), metal Al (Chinese: aluminium) and its alloy material are formed.Gate insulation layer 02 can using silica, silicon nitride or
The inorganic material such as aluminium oxide are formed.Active layer can be using polysilicon (p-si) or indium gallium zinc oxide (English: indium
gallium zinc oxide；Referred to as: IGZO) formed.Source and drain graph layer 03 can using metal Mo, Ni metal, metal Al and
Its alloy material is formed.Public electrode 04 and pixel electrode 07 are transparent electrode, and auxiliary electrode 05 is metal electrode, example
Ground, public electrode 04 and pixel electrode 07 are ITO electrode, and ITO electrode refers to the electrode formed using ITO as material, auxiliary electrode
05 can be formed using metal Mo, Ni metal, metal Al and its alloy material.Passivation layer 06 can use silica, silicon nitride
Or the inorganic material such as aluminium oxide are formed, in some scenes, passivation layer 06 is referred to as insulating layer.
In conclusion array substrate provided in an embodiment of the present invention, due to auxiliary electrode and common electrode contact, and assists
Orthographic projection of the electrode on underlay substrate is located at gate figure layer and source and drain graph layer in the orthographic projection region on underlay substrate, auxiliary
The resistance of public electrode can be reduced by helping the setting of electrode, and will not influence the aperture opening ratio of array substrate, therefore, help to solve
The lower problem of the aperture opening ratio of array substrate, guarantees the aperture opening ratio of array substrate.
Array substrate provided in an embodiment of the present invention can be applied to method hereafter, array substrate in the embodiment of the present invention
Manufacturing method and manufacturing theory may refer to the description in hereafter each embodiment.
The embodiment of the invention provides a kind of manufacturing method of array substrate, the manufacturing method of the array substrate can be used for
Above-mentioned array substrate is manufactured, this method comprises:
Gate figure layer, gate insulation layer, active layer, source and drain graph layer, public electrode, auxiliary electricity are formed on underlay substrate
Pole, passivation layer and pixel electrode, auxiliary electrode and common electrode contact, and orthographic projection of the auxiliary electrode on underlay substrate is located at
Gate figure layer and source and drain graph layer are in the orthographic projection region on underlay substrate.
In conclusion the manufacturing method of array substrate provided in an embodiment of the present invention, due to auxiliary electrode and public electrode
Contact, and orthographic projection of the auxiliary electrode on underlay substrate is located at the positive throwing of gate figure layer and source and drain graph layer on underlay substrate
In the domain of shadow zone, the setting of auxiliary electrode can reduce the resistance of public electrode, and will not influence the aperture opening ratio of array substrate, because
This, helps to solve the problems, such as that the aperture opening ratio of array substrate is lower, guarantees the aperture opening ratio of array substrate.
Optionally, on underlay substrate formed gate figure layer, gate insulation layer, active layer, source and drain graph layer, public electrode,
Auxiliary electrode, passivation layer and pixel electrode, comprising:
Gate figure layer, gate insulation layer, active layer and source and drain graph layer are sequentially formed on underlay substrate, gate figure layer includes
Grid and the grid line connecting with grid, source and drain graph layer include source electrode, drain electrode and the data line connecting with source electrode；
Public electrode and auxiliary electrode are formed on the underlay substrate for being formed with source and drain graph layer, auxiliary electrode is in substrate base
Orthographic projection on plate is located at grid line and data line in the orthographic projection region on underlay substrate；
Passivation layer and pixel electrode are sequentially formed on the underlay substrate for being formed with public electrode and auxiliary electrode.
Optionally, public electrode and auxiliary electrode are formed on the underlay substrate for being formed with source and drain graph layer, comprising:
Transparent material layer and metal material layer are sequentially formed on the underlay substrate for being formed with source and drain graph layer；
Transparent material layer and metal material layer are handled by a patterning processes, obtain public electrode and auxiliary electricity
Pole.
Optionally, transparent material layer and metal material layer are handled by a patterning processes, obtains public electrode
And auxiliary electrode, comprising:
Photoresist layer is formed on metal material layer；
After being exposed, develop to photoresist layer using intermediate tone mask version, photoetching offset plate figure, photoetching offset plate figure packet are obtained
Include: the first photoresist area, the second photoresist area and photoresist completely remove area, and the first photoresist area corresponds to auxiliary electricity to be formed
Pole, the first photoresist area and the second photoresist area correspond to public electrode to be formed, and photoresist completely removes area and corresponds to other areas
Domain；
The corresponding metal material floor in area is completely removed to photoresist and transparent material floor performs etching, obtains initially assisting electricity
Pole and public electrode；
Remove the photoresist in the second photoresist area；
The corresponding initial auxiliary electrode in second photoresist area is performed etching, auxiliary electrode is obtained；
Remove the photoresist in the first photoresist area.
Optionally, it is formed before public electrode and auxiliary electrode on the underlay substrate for being formed with source and drain graph layer, the party
Method further include: form resin layer on the underlay substrate for being formed with source and drain graph layer；
Public electrode and auxiliary electrode are formed on the underlay substrate for being formed with source and drain graph layer, comprising: be formed with tree
Public electrode and auxiliary electrode are formed on the underlay substrate of rouge layer.
Optionally, public electrode and pixel electrode are ITO electrode.
All the above alternatives can form alternative embodiment of the invention using any combination, herein no longer
It repeats one by one.
Referring to FIG. 4, it illustrates a kind of method flows of the manufacturing method of array substrate provided in an embodiment of the present invention
Figure, the manufacturing method of the array substrate can be used for manufacturing above-mentioned array substrate, referring to fig. 4, the manufacturing method of the array substrate
Include:
Step 401 sequentially forms gate figure layer, gate insulation layer, active layer and source and drain graph layer on underlay substrate.
Referring to FIG. 5, it illustrates one kind provided in an embodiment of the present invention to sequentially form gate figure on underlay substrate 00
Schematic diagram after layer (being not shown in Fig. 5), gate insulation layer 02, active layer (being not shown in Fig. 5) and source and drain graph layer 03.Wherein,
Gate figure layer includes grid (being not shown in Fig. 5) and the grid line connecting with grid (being not shown in Fig. 5), and source and drain graph layer 03 wraps
Include source electrode (being not shown in Fig. 5), drain electrode (being not shown in Fig. 5) and the data line 031 connecting with source electrode.The embodiment of the present invention
In, it may include following that gate figure layer, gate insulation layer 02, active layer and source and drain graph layer 03 are sequentially formed on underlay substrate 00
Four steps:
Step 1: forming gate figure layer on underlay substrate 00.Wherein, gate figure layer can using metal Mo, Ni metal,
Metal Al and its alloy material are formed.The present embodiment is illustrated for forming gate figure layer using metal Mo.
Illustratively, magnetron sputtering, thermal evaporation or plasma enhanced chemical vapor deposition method (Plasma can be used
Enhanced Chemical Vapor Deposition；One layer of gold is deposited the methods of referred to as: PECVD) on underlay substrate 00
Belong to Mo, obtains metal Mo material layers, then metal Mo material layers are handled to obtain gate figure layer by a patterning processes.
Wherein, a patterning processes include: photoresist (English: Photoresist；Referred to as: PR) coating, exposure, development, etching and light
Therefore metal Mo material layers, are handled to obtain gate figure layer to may include: in gold by photoresist removing by a patterning processes
Belong to and coat a layer photoresist in Mo material layers, photoresist is exposed using mask plate, photoresist is made to form complete exposure region
And non-exposed area, the photoresist after exposure is handled by developing process later, keeps the photoresist of complete exposure region complete
The photoresist of full removal, non-exposed area all retains, and performs etching to the corresponding region of exposure region complete in metal Mo material layers,
The photoresist of non-exposed area is removed later, and the corresponding region in non-exposed area forms gate figure layer in metal Mo material layers.It needs
Bright, the embodiment of the present invention is illustrated for forming gate figure layer using positive photoresist, in practical application, also
Gate figure layer can be formed using negative photoresist, it is not limited in the embodiment of the present invention.
Step 2: forming gate insulation layer 02 on the underlay substrate 00 for be formed with gate figure layer.Wherein, gate insulation layer 02 can
To be formed using inorganic material such as silica, silicon nitride or aluminium oxide, the present embodiment is to form gate insulation layer 02 using silica
For be illustrated.
Illustratively, gate figure layer can be formed with using the methods of coating, magnetron sputtering, thermal evaporation or PECVD
One layer of silica is deposited on underlay substrate 00 and obtains silica material layers, using silica material layers as gate insulation layer 02.It is practical
It,, can be by a patterning processes to oxygen after forming silica material layers when gate insulation layer 02 includes figure in
SiClx material layers are handled to obtain gate insulation layer 02.The process that silica material layers are handled by a patterning processes
Can be with reference to the process handled above by a patterning processes metal Mo material layers, the present embodiment is no longer superfluous herein
It states.
Step 3: forming active layer on the underlay substrate 00 for being formed with gate insulation layer 02.Wherein, active layer can use
IGZO or p-si are formed.
Illustratively, gate insulation layer 02 can be formed with using the methods of coating, magnetron sputtering, thermal evaporation or PECVD
Underlay substrate 00 on one layer of IGZO of deposition obtain IGZO material layers, then IGZO material layers are carried out by patterning processes
Processing obtains active layer.Alternatively, gate insulation can be formed with using the methods of coating, magnetron sputtering, thermal evaporation or PECVD
One layer of amorphous silicon (a-si) of deposition obtains a-si material layers on the underlay substrate 00 of layer 02, carries out high annealing to a-si material layers
So that a-si is converted into p-si and obtain p-si material layers, p-si material layers is handled to obtain by a patterning processes active
Layer.Wherein, by a patterning processes to IGZO material layers or p-si material layers be treated journey can with reference to above by
The process that patterning processes handle metal Mo material layers, details are not described herein for the present embodiment.
Step 4: forming source and drain graph layer 03 on the underlay substrate 00 for being formed with active layer.Wherein, source and drain graph layer 03
It can be formed using metal Mo, Ni metal, metal Al and its alloy material, the forming material and gate figure layer of source and drain graph layer 03
Forming material can be identical or different.The present embodiment is illustrated for forming source and drain graph layer 03 using Ni metal.
It illustratively, can be using the methods of magnetron sputtering, thermal evaporation or PECVD in the underlay substrate for being formed with active layer
On 00 deposit one layer of Ni metal, obtain Ni metal material layers, then by a patterning processes to Ni metal material layers at
Reason obtains source and drain graph layer 03.By a patterning processes to Ni metal material layers be treated journey can with reference to above by
The process that patterning processes handle metal Mo material layers, details are not described herein for the present embodiment.
Step 402 forms resin layer on the underlay substrate for being formed with source and drain graph layer.
Referring to FIG. 6, it illustrates provided in an embodiment of the present invention a kind of in the substrate base for being formed with source and drain graph layer 03
The schematic diagram after resin layer 08 is formed on plate 00.The resin layer 08 can be formed using organic resin material, the resin layer 08
The overlap capacitance that can reduce data line 031 with the public electrode 04 being subsequently formed is set, the signal pair on data line 031 is reduced
The influence of the voltage of public electrode 04.
It illustratively, can be using the methods of magnetron sputtering, thermal evaporation or PECVD in the lining for being formed with source and drain graph layer 03
One layer of resin material is deposited on substrate 00 obtains resin layer 08.In practical application, when resin layer 08 includes figure, depositing
After resin material, resin material can also be handled to obtain resin layer 08 by a patterning processes.
Step 403 forms public electrode and auxiliary electrode, auxiliary electrode and public affairs on the underlay substrate for be formed with resin layer
Common electrode contact, and orthographic projection of the auxiliary electrode on underlay substrate is located at gate figure layer and source and drain graph layer on underlay substrate
Orthographic projection region in.
Referring to FIG. 7, it illustrates provided in an embodiment of the present invention a kind of in the underlay substrate 00 for being formed with resin layer 08
The upper schematic diagram formed after public electrode 04 and auxiliary electrode 05, auxiliary electrode 05 is contacted with public electrode 04, and auxiliary electrode
05 is located at gate figure layer (being not shown in Fig. 7) and source and drain graph layer 03 on underlay substrate 00 in the orthographic projection on underlay substrate 00
Orthographic projection region in.In embodiments of the present invention, gate figure layer includes grid (being not shown in Fig. 7) and connect with grid
Grid line (is not shown) in Fig. 7, and source and drain graph layer 03 includes source electrode (being not shown in Fig. 7), drain electrode (being not shown in Fig. 7) and and source
The data line 031 of pole connection, orthographic projection of the auxiliary electrode 05 on underlay substrate 00 are located at gate figure layer and source and drain graph layer 03
Be specifically as follows in the orthographic projection region on underlay substrate 00: orthographic projection of the auxiliary electrode 05 on underlay substrate 00 is located at grid
Line and data line 031 are in the orthographic projection region of underlay substrate 00.Wherein, public electrode 04 can be transparent electrode, specific
It can be ITO electrode, auxiliary electrode 05 can be formed using metal Mo, Ni metal, metal Al and its alloy material.
Referring to FIG. 8, it illustrates provided in an embodiment of the present invention a kind of in the underlay substrate for being formed with source and drain graph layer
The upper method flow diagram for forming public electrode and auxiliary electrode, referring to Fig. 8, this method comprises:
Sub-step 4031 sequentially forms transparent material layer and metal material layer on the underlay substrate for be formed with resin layer.
Referring to FIG. 9, it illustrates provided in an embodiment of the present invention a kind of in the underlay substrate 00 for being formed with resin layer 08
On sequentially form the schematic diagram after transparent material layer X and metal material layer Y.Wherein, transparent material layer X can be ITO material layers,
Metal material layer Y can be metal Mo, Ni metal or metal Al material layers.Illustratively, can using magnetron sputtering, thermal evaporation or
The methods of person PECVD is sequentially depositing ITO and metal Al on the underlay substrate 00 for being formed with resin layer 08, obtains ITO material layers
With metal Al material layers, using ITO material layers as transparent material layer X, using metal Al material layers as metal material layer Y.
Sub-step 4032 is handled transparent material layer and metal material layer by a patterning processes, is obtained public
Electrode and auxiliary electrode.
Referring to FIG. 10, it illustrates one kind provided in an embodiment of the present invention by a patterning processes to transparent material layer
The method flow diagram handled with metal material layer, referring to Figure 10, this method comprises:
Sub-step 40321 forms photoresist layer on metal material layer.
Figure 11 is please referred to, it illustrates one kind provided in an embodiment of the present invention, and photoresist layer R is formed on metal material layer Y
Schematic diagram afterwards, photoresist layer R can not do this for positive photoresist layer or negative photo glue-line, the embodiment of the present invention
It limits, the embodiment of the present invention is illustrated so that photoresist layer R is positive photoresist layer as an example, illustratively, can be in metal material
One layer is coated on matter layer Y, and there is certain thickness positive photoresist to obtain photoresist layer R.
Sub-step 40322 after being exposed, developed to photoresist layer using intermediate tone mask version, obtains photoetching offset plate figure,
Photoetching offset plate figure includes: that the first photoresist area, the second photoresist area and photoresist completely remove area, the first photoresist area it is corresponding to
The auxiliary electrode of formation, the first photoresist area and the second photoresist area correspond to public electrode to be formed, and photoresist completely removes
Area corresponds to other regions.
Figure 12 is please referred to, it illustrates provided in an embodiment of the present invention a kind of using intermediate tone mask version (English: Half
Tone Mask；Schematic diagram after referred to as: HTM) photoresist layer R is exposed, is developed carries out photoresist layer R using HTM
Photoetching offset plate figure R1 is obtained after exposure, development, photoetching offset plate figure R1 includes: the first photoresist area R11, the second photoresist area R12
Area R13 is completely removed with photoresist, the first photoresist area R11 corresponds to auxiliary electrode to be formed, the first photoresist area R11 and
Two photoresist area R12 correspond to public electrode to be formed, and photoresist completely removes area R13 and corresponds to other regions.
Illustratively, photoresist layer R can be exposed using the HTM with respective graphical, so that photoresist layer R is formed
Complete exposure region, Partial exposure area and non-exposed area, carry out development treatment to the photoresist layer R after exposure later, and removal is complete
The photoresist of exposure region retains the photoresist of part exposure region and non-exposed area, obtains photoetching offset plate figure R1 as shown in figure 12.
Sub-step 40323 completely removes the corresponding metal material floor in area to photoresist and transparent material floor performs etching, and obtains
To initial auxiliary electrode and public electrode.
Figure 13 is please referred to, to completely remove area R13 corresponding it illustrates a kind of pair of photoresist provided in an embodiment of the present invention
Metal material layer Y and transparent material layer X perform etching after schematic diagram.R13 corresponding metal material in area is completely removed to photoresist
After matter layer Y and transparent material layer X is performed etching, initial auxiliary electrode Y1 and public electrode 04 are obtained.It is alternatively possible to successively
R13 corresponding metal material floor Y in area is completely removed to photoresist and photoresist completely removes the corresponding transparent material floor X of area R13
It performs etching respectively, the embodiment of the present invention is not construed as limiting this.
Sub-step 40324, the photoresist for removing the second photoresist area.
Figure 14 is please referred to, it illustrates a kind of photoresists for removing the second photoresist area R12 provided in an embodiment of the present invention
Schematic diagram afterwards.Wherein it is possible to remove the photoresist of the second photoresist area R12 using techniques such as development, ashing or removings.
Sub-step 40325 performs etching the corresponding initial auxiliary electrode in the second photoresist area, obtains auxiliary electrode.
Figure 15 is please referred to, it is corresponding to the second photoresist area R12 initial that it illustrates one kind provided in an embodiment of the present invention
Auxiliary electrode Y1 perform etching after schematic diagram, initial auxiliary electrode Y1 corresponding to the second photoresist area R12 perform etching it
After obtain auxiliary electrode 05.It is alternatively possible to using wet-etching technology initial auxiliary electricity corresponding to the second photoresist area R12
Pole Y1 is performed etching.
Sub-step 40326, the photoresist for removing the first photoresist area.
Schematic diagram after removing the photoresist of the first photoresist area R11 can refer to Fig. 7.
It should be noted that the embodiment of the present invention is to form public electrode 04 and auxiliary electrode 05 by same one-time process
For be illustrated, in practical application, public electrode 04 and auxiliary electrode 05 can also can be formed by different processes, this hair
Bright embodiment does not limit this.
Step 404 sequentially forms passivation layer and pixel electricity on the underlay substrate for being formed with public electrode and auxiliary electrode
Pole.
Passivation layer 06 and pixel electricity are sequentially formed on the underlay substrate 00 for being formed with public electrode 04 and auxiliary electrode 05
Schematic diagram behind pole 07 can refer to Fig. 3.In the embodiment of the present invention, in the substrate for being formed with public electrode 04 and auxiliary electrode 05
It may include following two step that passivation layer 06 and pixel electrode 07 are sequentially formed on substrate 00:
Step 1: forming passivation layer 06 on the underlay substrate 00 for being formed with public electrode 04 and auxiliary electrode 05.Wherein,
Passivation layer 06 can be formed using inorganic material such as silica, silicon nitride or aluminium oxide.
Illustratively, public electrode 04 can be formed with using the methods of coating, magnetron sputtering, thermal evaporation or PECVD
Silicon nitride material layer is obtained with one layer of silicon nitride is deposited on the underlay substrate 00 of auxiliary electrode 05, using silicon nitride material layer as blunt
Change layer 06.
Step 2: forming pixel electrode 07 on the underlay substrate 00 for be formed with passivation layer 06.Wherein, pixel electrode 07 can
Think transparent electrode, is specifically as follows ITO electrode.
Illustratively, passivation layer 06 can be formed with using the methods of coating, magnetron sputtering, thermal evaporation or PECVD
One layer of ITO is deposited on underlay substrate 00 and obtains ITO material layers, and then ITO material layers are handled by a patterning processes
Obtain pixel electrode 07.It can be with reference to above by primary by the process that a patterning processes handle ITO material layers
The process that patterning processes handle metal Mo material layers, details are not described herein for the present embodiment.
It should be noted that passivation layer 06 and resin layer 08 have been respectively formed on via hole, and on passivation layer 06 in practical application
Via hole be connected to the via hole on resin layer 08, pixel electrode 07 passes sequentially through on via hole and resin layer 08 on passivation layer 06
Via hole, the drain contact with source and drain graph layer 03.Therefore, after forming passivation layer 06, a patterning processes pair can be passed through
Passivation layer 06 and resin layer 08 are handled, to form via hole on passivation layer 06 and resin layer 08.
In conclusion the manufacturing method of array substrate provided in an embodiment of the present invention, due to auxiliary electrode and public electrode
Contact, and orthographic projection of the auxiliary electrode on underlay substrate is located at the positive throwing of gate figure layer and source and drain graph layer on underlay substrate
In the domain of shadow zone, the setting of auxiliary electrode can reduce the resistance of public electrode, and will not influence the aperture opening ratio of array substrate, because
This, helps to solve the problems, such as that the aperture opening ratio of array substrate is lower, guarantees the aperture opening ratio of array substrate.
The embodiment of the invention also provides a kind of display device, which includes array base provided by the above embodiment
Plate, the display device can be LCD display device, can be with are as follows: liquid crystal display panel, Electronic Paper, mobile phone, tablet computer, television set,
Any products or components having a display function such as display, laptop, Digital Frame or navigator.
Those of ordinary skill in the art will appreciate that realizing that all or part of the steps of above-described embodiment can pass through hardware
It completes, relevant hardware can also be instructed to complete by program, the program can store in a kind of computer-readable
In storage medium, storage medium mentioned above can be read-only memory, disk or CD etc..
The foregoing is merely alternative embodiments of the invention, are not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of array substrate, which is characterized in that the array substrate includes:
Underlay substrate and the gate figure layer being successively set on the underlay substrate, gate insulation layer, active layer, source and drain figure
Layer, public electrode, auxiliary electrode, passivation layer and pixel electrode, the auxiliary electrode and the common electrode contact, and it is described auxiliary
Orthographic projection of the electrode on the underlay substrate is helped to be located at the gate figure layer and the source and drain graph layer in the underlay substrate
On orthographic projection region in.
2. array substrate according to claim 1, which is characterized in that the array substrate further include: be arranged in the source
Resin layer between leakage graphic layer and the public electrode.
3. array substrate according to claim 1, which is characterized in that the gate figure layer include grid and with the grid
The grid line of pole connection, the source and drain graph layer include source electrode, drain electrode and the data line connecting with the source electrode, the auxiliary electricity
Pole is located at the forward projection region of the grid line and the data line on the underlay substrate in the orthographic projection on the underlay substrate
In domain.
4. array substrate according to any one of claims 1 to 3, which is characterized in that the public electrode and pixel electricity
Pole is transparent electrode, and the auxiliary electrode is metal electrode.
5. a kind of manufacturing method of array substrate, which is characterized in that the described method includes:
Gate figure layer, gate insulation layer, active layer, source and drain graph layer, public electrode, auxiliary electrode, blunt is formed on underlay substrate
Change layer and pixel electrode, the auxiliary electrode and the common electrode contact, and the auxiliary electrode is on the underlay substrate
Orthographic projection be located at the gate figure layer and the source and drain graph layer in the orthographic projection region on the underlay substrate.
6. according to the method described in claim 5, it is characterized in that, described form gate figure layer, gate insulation on underlay substrate
Layer, active layer, source and drain graph layer, public electrode, auxiliary electrode, passivation layer and pixel electrode, comprising:
Gate figure layer, gate insulation layer, active layer and source and drain graph layer are sequentially formed on underlay substrate, the gate figure layer includes
Grid and the grid line connecting with the grid, the source and drain graph layer include source electrode, drain electrode and connect with the source electrode
Data line；
Public electrode and auxiliary electrode are formed on the underlay substrate for being formed with the source and drain graph layer, the auxiliary electrode is in institute
It states the orthographic projection on underlay substrate and is located at the grid line and the data line in the orthographic projection region on the underlay substrate；
Passivation layer and pixel electrode are sequentially formed on the underlay substrate for being formed with the public electrode and the auxiliary electrode.
7. according to the method described in claim 6, it is characterized in that, described in the underlay substrate for being formed with the source and drain graph layer
Upper formation public electrode and auxiliary electrode, comprising:
Transparent material layer and metal material layer are sequentially formed on the underlay substrate for being formed with the source and drain graph layer；
The transparent material layer and metal material layer are handled by a patterning processes, obtain the public electrode and institute
State auxiliary electrode.
8. the method according to the description of claim 7 is characterized in that described pass through a patterning processes to the transparent material layer
It is handled with metal material layer, obtains the public electrode and the auxiliary electrode, comprising:
Photoresist layer is formed on the metal material layer；
After the photoresist layer is exposed, is developed using intermediate tone mask version, photoetching offset plate figure, the photoresist figure are obtained
Shape includes: that the first photoresist area, the second photoresist area and photoresist completely remove area, and first photoresist area corresponds to be formed
The auxiliary electrode, first photoresist area and second photoresist area correspond to the public electrode to be formed, institute
It states photoresist and completely removes area and correspond to other regions；
The corresponding metal material floor in area is completely removed to the photoresist and transparent material floor performs etching, obtains initially assisting electricity
Pole and the public electrode；
Remove the photoresist in second photoresist area；
The corresponding initial auxiliary electrode in second photoresist area is performed etching, the auxiliary electrode is obtained；
Remove the photoresist in first photoresist area.
9. according to any method of claim 6 to 8, which is characterized in that
It is formed before public electrode and auxiliary electrode on the underlay substrate for being formed with the source and drain graph layer, the method is also wrapped
It includes: forming resin layer on the underlay substrate for being formed with the source and drain graph layer；
It is described that public electrode and auxiliary electrode are formed on the underlay substrate for being formed with the source and drain graph layer, comprising: to be formed
Have and forms public electrode and auxiliary electrode on the underlay substrate of the resin layer.
10. a kind of display device, which is characterized in that the display device includes any array base of Claims 1-4
Plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810934010.0A CN109087921A (en) | 2018-08-15 | 2018-08-15 | Array substrate and its manufacturing method, display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810934010.0A CN109087921A (en) | 2018-08-15 | 2018-08-15 | Array substrate and its manufacturing method, display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109087921A true CN109087921A (en) | 2018-12-25 |
Family
ID=64793499
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810934010.0A Pending CN109087921A (en) | 2018-08-15 | 2018-08-15 | Array substrate and its manufacturing method, display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109087921A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020113599A1 (en) * | 2018-12-03 | 2020-06-11 | 惠科股份有限公司 | Active switch and manufacturing method thereof, and display device |
| WO2022178836A1 (en) * | 2021-02-26 | 2022-09-01 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, display panel and display device |
| CN115236907A (en) * | 2022-07-26 | 2022-10-25 | 京东方科技集团股份有限公司 | Array substrate, display panel, display device and manufacturing method |
| CN115373189A (en) * | 2022-07-29 | 2022-11-22 | 惠科股份有限公司 | Array substrate, display device and driving circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104951132A (en) * | 2015-06-02 | 2015-09-30 | 业成光电（深圳）有限公司 | Touch display panel structure |
| US20170010497A1 (en) * | 2015-07-06 | 2017-01-12 | Samsung Display Co., Ltd | Liquid crystal display and method for manufacturing same |
| US20180059449A1 (en) * | 2016-08-23 | 2018-03-01 | Samsung Display Co., Ltd. | Display device |
-
2018
- 2018-08-15 CN CN201810934010.0A patent/CN109087921A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104951132A (en) * | 2015-06-02 | 2015-09-30 | 业成光电（深圳）有限公司 | Touch display panel structure |
| US20170010497A1 (en) * | 2015-07-06 | 2017-01-12 | Samsung Display Co., Ltd | Liquid crystal display and method for manufacturing same |
| US20180059449A1 (en) * | 2016-08-23 | 2018-03-01 | Samsung Display Co., Ltd. | Display device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020113599A1 (en) * | 2018-12-03 | 2020-06-11 | 惠科股份有限公司 | Active switch and manufacturing method thereof, and display device |
| WO2022178836A1 (en) * | 2021-02-26 | 2022-09-01 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, display panel and display device |
| CN115280231A (en) * | 2021-02-26 | 2022-11-01 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof, display panel and display device |
| CN115280231B (en) * | 2021-02-26 | 2023-11-03 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof, display panel and display device |
| CN115236907A (en) * | 2022-07-26 | 2022-10-25 | 京东方科技集团股份有限公司 | Array substrate, display panel, display device and manufacturing method |
| CN115236907B (en) * | 2022-07-26 | 2023-11-03 | 京东方科技集团股份有限公司 | Array substrate, display panel, display device and manufacturing method |
| CN115373189A (en) * | 2022-07-29 | 2022-11-22 | 惠科股份有限公司 | Array substrate, display device and driving circuit |
| CN115373189B (en) * | 2022-07-29 | 2023-07-18 | 惠科股份有限公司 | Array substrate, display device and driving circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8735888B2 (en) | TFT-LCD array substrate and manufacturing method thereof | |
| US9698178B2 (en) | Array substrate, method for manufacturing the same, and display apparatus | |
| CN105845737B (en) | Thin film transistor (TFT) and its manufacturing method, array substrate, display device | |
| CN109087921A (en) | Array substrate and its manufacturing method, display device | |
| US8895334B2 (en) | Thin film transistor array substrate and method for manufacturing the same and electronic device | |
| CN106653774B (en) | Array substrate and manufacturing method thereof, mask and display device | |
| US20180292696A1 (en) | Array substrate, manufacturing method thereof, display panel and display device | |
| WO2014015453A1 (en) | Thin film transistor, array substrate and manufacturing method thereof, and display device | |
| WO2013155830A1 (en) | Method for manufacturing array substrate, array substrate, and display device | |
| JP2010191421A (en) | Tft-lcd array substrate and manufacturing method thereof | |
| KR100698062B1 (en) | Liquid Crystal Display Device And Method For Fabricating The Same | |
| WO2014187113A1 (en) | Array substrate, preparation method, and display apparatus | |
| WO2014166181A1 (en) | Thin-film transistor and manufacturing method thereof, array base plate and display apparatus | |
| US9791755B2 (en) | Color filter-on-array substrate, display device, and method for manufacturing the color filter-on-array substrate | |
| WO2017140058A1 (en) | Array substrate, manufacturing method therefor, display panel and display apparatus | |
| WO2014153958A1 (en) | Array substrate, method for manufacturing array substrate and display device | |
| WO2015096312A1 (en) | Array substrate and manufacturing method thereof, and display device | |
| EP2757589A2 (en) | Methods for fabricating a thin film transistor and an array substrate | |
| CN104241296B (en) | A kind of array base palte and preparation method thereof and display device | |
| WO2020093458A1 (en) | Array substrate and preparation method therefor, liquid crystal display panel, and display device | |
| CN106353944A (en) | Array base plate, manufacturing method of array base plate, display panel and display device | |
| CN104779203B (en) | A kind of array base palte and its manufacture method, display device | |
| WO2013159520A1 (en) | Thin-film transistor array substrate, manufacturing method therefor and liquid crystal display | |
| TWI396916B (en) | Method of forming thin film transistor array substrate | |
| WO2012017626A1 (en) | Thin-film transistor substrate, method for producing same, and liquid crystal display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20181225 |
|
| RJ01 | Rejection of invention patent application after publication |