CN109065619A - A kind of IGBT device with low noise low switching losses characteristic - Google Patents
A kind of IGBT device with low noise low switching losses characteristic Download PDFInfo
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
The invention belongs to power semiconductor device technology fields, more particularly to a kind of IGBT device with low noise low switching losses characteristic.15 structure of P+ type JFET source region 13, the gate regions N+ type JFET 14 and P-type JFET channel region that the present invention passes through the introducing low noise in the area discrete floating pbody 8 of traditional IGBT device, enhancing conductance modulation in hole is stored in device forward conduction with this, it quickly releases when shutdown hole, reduces the turn-off time；Semi-surrounding structure is formed in the gate regions JFET 14 by dielectric layer 10 simultaneously, reduce the Miller capacitance Cgc of device, influence of the parasitic NPN unlatching to effective grid voltage in JFET structure is inhibited, has reached under conditions of guaranteeing low noise, has reduced switch time and switching loss.
Description
Technical field
The invention belongs to power semiconductor device technology fields, and in particular to one kind has low noise low switching losses characteristic
IGBT device.
Background technique
With rail traffic, the fast development of smart grid, field of wind power generation, insulated gate bipolar transistor
(Insulated Gate Bipolar Transistor, IGBT) is by feat of grid control is simple, input impedance is high, electric current is close
The advantages such as degree is big, saturation voltage drop is low, it has also become one of mainstream device for power switching in middle high power range, while will also continue
Develop towards directions such as high-voltage great-current, low-power consumption, elevated operating temperature and high reliability.
High pressure IGBT generallys use planar gate structure, for high-speed rail, power transmission etc. to the very high environment of reliability requirement,
But for plane grid-type IGBT because of parasitism JFET resistance, compared to groove gate type structure, saturation voltage drop is big, increases on-state loss；
Groove gate type IGBT (Trench IGBT) cellular spacing is small simultaneously, and current density is big, it has also become reduces the common knot of conduction loss
Structure.And TIGBT is in slot grid bottom that there are peak electric fields, limits the raising of blocking voltage, while its short circuit current is larger, resists short
Road ability is weaker；Peak electric field can be reduced by introducing P-floating shielded layer in slot grid bottom, but can introduced additional
JFET resistance and increase conduction loss；Clamp diode is introduced simultaneously in the base area P between slot grid, Eoff- can be improved simultaneously
Vcesat optimizes trade-off relation and strengthens shorted devices ability to bear, but existing scheme focuses mostly in 1200V voltage class.Pass through
Device current density can be reduced using sipes grid spacing or the region FP (Floating-Pbody), hence it is evident that improve the short circuit of TIGBT
Ability to bear, but the groove gate type IGBT (FP-TIGBT) of FP structure is because of negative grid capacity effect, so that FP is tied when device is opened
The voltage change generated in structure generates displacement current in grid by Miller capacitance Cgc, reduces the grid control ability of IGBT,
EMI noise problem can be brought simultaneously.
It, can by Fin p-Body, Shield trench and Side-gate structure in 1200-1700V voltage class
Improve EMI problem, but precision of manufacturing process is required stringent；For being greater than IGBT, ABB and the Hitachi of 2500V voltage class
Equal overseas enterprises have been proposed 3300V-TIGBT product, are more than the area discrete floating P of slot grid depth by built-in junction depth
(Separate Floating Pbody) plays the role of reducing slot grid bottom peak electric field and enhances conductance modulation, improve
Eoff-Vcesat trade-off relation, but the area discrete floating FP will affect device pressure resistance and on state characteristic；And discrete FP is passed through into fixation
Resistance is connected to the ground, and provides partial holes access, conduction loss is easily caused to increase.
Summary of the invention
In view of described above, there are the causes of the area P potential change for the slot grid IGBT device in the existing area discrete floating P by the present invention
Reduce pressure device, the problems such as switching loss is larger, providing a kind of has low noise low switching losses IGBT device.By
Groove is formed in discrete FP, built-in JFET structure forms holoe carrier control structure in groove；JFET be low-noise device and
It is built in the discrete area FP, is equivalent to variable resistance, it is reliable can to improve device pressure resistance while guaranteeing to solve the problems, such as EMI
Property；Miller capacitance is reduced simultaneously, reduces switching loss.
To achieve the goals above, the invention provides the following technical scheme:
One kind having low noise low switching losses IGBT device, and structure cell includes the metal stacked gradually from bottom to up
Collector 7, P+ collecting zone 6, N-type buffer layer 5, the drift region N- 4 and metal emitting 11；Among the top layer of the drift region N- 4
Region is equipped with the discrete area P+ floating pbody 8, and the two sides in the discrete area P+ floating pbody 8 are respectively equipped with the base area P+ 2, the P+
The top layer of base area 2 is equipped with N+ emitter region 1；The base area P+ 2 and N+ emitter region 1 pass through metal emitting 11 and discrete P+ floating
The area pbody 8 is in contact；Gate structure, institute are equipped between the base area P+ 2 and N+ emitter region 1 and the discrete area P+ floating pbody 8
Stating gate structure includes gate electrode 9 and gate dielectric layer 3, and gate dielectric layer 3 extends into shape in the drift region N- 4 along device vertical direction
At groove, the setting of gate electrode 9 is in the trench；The side and the base area P+ 2 of the gate dielectric layer 3, N+ emitter region 1 and N- are drifted about
Area 4 contacts, it is characterised in that: the other side of the gate dielectric layer 3 is separated by with the discrete area P+ floating pbody 8 by the drift region N- 4
From；The gate regions N+ type JFET 14, P+ type JFET source region 13 and P-type JFET ditch are additionally provided in the discrete area P+ floating pbody 8
The JFET structure that road area 15 is formed；The intermediate region of discrete 8 top layer of the area P+ floating pbody is arranged in P-type JFET channel region 15,
The top layer of P-type JFET channel region 15 is arranged in the P+ type JFET source region 13, and the gate regions N+ type JFET 14 are symmetricly set on
It the two sides of P+ type JFET source region 13 and is in contact with gate electrode 9 by connecting bridge 12；The gate regions the N+ type JFET 14 and discrete P
It is isolated between the area+floating pbody 8 by dielectric layer 10；The P+ type JFET source region 13 passes through metal emitting 11 and the base area P+ 2
It is in contact with N+ emitter region 1；Between the metal emitting 11 and the drift region N- 4 and P-type JFET channel region 15 and connecting bridge
It is isolated respectively by dielectric layer 10 between the drift region 12 and N- 4.
Further, the junction depth in the discrete area P+ floating pbody 8 is greater than the depth of gate structure in the present invention.
Further, JFET generates consumption under the conditions of the width of P-type JFET channel region 15 is less than device on-state in the present invention
The width in area to the greatest extent.
Further, 10 thickness of dielectric layer in the present invention between the gate regions N+ type JFET 14 and the discrete area P+ floating pbody 8
Width realizes the semi-surrounding structure to the gate regions JFET 14, eliminates the PN between the gate regions JFET 14 and the discrete area P+ floating pbody 8
Junction capacity.
Further, dielectric layer 10 of the present invention passes through dry etching or wet to the semi-surrounding structures of the gate regions JFET 14
Method etching combines realization with thermal oxidation technology.
Further, the doping way in the discrete area P+ floating pbody 8 is non-uniform doping or uniformly mixes in the present invention
It is miscellaneous.
Further, semiconductor material is monocrystalline silicon, silicon carbide or gallium nitride in the present invention.
It is necessary to meet following condition for JFET structure in the discrete area P+ floating pbody 8 of the invention:
1. being separated between the discrete area P+ floating pbody 8 and gate structure by the drift region N- 4；
The gate regions 2.N+ type JFET 14 are located at the neutral region in the discrete area P+ floating pbody 8 when forward blocking；
The depletion layer that the symmetrical gate regions N+ type JFET 14 are generated with P-type JFET channel region 15 in 3.JFET structure
Width can block completely channel region.
Compared with prior art, the beneficial effects of the present invention are:
1. the present invention in the discrete area P+ floating pbody by introducing the area JFET, the area JFET is equivalent to variable resistance；In device
It is able to storage hole when part forward conduction, reduces the saturation conduction pressure drop of device；It is provided in device forward blocking for hole
Quick bleed-off circuit, reduces turn-off time and turn-off power loss.
2. the present invention reduces Miller capacitance Cgc, has by the way that the discrete area P+ floating pbody to be connected to the ground when off
Reduce switch time and switching loss to effect.
3. the semi-surrounding structure of 10 pairs of gate regions JFET 14 of present media layer, can be effectively reduced grid capacitance, drop simultaneously
The low JFET gate leakage that the generation of parasitic NPN triode is formed by the gate regions JFET, the discrete area P+ floating pbody and the drift region N-
Electric current.
4. dielectric layer 10 proposed by the present invention is to the semi-surrounding structure of the gate regions JFET 14, in IGBT slot grid structure technique
Shallow slot is formed, forms thick dielectric layer in 3 technique of gate dielectric layer, JFET channel region 15 is formed by etching shallow slot bottom section
With the contact in the discrete area P+ floating pbody；JFET structure is formed finally by deposit and doping process, with existing high pressure IGBT device
Part manufacture craft is compatible.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the area traditional discrete floating pbody IGBT device；
Fig. 2 is the structural schematic diagram provided by the invention with low noise low switching losses IGBT device；
Fig. 3 is provided by the invention with low noise low switching losses IGBT device equivalent circuit diagram；
Fig. 4 is IGBT structure provided by the invention and traditional structure switching process comparison of wave shape figure；
Fig. 5 is IGBT structure provided by the invention and traditional structure Miller capacitance Cgc comparison diagram；
In figure: 1 is N+ emitter region, and 2 be the base area P+, and 3 be gate dielectric layer, and 4 be the drift region N-, and 5 be N-type buffer layer, and 6 be P+
Collecting zone, 7 be metal collector, and 8 be the discrete area P+ floating pbody, and 9 be gate electrode, and 10 be dielectric layer, and 11 emit for metal
Pole, 12 be connecting bridge, and 13 be P+ type JFET source region, and 14 be the gate regions N+ type JFET, and 15 be P-type JFET channel region.
Specific embodiment
With reference to the accompanying drawings of the specification technical solution of the present invention in detail, clearly explain with specific embodiment
It states:
Embodiment:
One kind having low noise low switching losses IGBT device, as shown in Fig. 2, its structure cell includes from bottom to up successively
Metal collector 7, P+ collecting zone 6, N-type buffer layer 5, the drift region N- 4 and the metal emitting 11 of stacking；The drift region N- 4
Top layer intermediate region be equipped with the discrete area P+ floating pbody 8, the two sides in the discrete area P+ floating pbody 8 are respectively equipped with P+ base
The top layer in area 2, the base area P+ 2 is equipped with N+ emitter region 1；The base area P+ 2 and N+ emitter region 1 by metal emitting 11 and are divided
The vertical area P+ floating pbody 8 is in contact；Grid is equipped between the base area P+ 2 and N+ emitter region 1 and the discrete area P+ floating pbody 8
Structure, the gate structure include gate electrode 9 and gate dielectric layer 3, and gate dielectric layer 3 extends into N- drift along device vertical direction
Groove is formed in area 4, the setting of gate electrode 9 is in the trench；The side and the base area P+ 2, N+ emitter region 1 of the gate dielectric layer 3
It is contacted with the drift region N- 4, it is characterised in that: the other side of the gate dielectric layer 3 and the discrete area P+ floating pbody 8 are floated by N-
Area 4 is moved to be isolated；The gate regions N+ type JFET 14, P+ type JFET source region 13 and P- are additionally provided in the discrete area P+ floating pbody 8
The JFET structure that type JFET channel region 15 is formed；P-type JFET channel region 15 is arranged in discrete 8 top layer of the area P+ floating pbody
Between region, the top layer of P-type JFET channel region 15 is arranged in the P+ type JFET source region 13, and the gate regions 14 N+ type JFET are right
Claim the two sides that P+ type JFET source region 13 is set and is in contact by connecting bridge 12 with gate electrode 9；The gate regions N+ type JFET
It is isolated between 14 and the discrete area P+ floating pbody 8 by dielectric layer 10；The P+ type JFET source region 13 passes through metal emitting 11
It is in contact with the base area P+ 2 and N+ emitter region 1；Between the metal emitting 11 and the drift region N- 4 and P-type JFET channel region 15
And it is isolated respectively by dielectric layer 10 between connecting bridge 12 and the drift region N- 4.
Preferably, the junction depth in the discrete area P+ floating pbody 8 is greater than gate structure (i.e. slot in the present embodiment
Grid) depth；In this way in device forward blocking, the area p-type floating pbody 8 can form depletion region with the drift region N- 4, weaken
The electric field aggregation phenomenon of gate structure (slot grid) bottom when forward blocking, to ensure that groove gate type high pressure IGBT device just
To the reliability of pressure resistance.
The principle of the invention is described in detail below with reference to embodiment:
For mentioned structure in forward blocking, IGBT grid is zero potential, and JFET channel is connected at this time, discrete P+ floating
The area pbody 8 is directly connected to the ground by JFET channel, increases floating pbody/N- drift region pressure resistance PN junction；Discrete P+ simultaneously
The junction depth in the area floating pbody 8 is greater than the depth of gate structure, and the electric field that can weaken forward blocking time slot grid bottom gathers now
As helping to promote breakdown voltage to realize effect identical with floating field limiting ring.In contrast, Fig. 1's is traditional discrete floating
The empty area pbody IGBT device structure, the discrete area P+ floating pbody 8 store excessive hole in forward conduction, and hole is only when shutdown
The base area P+ (i.e. the area P-base) hole of releasing of cellular can be passed through, so that turn-off time and turn-off power loss increase；Simultaneously in forward direction
When blocking, the area discrete floating pbody current potential floating, although the peak electric field of slot grid bottom can be reduced, partial pressure effect is not so good as
The area pbody ground connection, so that forward blocking voltage is lower than proposed structure.
When device forward conduction, IGBT grid is high potential, at this time the gate regions N+ type JFET 14 and P-type JFET channel region
15 form depletion layer, and the discrete area P+ floating pbody 8 will not connect with ground potential.Electronics is from MOS Channeling implantation to drift region
In, hole is injected into the drift region N- 4 from the metal collector 7 at back, and conductance modulation effect occurs for the drift region N- 4；Meanwhile it is empty
Cave can be stored in the discrete area P+ floating pbody 8, and according to elrectroneutrality pcharge-neutrality principle, corresponding electronics is had in the drift region N- 4, thus
4 carriers concentration of the drift region N- is enhanced, device saturation conduction pressure drop is advantageously reduced.As hole is in discrete P+ floating
Quantity in the area pbody 8 increases, and the current potential in the discrete area P+ floating pbody 8 is approximately equal to 4 current potential of the drift region N-, by N+ type JFET
The NPN transistor that gate regions 14, the discrete area P+ floating pbody 8 and the drift region N- 4 are formed, which exists, opens risk, in mentioned structure
Dielectric layer 10 realizes semi-surrounding to the gate regions JFET 14, can reduce parasitic NPN transistor PN junction area, reduces parasitic NPN and increases
Benefit improves IGBT grid control ability to effectively reduce leakage current of the device in conducting at JFET grid.Because discrete
The area P+ floating pbody is connected to the ground when off, reduces Miller capacitance Cgc, to reduce gate voltage in switching process
Plateau, can significantly reduce switch time and switching loss.Half packet of the dielectric layer 10 of the present invention to the gate regions JFET 14
Closed structure reduces the relative area of JFET grid and collector, is conducive to the grid capacitance for further decreasing device entirety.
Device architecture proposed by the present invention determines that device can be realized reliable forward blocking ability, effectively inhibits and posts
Raw NPN triode is opened, and the grid-control ability of device is improved, and can reduce Miller capacitance Cgc, when realizing shorter switch
Between, lower switching loss, while JFET be low-noise device, ensure that the low-noise characteristic of devices switch process.
In order to verify beneficial effects of the present invention, by taking 3300V high pressure N-channel groove gate type IGBT design as an example, utilize
MEDICI software proposes that IGBT device structure is imitated to the present invention shown in traditional IGBT device structure shown in FIG. 1 and Fig. 2
It is true to compare, the static parameter including device: forward blocking voltage, saturation conduction pressure drop and threshold voltage, dynamic parameter: Miller electricity
It is as shown in the table to hold Cgc, unlatching loss and turn-off power loss, comparing result:
It is obviously found from table, the mentioned structure forward blocking voltage of the present invention is 4297V, is improved compared to traditional structure
13%, both conduction voltage drops quite, and open loss and turn-off power loss be then substantially reduced, especially Miller capacitance Cgc compared to
Traditional structure reduces 70%.
Fig. 4 switching process simulation result shows the turn-off speed of IGBT device structure proposed by the present invention compared to tradition
Structure is obviously improved, because of the reduction of Miller capacitance Cgc, mentioned structure grid voltage plateau is substantially reduced.Fig. 5 capacitor
Simulation result directly shows that in the Vce voltage range of 0-200V, the Cgc of mentioned structure has obviously compared to traditional structure
It reduces, under the conditions of Vce=25V, Cgc maximum reduces 70%.
In conclusion it is provided by the invention a kind of with low noise low switching losses IGBT device, compared to current tradition
Structure, the JFET structure that the present invention introduces low noise in the area discrete floating pbody, stores hole in device forward conduction, increases
Strong conductance modulation, when shutdown, quickly release hole, reduce the turn-off time；Semi-surrounding knot is formed in the gate regions JFET by dielectric layer
Structure, reduces the Miller capacitance of device, while inhibiting influence of the parasitic NPN unlatching to grid voltage in JFET structure, has reached and has protected
Under conditions of demonstrate,proving low noise, switch time and switching loss are reduced.
It should be strongly noted that being applicable not only at present about low noise low switching losses IGBT device in the present invention
The high pressure range IGBT device of commonly used 3300V~6500V is equally applicable to the middle pressure model based on planar gate and groove gate type
The enhanced IGBT device of the carrier enclosed.
Claims (5)
1. a kind of IGBT device with low noise low switching losses characteristic, structure cell includes stacking gradually to set from bottom to up
Metal collector (7), P+ collecting zone (6), N-type buffer layer (5), the drift region N- (4) and the metal emitting (11) set；The N-
The top layer intermediate region of drift region (4) be equipped with the discrete area P+ floating pbody (8), the two of the discrete area P+ floating pbody (8)
Side is respectively equipped with the base area P+ (2), and the top layer of the base area P+ (2) is equipped with N+ emitter region (1)；The base area P+ (2) and N+ transmitting
Area (1) is in contact by metal emitting (11) with the discrete area P+ floating pbody (8)；The base area P+ (2) and N+ emitter region
(1) gate structure is equipped between the discrete area P+ floating pbody (8), the gate structure includes gate electrode (9) and gate dielectric layer
(3), gate dielectric layer (3) is extended into along device vertical direction forms groove in the drift region N- (4), gate electrode (9) setting
In the trench；The side of the gate dielectric layer (3) is contacted with the base area P+ (2), N+ emitter region (1) and the drift region N- (4), feature
Be: the other side of the gate dielectric layer (3) is isolated with the discrete area P+ floating pbody (8) by the drift region N- (4)；It is described
The gate regions N+ type JFET (14), P+ type JFET source region (13) and P-type JFET channel are additionally provided in the discrete area P+ floating pbody (8)
The JFET structure that area (15) is formed；P-type JFET channel region (15) is arranged in the middle area of the discrete area P+ floating pbody (8) top layer
Domain, top layer of P+ type JFET source region (13) setting in P-type JFET channel region (15), the gate regions N+ type JFET (14)
It is symmetricly set on the two sides of P+ type JFET source region (13) and is in contact by connecting bridge (12) with gate electrode (9)；The N+ type
It is isolated between the gate regions JFET (14) and the discrete area P+ floating pbody (8) by dielectric layer (10)；The P+ type JFET source region
(13) it is in contact by metal emitting (11) with the base area P+ (2) and N+ emitter region (1)；The metal emitting (11) and N- float
It moves between area (4) and P-type JFET channel region (15) and passes through dielectric layer respectively between connecting bridge (12) and the drift region N- (4)
(10) it is isolated.
2. according to claim 1 a kind of with low noise low switching losses IGBT device, it is characterised in that: P-type JFET
The width of channel region (15) is less than the width of JFET generation depletion region under the conditions of device on-state.
3. according to claim 2 a kind of with low noise low switching losses IGBT device, it is characterised in that: the medium
Layer (10) forms the semi-surrounding structure to the gate regions JFET (14).
4. according to claim 3 a kind of with low noise low switching losses IGBT device, it is characterised in that: described discrete
The junction depth in the area P+ floating Pbody (8) is greater than the depth of the gate structure.
5. one kind according to any one of claims 1-4 has low noise low switching losses IGBT device, feature exists
In: the material of semiconductor used in device is monocrystalline silicon, silicon carbide or gallium nitride.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109768080A (en) * | 2019-01-23 | 2019-05-17 | 电子科技大学 | A kind of IGBT device with MOS control hole access |
| CN110265477A (en) * | 2019-06-28 | 2019-09-20 | 电子科技大学 | IGBT device with PNP break-through triode |
| CN113764510A (en) * | 2021-07-30 | 2021-12-07 | 西安电子科技大学 | Novel low turn-off loss electron injection effect enhanced IGBT device |
Citations (3)
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109768080A (en) * | 2019-01-23 | 2019-05-17 | 电子科技大学 | A kind of IGBT device with MOS control hole access |
| CN109768080B (en) * | 2019-01-23 | 2021-03-30 | 电子科技大学 | IGBT device with MOS control hole access |
| CN110265477A (en) * | 2019-06-28 | 2019-09-20 | 电子科技大学 | IGBT device with PNP break-through triode |
| CN110265477B (en) * | 2019-06-28 | 2020-12-29 | 电子科技大学 | IGBT device with PNP punch-through triode |
| CN113764510A (en) * | 2021-07-30 | 2021-12-07 | 西安电子科技大学 | Novel low turn-off loss electron injection effect enhanced IGBT device |
| CN113764510B (en) * | 2021-07-30 | 2022-09-09 | 西安电子科技大学 | Low-turn-off-loss IGBT device with enhanced electron injection effect |
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