CN109065618B - IGBT with firm short circuit bearing capacity - Google Patents
IGBT with firm short circuit bearing capacity Download PDFInfo
- Publication number
- CN109065618B CN109065618B CN201810953482.0A CN201810953482A CN109065618B CN 109065618 B CN109065618 B CN 109065618B CN 201810953482 A CN201810953482 A CN 201810953482A CN 109065618 B CN109065618 B CN 109065618B
- Authority
- CN
- China
- Prior art keywords
- region
- type
- igbt
- diode
- jfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 210000000746 body region Anatomy 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- 239000002210 silicon-based material Substances 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 13
- 230000003071 parasitic effect Effects 0.000 abstract description 10
- 230000002441 reversible effect Effects 0.000 abstract description 8
- 238000007599 discharging Methods 0.000 abstract 2
- 230000000903 blocking effect Effects 0.000 description 10
- 230000001965 increasing effect Effects 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 230000003111 delayed effect Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses an IGBT with stable short circuit bearing capacity, and belongs to the technical field of power semiconductor devices. The invention introduces JFET structures (13), (14) and (15) equivalent to variable resistors, a diode N-type region (16) and a diode P-type region (17) into a discrete floating body region (8) of the traditional IGBT device; storing holes when the device is normally conducted, providing a hole discharging path in the short-circuit conduction and short-circuit turn-off processes, quickly discharging the holes, and reducing short-circuit current during short-circuit conduction; the JFET grid (14) is connected with the IGBT grid (9) through a reverse voltage-withstanding diode, so that leakage current at the JFET grid in the short-circuit process is reduced, a parasitic triode is restrained from being opened, the application requirements of positive and negative grid voltage driving are met, and the grid control and short-circuit turn-off capabilities of the device are remarkably improved.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to an IGBT with stable short circuit bearing capacity.
Background
With the rapid development of the fields of high-speed railways, smart grids, new energy vehicles and the like, an Insulated Gate Bipolar Transistor (IGBT) has become one of mainstream power switching devices in a medium-high power range by virtue of the advantages of easy driving of a Gate, high input impedance, high switching speed, large current density, reduction of saturation voltage and the like; meanwhile, the IGBT device technology will continue to develop towards high voltage, large current, high working temperature, high reliability and the like, and is listed as a major special subject by the nation to be researched.
In application of the high-voltage IGBT device, particularly in the motor driving process, two ends of the device can be subjected to a short circuit condition; the device conducts in the event of a short circuit of the load, there being a brief sharp temperature rise process. The short-circuit failure of the IGBT is represented by immediate failure and delayed failure (delayed failure) in time, wherein the delayed failure is mainly a phenomenon of hot rush caused by temperature rise and is a common short-circuit failure mode of a high-voltage IGBT device; the short-circuit withstand time is an important parameter for measuring the short-circuit resistance of the device, and is typically 10 mus. In order to improve the short-circuit resistance of the device, the short-circuit saturation current of the device should be as low as possible under the heat dissipation condition of the existing module package, so as to reduce the generation of heat during the short-circuit process. High-voltage IGBTs generally adopt a planar gate structure, and are often used in environments where high-speed rails, power transmission, and the like have high requirements for reliability (particularly short-circuit capability), and researchers have proposed various structures such as planar gate injection-enhanced gate bipolar transistors (HiGT), enhanced planar IGBTs (EP-IGBTs), and Emitter Ballast Resistors (EBR) -IGBTs to improve the short-circuit capability thereof. However, the concentration of the hole barrier layer introduced by the HiGT in the Pbase region under the planar gate is too high, so that avalanche breakdown can occur in a PN junction formed by the Pbase and the hole barrier layer in advance, and the breakdown voltage of the device is reduced; the EP-IGBT short circuit capability is improved, the design of a current carrier storage layer, a soft penetrating buffer layer and a current collecting area needs to be optimized at the same time, and the forward blocking voltage cannot be influenced; in the layout design of the EBR-IGBT, an emitter ballast resistor formed by an N + doped region is introduced, and the resistance value of the EBR-IGBT usually presents a weak positive temperature coefficient, so that the short-circuit capability of the device at high temperature is weakened.
With the continuous improvement of the grooving process, the parasitic JFET (junction field effect transistor) resistance of the planar gate type IGBT is eliminated in the groove gate type IGBT, so that the saturation voltage drop and the on-state loss are reduced; however, the trench gate type igbt (trench igbt) has an electric field peak at the bottom of the trench gate, which limits the improvement of blocking voltage, and has a large short-circuit current and a weak short-circuit resistance. The current density of the device can be reduced by adopting a wide slot gate spacing or an FP (Floating-Pbody) area, and the short circuit bearing capacity of the TIGBT is obviously improved, but the voltage change generated in the FP structure when the device is turned on is caused by the negative gate capacitance effect of the slot gate type IGBT (FP-TIGBT) with the FP structure, and the displacement current is generated at the gate through the miller capacitance Cgc, so that the gate control capacity of the IGBT is reduced, and meanwhile, the EMI noise problem is brought.
Foreign enterprises such as ABB and Hitachi have already proposed 3300V-TIGBT products, through the built-in junction depth exceeds the discrete Floating P area (Separate Floating Pbody) of the depth of the grooved gate, play and reduce the electric field peak value and enhance the effects of conductivity modulation of the bottom of grooved gate, improve Eoff-Vcesat trade-off relation, improve EMI noise problem at the same time, but Separate FP area will influence the withstand voltage and turn-on characteristic of the device; meanwhile, the holes stored in the separate FP regions during forward conduction cannot be extracted from the FP regions in time when the FP regions are turned off under the condition of short circuit, so that the delay failure of the device is easily caused, and the short circuit bearing capacity of the device is reduced. The discrete FP is connected to ground through a fixed resistor to provide a partial hole path, which tends to increase conduction loss. In order to reduce the switching time and the turn-off reliability of the high-voltage IGBT, a positive and negative grid voltage control scheme is often adopted, so that more restrictions are put on the IGBT grid structure.
Disclosure of Invention
In view of the above, the present invention provides an IGBT with stable short circuit tolerance, which is directed to the problem that the short circuit turn-off capability and the short circuit tolerance of the device are reduced due to the FP region storing holes in the conventional trench gate IGBT device with a discrete floating P region. The groove is formed in the discrete FP, the JFET structure is arranged in the groove to form a hole carrier control structure, the hole carrier control structure is equivalent to a variable resistor, the conduction voltage drop of the device is guaranteed to be equivalent to that of the traditional discrete FP structure when the device is normally conducted, an extra hole release access is provided when the device is conducted under the short-circuit condition, the conduction voltage drop of the device is increased, the short-circuit saturation current is reduced, and the short-circuit turn-off capability and the short-circuit bearing time of the device are improved.
In order to achieve the above purpose, the invention provides the following technical scheme:
a cell structure of the IGBT with stable short circuit bearing capacity comprises a metal collector 7, a P + collector region 6, an N-type buffer layer 5, an N-drift region 4 and a metal emitter 11 which are sequentially stacked from bottom to top; a discrete P + floating pbody region 8 is arranged in the middle area of the top layer of the N-drift region 4, P + base regions 2 are respectively arranged on two sides of the discrete P + floating pbody region 8, and an N + emitter region 1 is arranged on the top layer of each P + base region 2; the P + base region 2 and the N + emitter region 1 are in contact with the discrete P + floating pbody region 8 through a metal emitter 11; a gate structure is arranged between the P + base region 2 and the N + emitter region 1 and the discrete P + floating body region 8, the gate structure comprises a gate electrode 9 and a gate dielectric layer 3, the gate dielectric layer 3 extends into the N-drift region 4 along the vertical direction of the device to form a groove, and the gate electrode 9 is arranged in the groove; one side of the gate dielectric layer 3 is contacted with the P + base region 2, the N + emitter region 1 and the N-drift region 4, and the method is characterized in that: the other side of the gate dielectric layer 3 is isolated from the discrete P + floating body region 8 through the N-drift region 4; the discrete P + floating body region 8 is also provided with a JFET structure formed by an N + type JFET gate region 14, a P + type JFET source region 13 and a P-type JFET channel region 15; the P-type JFET channel region 15 is arranged in the middle area of the top layer of the discrete P + floating body region 8, the P + type JFET source region 13 is arranged on the top layer of the P-type JFET channel region 15, the N + type JFET gate regions 14 are symmetrically arranged on two sides of the P + type JFET source region 13 and are in contact with the gate electrode 9 through the connecting bridge 12, the diode N-type region 16 and the diode P-type region 17; the N + type JFET gate region 14 is isolated from the discrete P + floating body region 8 through a dielectric layer 10; the P + type JFET source region 13 is in contact with the P + base region 2 and the N + emitter region 1 through the metal emitter 11; the metal emitter 11, the N-drift region 4 and the P-type JFET channel region 15, the diode N-type region 16, the diode P-type region 17, the metal emitter 11 and the N-drift region 4, and the connecting bridge 12 and the N-drift region 4 are respectively isolated through the dielectric layer 10.
Furthermore, the diode formed by the diode N-type region 16 and the diode P-type region 17 has the characteristics of low conduction voltage, small junction capacitance and high breakdown voltage.
Further, the diode N-type region 16 and the diode P-type region 17 are made of polysilicon or monocrystalline silicon material.
Further, the junction depth of the discrete P + floating pbody regions 8 in the present invention is greater than the depth of the gate structure.
Further, in the present invention, the dielectric layer 10 forms a half-wrap-around structure for the JFET gate region 14, eliminating the PN junction capacitance between the JFET gate region 14 and the discrete P + floating pbody region 8.
Furthermore, the doping manner of the diode N-type region 16 and the diode P-type region 17 in the present invention is non-uniform doping or uniform doping.
Furthermore, the semiconductor material in the invention is monocrystalline silicon, silicon carbide or gallium nitride.
The JFET structure introduced in the discrete P + floating pbody region 8 of the present invention needs to satisfy the following conditions:
1. the discrete P + floating body region 8 is separated from the grid structure through the N-drift region 4;
the N + type JFET gate region 14 is located in the neutral region of the discrete P + floating pbody region 8 when forward blocked;
and 3, the depletion layer width generated by the N + type JFET gate region 14 and the P-type JFET channel region 15 which are symmetrical left and right in the JFET structure can completely block the channel region.
And 4, ohmic contact is formed between the N + type JFET gate regions 14 which are symmetrical left and right in the JFET structure and the corresponding diode N-type regions 16, diode P-type regions 17 and the connecting bridge 12.
Compared with the prior art, the invention has the beneficial effects that:
1. according to the invention, the JFET area is introduced into the discrete P + floating body area, and the JFET area is equivalent to a variable resistor; holes can be stored when the device is conducted in the forward direction, and the saturation conduction voltage drop of the device is equivalent to that of the traditional structure; when the device is blocked in the forward direction, the discrete FP area is grounded, and the breakdown voltage of the device is improved.
2. According to the JFET structure, under the condition of short-circuit conduction of the device, the potential of the discrete FP region rises, so that a JFET channel is opened, the degree of conductivity modulation in a drift region is reduced, the conduction voltage drop under the condition of short-circuit conduction is improved, the short-circuit current is reduced, and the short-circuit bearing capacity of the device is favorably improved.
3. In the short-circuit turn-off process of the device, the JFET channel is in a conducting condition due to the control effect of the JFFT grid, so that a hole discharge path is increased during turn-off, a hole discharge path is shortened, delay failure is inhibited, and the reliability of short-circuit turn-off is improved.
4. The JFET gate region 14 is connected with the IGBT gate 9 sequentially through the reverse diode N-type region 16 and the diode P-type region 17, so that leakage current generated from the JFET gate region 14 can be reduced, and the application requirements of the IGBT under the conditions of positive and negative gate voltages can be met.
5. The semi-surrounding structure of the dielectric layer 10 to the JFET gate region 14 can reduce the JFET gate leakage current generated when the IBGT is switched on, wherein a parasitic NPN triode is formed by the JFET gate region, the discrete P + floating body region and the N-drift region.
6. The diode N-type region 16 and the diode P-type region 17 are compatible with the existing IGBT polysilicon grid manufacturing process.
Drawings
FIG. 1 is a schematic structural diagram of a conventional discrete floating body IGBT device;
FIG. 2 is a schematic structural diagram of an IGBT with a stable short circuit tolerance provided by the present invention;
FIG. 3 is an equivalent circuit diagram of an IGBT with a robust short circuit withstand capability according to the present invention;
FIG. 4 is a current line distribution of the front side structure when the IGBT structure provided by the invention is normally turned on;
FIG. 5 shows the current line distribution of the front side structure when the IGBT structure provided by the invention is in short circuit conduction;
FIG. 6 is the current line distribution of the front side structure when the conventional IGBT structure is short-circuited and turned on;
FIG. 7 is a comparison of the short circuit simulation waveforms of the IGBT structure provided by the present invention and the conventional structure;
in the figure: the semiconductor device comprises a substrate, a semiconductor substrate, a.
Detailed Description
The technical scheme of the invention is described in detail and clearly in the following description with reference to the accompanying drawings and the specific embodiments:
example (b):
an IGBT with a stable short circuit endurance is disclosed, as shown in fig. 2, a cell structure of the IGBT includes a metal collector 7, a P + collector region 6, an N-type buffer layer 5, an N-drift region 4, and a metal emitter 11, which are sequentially stacked from bottom to top; a discrete P + floating pbody region 8 is arranged in the middle area of the top layer of the N-drift region 4, P + base regions 2 are respectively arranged on two sides of the discrete P + floating pbody region 8, and an N + emitter region 1 is arranged on the top layer of each P + base region 2; the P + base region 2 and the N + emitter region 1 are in contact with the discrete P + floating pbody region 8 through a metal emitter 11; a gate structure is arranged between the P + base region 2 and the N + emitter region 1 and the discrete P + floating body region 8, the gate structure comprises a gate electrode 9 and a gate dielectric layer 3, the gate dielectric layer 3 extends into the N-drift region 4 along the vertical direction of the device to form a groove, and the gate electrode 9 is arranged in the groove; one side of the gate dielectric layer 3 is contacted with the P + base region 2, the N + emitter region 1 and the N-drift region 4, and the method is characterized in that: the other side of the gate dielectric layer 3 is isolated from the discrete P + floating body region 8 through the N-drift region 4; the discrete P + floating body region 8 is also provided with a JFET structure formed by an N + type JFET gate region 14, a P + type JFET source region 13 and a P-type JFET channel region 15; the P-type JFET channel region 15 is arranged in the middle area of the top layer of the discrete P + floating body region 8, the P + type JFET source region 13 is arranged on the top layer of the P-type JFET channel region 15, the N + type JFET gate regions 14 are symmetrically arranged on two sides of the P + type JFET source region 13 and are in contact with the gate electrode 9 through the connecting bridge 12, the diode N-type region 16 and the diode P-type region 17; the N + type JFET gate region 14 is isolated from the discrete P + floating body region 8 through a dielectric layer 10; the P + type JFET source region 13 is in contact with the P + base region 2 and the N + emitter region 1 through the metal emitter 11; the metal emitter 11, the N-drift region 4 and the P-type JFET channel region 15, the diode N-type region 16, the diode P-type region 17, the metal emitter 11 and the N-drift region 4, and the connecting bridge 12 and the N-drift region 4 are respectively isolated through the dielectric layer 10.
In the preferred embodiment, the junction depth of the discrete P + floating body region 8 is greater than the depth of the gate structure (i.e., the trench gate), so that when the device is forward-blocked, the electric field concentration at the bottom of the gate structure (i.e., the trench gate) during forward-blocking can be reduced, thereby ensuring the reliability of the forward withstand voltage of the trench gate type IGBT device. The diode N-type region 16 and the diode P-type region 17 are made of polycrystalline silicon materials, a polycrystalline silicon diode with low on-state voltage, small junction capacitance and high breakdown voltage is formed, and ohmic contact is formed between the polycrystalline silicon diode and the N + type JFET gate region 14 and the connecting bridge 12.
The principles of the present invention are described in detail below with reference to examples:
the basic static parameters of the proposed structure are superior to those of the conventional structure in the normal operating state. When the IGBT is forwardly blocked, the grid electrode of the IGBT is at zero potential, the JFET channel is conducted, the discrete P + floating pbody region 8 is directly connected with the ground through the JFET channel, and a pressure-resistant PN junction of the floating pbody/N-drift region is increased; meanwhile, the junction depth of the discrete P + floating body region 8 is larger than the depth of the grid structure, so that the electric field concentration phenomenon at the bottom of the groove grid during forward blocking can be weakened, and the breakdown voltage can be improved. In contrast, in the conventional discrete floating pbody region IGBT device structure of fig. 1, when forward blocking occurs, the potential of the discrete floating pbody region floats, and although the electric field peak at the bottom of the trench gate can be reduced, the voltage division effect is not as good as that of the pbody region, so that the forward blocking voltage is lower than that of the proposed structure.
When the device is in forward conduction, the IGBT gate electrode is at high potential, at the moment, the N + type JFET gate region 14 and the P-type JFET channel region 15 form a depletion layer, and the separated P + floating body region 8 cannot be connected with the ground potential and has the same working mode as the traditional structure. Electrons are injected into the drift region from the MOS channel, holes are injected into the N-drift region 4 from the P + collector region 6 on the back, and the N-drift region 4 has a conductance modulation effect; meanwhile, holes can be stored in the discrete P + floating body region 8, and corresponding electrons can be generated in the N-drift region 4 according to the electric neutral principle, so that the carrier concentration in the N-drift region 4 is enhanced, and the saturated conduction voltage drop of the device is favorably reduced. The medium layer 10 in the proposed structure realizes half-surrounding of the JFET gate region 14, so that the area of a parasitic NPN transistor PN junction formed by the N + type JFET gate region 14, the discrete P + floating body region 8 and the N-drift region 4 can be reduced, and parasitic NPN gain is reduced; meanwhile, the N + type JFET gate region 14 is connected with the IGBT gate 9 through the polysilicon diode in reverse connection, so that leakage current of the device passing through the JFET gate during conduction can be effectively reduced, and the IGBT gate control capability is improved.
When the structure is conducted under a short circuit condition, compared with a normal conducting state, the two ends of the device bear 80% of forward blocking voltage, so that the current flowing through the device is increased rapidly; the potential of the discrete P + floating body region 8 rises along with the rising of the potential, so that the reverse bias degree of a PN junction formed by the JFET channel/N + type JFET gate region is reduced; because the polysilicon diode connected with the grid electrode of the N + type JFET is in a reverse voltage-resistant state, the leakage current when the PN junction is reversely biased can not pass through the grid electrode of the JFET; the potential of the discrete P + floating body region 8 rises, so that the JFET channel region cannot maintain a pinch-off state, holes in the drift region are transported to the ground end through the JFET channel region, the carrier concentration in the drift region is reduced, the conduction voltage drop of the device is remarkably improved, the short-circuit current is favorably reduced, and the short-circuit withstand time of the device is prolonged.
When the device is in a short-circuit turn-off state, particularly when the device is turned off through negative gate voltage, the JFET channel/N + type JFET gate region is in a forward bias state, a parasitic triode formed by the N + type JFET gate region 14, the discrete P + floating body region 8 and the N type drift region is easy to trigger to be turned on, and then the device is latched and burnt. The N + type JFET gate region 14 of the proposed structure is connected with the IGBT gate 9 through a polysilicon diode in reverse connection, providing an additional voltage-resistant junction, effectively blocking the current path required by the parasitic triode, and meeting the requirements of device turn-off and negative gate voltage application. When the IGBT is turned off, the JFET gate is reduced along with the reduction of the grid potential of the IGBT, and at the moment, the conduction degree of the JFET channel is improved under the control of the grid potential of the JFET channel; compared with the traditional structure that the hole can only be transported through the P + base region 2, the JFET channel provides an extra hole bleeder path with a shorter path in the turn-off process, the probability that the hole collides with a depletion layer of a drift region in the transport path of the P + base region 2 in the short-circuit turn-off process is reduced, and the increase of leakage current is reduced; particularly, under the condition that the lattice temperature is increased in the short circuit turn-off process, positive feedback between hole leakage current and high temperature can be effectively inhibited, the reliability of short circuit turn-off of the device is improved, and the occurrence of delayed failure is inhibited. And the holes in the P + floating body region are separated in the traditional structure and can only be transported through the P + base region, so that positive feedback is easily formed between hole leakage current and high temperature, and the thermal stability and short circuit turn-off capability of the device are reduced.
The device structure provided by the invention determines that the device can meet the application requirements under the positive and negative grid voltage conditions, and the polysilicon diode can effectively inhibit the parasitic NPN triode from being started, so that the grid control capability of the device is improved; meanwhile, when the short circuit is conducted, the JFET channel can be conducted due to the fact that the discrete P + floating body area potential rises, hole carriers flow to the ground end from the JFET channel, conduction voltage drop is remarkably improved, short circuit current of a conduction state is effectively reduced, and short circuit bearing capacity of a device is improved.
In order to verify the beneficial effects of the invention, taking the design of 3300V high-voltage N-channel trench gate type IGBT as an example, the traditional IGBT device structure shown in fig. 1 and the IGBT device structure proposed by the invention shown in fig. 2 are compared in a simulation mode by using the piece of media software, including the static parameters of the devices: the forward blocking voltage, the saturation conduction voltage drop and the threshold voltage, as well as the short-circuit current and the short-circuit withstand time of the device, are shown in the following table:
| parameter(s) | IGBT structure | Traditional IGBT structure |
| Forward blocking voltage (V) | 4297 | 3801 |
| Threshold voltage (V) | 4.45 | 4.56 |
| Conduction voltage drop (V) | 1.7 | 1.7 |
| Short-circuit current (A) | 490 | 502 |
| Short circuit withstand time (μ s) | 11.1 | 10.9 |
The table shows that the forward blocking voltage of the structure provided by the invention is 4297V, which is improved by 13% compared with the traditional structure, and the conduction voltage drop is equivalent to the conduction voltage drop; the proposed structure of the peak current at short circuit conduction is 490A, which is significantly lower than the conventional structure; because the reduction of peak current when short circuit is conducted and the extra hole path are provided by the structure in the turn-off process, the short circuit bearing time of the structure is improved to 11.1 mu s, and the short circuit bearing capacity of the device is improved.
Fig. 4 and 5 show the difference of the carrier transport path of the proposed structure in the case of normal conduction and short-circuit conduction, respectively. The line in the figure is a current line, and when the current line is normally conducted, the current line flows through the discrete FP region and is mainly a hole carrier; because the JFET channel is pinched off under the control of the IGBT grid electrode, the discrete FP area stores holes and plays a role in enhancing the conductance modulation effect in the drift area below. Fig. 5 shows that when the proposed structure is turned on due to a short circuit, the JFET channel cannot be completely pinched off due to the increased potential in the discrete FP region, a hole bleed-off path is formed, and hole carriers in the drift region flow out of the JFET channel, thereby reducing the magnitude of the short-circuit current and increasing the on-state voltage drop. Meanwhile, because the JFET grid is connected with the IGBT grid through the reverse diode, current cannot be discharged from the JFET grid to a grid power supply for driving, a parasitic triode cannot be triggered to be opened, and therefore a current line cannot flow through the JFET grid in the figure 5. In contrast, fig. 6 shows the distribution of current lines when the conventional structure is turned on due to a short circuit, and since there is no hole leakage loop in the discrete FP region, the current lines flowing through the discrete FP region can only flow out through the P-type base region finally, which reduces the reliability of operation during a short circuit.
Fig. 7 is a graph simulating the variation between the current Ice and the voltage Vce after turn-off for two configurations with a short-circuit on-time of 11 μ s. As shown by solid marks in the figure, the current and voltage of the two ends of the device are normally turned off after the short circuit is conducted for 11 mus; after the short circuit of the traditional structure is turned off, the traditional structure is failed after delaying for about 3.5 milliseconds, at the moment, the current rises sharply, the voltage is reduced rapidly, and the device is burnt finally, so that the characteristic that the provided structure has stable short circuit bearing capacity is verified from a short circuit simulation result.
In summary, compared with the conventional structure, the IGBT with the stable short circuit endurance provided by the invention introduces the JFET structure equivalent to the variable resistor in the discrete floating pbody region, stores holes when the device is normally turned on, provides a hole discharge path in the short circuit on and off processes, quickly discharges the holes, reduces the short circuit current when the device is turned on, and improves the short circuit endurance of the device; the JFET grid is connected with the IGBT grid through a reverse voltage-withstanding diode, so that leakage current at the JFET grid in the short circuit process is reduced, a parasitic triode is restrained from being turned on, the application requirements of positive and negative grid voltage driving are met, and the grid control and short circuit turn-off capabilities of the device are remarkably improved.
It should be noted that, the present invention is applicable to IGBT devices with stable short circuit tolerance, not only to IGBT devices in the high voltage range of 3300V to 6500V, which are commonly used at present, but also to IGBT devices in the medium voltage range based on planar gate and trench gate.
Claims (6)
1. A cell structure of the IGBT with stable short circuit bearing capacity comprises a metal collector (7), a P + collector region (6), an N-type buffer layer (5), an N-drift region (4) and a metal emitter (11) which are sequentially stacked from bottom to top; a discrete P + floating pbody region (8) is arranged in the middle area of the top layer of the N-drift region (4), P + base regions (2) are respectively arranged on two sides of the discrete P + floating pbody region (8), and an N + emitter region (1) is arranged on the top layer of the P + base region (2); the P + base region (2) and the N + emitter region (1) are in contact with the discrete P + floating body region (8) through a metal emitter (11); a grid structure is arranged between the P + base region (2) and the N + emitter region (1) and the discrete P + floating body region (8), the grid structure comprises a grid electrode (9) and a grid dielectric layer (3), the grid dielectric layer (3) extends into the N-drift region (4) along the vertical direction of the device to form a groove, and the grid electrode (9) is arranged in the groove; one side of the gate dielectric layer (3) is in contact with the P + base region (2), the N + emitter region (1) and the N-drift region (4), and the method is characterized in that: the other side of the gate dielectric layer (3) is isolated from the discrete P + floating body region (8) through the N-drift region (4); the discrete P + floating body region (8) is also provided with an N + type JFET gate region (14), a P + type JFET source region (13) and a P-type JFET channel region (15) to form a JFET structure; the P-type JFET channel region (15) is arranged in the middle area of the top layer of the discrete P + floating body region (8), the P + type JFET source region (13) is arranged on the top layer of the P-type JFET channel region (15), the N + type JFET gate regions (14) are symmetrically arranged on two sides of the P + type JFET source region (13) and are in contact with the gate electrode (9) through the connecting bridge (12), the diode N-type region (16) and the diode P-type region (17); the N + type JFET gate region (14) and the discrete P + floating body region (8) are isolated by a dielectric layer (10); the P + type JFET source region (13) is in contact with the P + base region (2) and the N + emitter region (1) through a metal emitter (11); the metal emitter (11) is isolated from the N-drift region (4) and the P-type JFET channel region (15), the diode N-type region (16), the diode P-type region (17) is isolated from the metal emitter (11) and the N-drift region (4), and the connecting bridge (12) is isolated from the N-drift region (4) through the dielectric layer (10).
2. The IGBT of claim 1 having robust short circuit withstand capability, wherein: the diode N-type region (16) and the diode P-type region (17) are made of polysilicon or monocrystalline silicon materials.
3. The IGBT of claim 1 having robust short circuit withstand capability, wherein: the doping modes of the diode N-type region (16) and the diode P-type region (17) are non-uniform doping or uniform doping.
4. The IGBT of claim 1 having robust short circuit withstand capability, wherein: ohmic contacts are formed among the N + type JFET gate regions (14) which are symmetrical left and right, the diode N-type region (16), the diode P-type region (17) and the connecting bridge (12).
5. The IGBT of claim 1 having robust short circuit withstand capability, wherein: the junction depth of the discrete P + floating pbody regions (8) is greater than the depth of the gate structures.
6. The IGBT of claim 1 having robust short circuit withstand capability, wherein: the semiconductor material used by the device is monocrystalline silicon, silicon carbide or gallium nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810953482.0A CN109065618B (en) | 2018-08-21 | 2018-08-21 | IGBT with firm short circuit bearing capacity |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810953482.0A CN109065618B (en) | 2018-08-21 | 2018-08-21 | IGBT with firm short circuit bearing capacity |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109065618A CN109065618A (en) | 2018-12-21 |
| CN109065618B true CN109065618B (en) | 2020-05-26 |
Family
ID=64686617
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810953482.0A Active CN109065618B (en) | 2018-08-21 | 2018-08-21 | IGBT with firm short circuit bearing capacity |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109065618B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112038401A (en) * | 2019-06-04 | 2020-12-04 | 中国科学院微电子研究所 | Insulated gate bipolar transistor structure and preparation method thereof |
| CN111415932B (en) * | 2020-03-30 | 2022-10-04 | 电子科技大学 | High-voltage bootstrap diode composite device structure |
| WO2022063210A1 (en) * | 2020-09-24 | 2022-03-31 | 比亚迪半导体股份有限公司 | Semiconductor cell structure, igbt cell structure and preparation method therefor, and semiconductor structure |
| CN113764510B (en) * | 2021-07-30 | 2022-09-09 | 西安电子科技大学 | Low-turn-off-loss IGBT device with enhanced electron injection effect |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107516669A (en) * | 2017-08-07 | 2017-12-26 | 电子科技大学 | A kind of IGBT device |
| CN107623027A (en) * | 2017-10-20 | 2018-01-23 | 电子科技大学 | A kind of trench gate electric charge memory type insulated gate bipolar transistor and its manufacture method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10090294B2 (en) * | 2016-03-04 | 2018-10-02 | Rohm Co., Ltd. | Semiconductor device |
-
2018
- 2018-08-21 CN CN201810953482.0A patent/CN109065618B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107516669A (en) * | 2017-08-07 | 2017-12-26 | 电子科技大学 | A kind of IGBT device |
| CN107623027A (en) * | 2017-10-20 | 2018-01-23 | 电子科技大学 | A kind of trench gate electric charge memory type insulated gate bipolar transistor and its manufacture method |
Non-Patent Citations (2)
| Title |
|---|
| "A New Fin p-Body Insulated Gate Bipolar Transistor With Low Miller Capacitance";Hao Feng等;《IEEE ELECTRON DEVICE LETTERS》;20150630;第36卷(第6期);第591-593页 * |
| "Novel 3.3-kV advanced trench HiGT with low loss and low dv/dt noise";Y.Toyota等;《Proceedings of The 25th International Symposium on Power Semiconductor Devices & ICs，Kanazawa》;20130531;第29-32页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109065618A (en) | 2018-12-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109768080B (en) | IGBT device with MOS control hole access | |
| CN109065618B (en) | IGBT with firm short circuit bearing capacity | |
| CN110797403B (en) | RC-IGBT semiconductor device | |
| CN109427869B (en) | Semiconductor device with a plurality of transistors | |
| CN108493241B (en) | IGBT device with built-in JFET structure | |
| Kopta et al. | The field charge extraction (FCE) diode: a novel technology for soft recovery high voltage diodes | |
| CN110277443B (en) | Trench gate IGBT device with PNP punch-through triode | |
| CN110767753A (en) | SiC power device | |
| CN110993687B (en) | Super junction reverse-conducting gate-controlled bipolar device | |
| CN109888007B (en) | SOI LIGBT device with diode clamped carrier storage layer | |
| CN108493242B (en) | Carrier enhancement type IGBT device for optimizing internal electric field | |
| CN111834449B (en) | Quick turn-off RC-IGBT device with back double MOS structure | |
| CN109065619B (en) | IGBT device with low-noise and low-switching loss characteristics | |
| CN113437141A (en) | Floating P-region CSTBT device with polysilicon diode grid structure | |
| Corvasce et al. | 3300V HiPak2 modules with enhanced trench (TSPT+) IGBTs and field charge extraction diodes rated up to 1800A | |
| CN110504305B (en) | SOI-LIGBT device with self-biased pmos clamp carrier storage layer | |
| CN108766998B (en) | IGBT device with groove gate type JFET structure | |
| CN108417622B (en) | IGBT device | |
| US20150187922A1 (en) | Power semiconductor device | |
| CN112466935B (en) | RC-IGBT device with polycrystalline silicon electronic channel of collector electrode | |
| CN111933687B (en) | Lateral power device with high safety working area | |
| CN109888006B (en) | Low-power-consumption silicon-on-insulator transverse insulated gate bipolar transistor | |
| CN108389899A (en) | RC-IGBT devices and its process | |
| CN110504312B (en) | Transverse IGBT with short circuit self-protection capability | |
| CN108172610B (en) | High-voltage IGBT device with built-in ballast resistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |