CN109002903B - Optimized scheduling method for printed circuit board surface mounting production line - Google Patents

Optimized scheduling method for printed circuit board surface mounting production line Download PDF

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CN109002903B
CN109002903B CN201810598335.6A CN201810598335A CN109002903B CN 109002903 B CN109002903 B CN 109002903B CN 201810598335 A CN201810598335 A CN 201810598335A CN 109002903 B CN109002903 B CN 109002903B
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钱斌
孙在省
胡蓉
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Abstract

The invention relates to an optimized scheduling method for a printed circuit board surface mounting production line, and belongs to the field of intelligent optimized scheduling of production workshops. The method comprises the steps of establishing a disjunctive planning model and determining an optimized target through a scheduling process of a printed circuit board surface mounting production line, and optimizing the target by using an optimized scheduling method based on an improved sine and cosine algorithm; the scheduling problem of the printed circuit board surface mounting production line is represented by an analytic graph G (N, A, E, Re), an analytic planning model is established according to the number of steps and the processing time of each PCB on each chip mounter and the description of the processing sequence of each PCB on each chip mounter in the analytic graph, and the optimization target is total weighted delay time. The invention can improve the mounting efficiency by 12-20%, reduce the production cost of a factory, greatly meet the requirements of customers and improve the economic benefit and reputation of the factory.

Description

Optimized scheduling method for printed circuit board surface mounting production line
Technical Field
The invention relates to an optimized scheduling method for a printed circuit board surface mounting production line, and belongs to the field of intelligent optimized scheduling of production workshops.
Background
A Printed Circuit Board (PCB) assembly system, also called Surface Mount Technology (SMT), is an electronic assembly process Technology for printing and mounting electronic components on a Surface of a PCB or a substrate, and is used as an important electronic connector.
The chip mounter is an implementation form of a surface mounting technology, and has been widely applied to an electronic assembly production line, and the chip mounter is a core technology of the whole production process, and the production speed of the chip mounter directly affects the efficiency of the process. Aiming at a printed circuit board surface mounting production line, the following conditions should be met, namely, firstly, a plurality of chip mounters can be ensured to be capable of mounting components at the same time as much as possible; secondly, only one type of components are stored in each feeder; thirdly, components can be directly mounted, if necessary, the mounting position is corrected by using an image at the upward-looking camera, and the position correction is generally needed for the components packaged by the BGA, so that the mounting precision is ensured; fourthly, the time for replacing the suction nozzle head is reduced. The scheduling process of the printed circuit board surface mounting production line is a complex scheduling problem of a reentrant job shop. Therefore, the method has extremely important practical significance and engineering value in optimizing the component mounting process and shortening the mounting time of the chip mounter. In the actual production flow, the long time for pasting leads to failure of soldering paste on an electronic printing plate, poor pasting effect of components and parts and serious influence on the quality of products; and shortening the process time can significantly improve the above-mentioned disadvantages. Currently, optimization algorithms are mainly divided into two types; one is to optimize the mounting sequence when the positions of the feeders are known, and the other is to optimize the arrangement positions of the feeders when the mounting sequence of the components is fixed. A common method is to separately create a mathematical model for optimizing the mounting sequence of components for the two cases and calculate an optimal solution. The commonly used algorithms mainly include ant colony algorithm, genetic algorithm and the like, and the obtained solution is often a local optimal solution, so that the further improvement of the production speed and the process efficiency is limited.
The invention designs an optimized scheduling method based on an improved sine and cosine algorithm by adopting an extraction planning model, and can obtain an approximately optimal solution of the scheduling problem of the surface mounting production line of the printed circuit board in effective time, thereby reducing the production cost of a factory, greatly meeting the requirements of customers and improving the economic benefit and the credit of the factory.
Disclosure of Invention
The invention aims to provide an optimized scheduling method based on an improved sine and cosine algorithm aiming at the scheduling problem of a printed circuit board surface mounting production line, and solves the problems of factory cost waste, low economic benefit, customer dissatisfaction caused by incomplete processing in a delivery date and the like in the processing process of the printed circuit board surface mounting production line.
The technical scheme of the invention is as follows: an optimal scheduling method of a printed circuit board surface mounting production line is characterized in that a disjunctive planning model is established through a scheduling process of the printed circuit board surface mounting production line, an optimal target is determined, and the target is optimized by using an optimal scheduling method based on an improved sine and cosine algorithm; the scheduling problem of the printed circuit board surface mounting production line is represented by an analytic graph G (N, A, E, Re), an analytic planning model is established according to the process number and the processing time of each PCB on each chip mounter and the description of the processing order of each PCB on each chip mounter in the analytic graph, and the optimization target is total weighted delay time; the disjunctive planning model is described as follows:
Figure GDA0003280952830000021
Figure GDA0003280952830000022
Figure GDA0003280952830000023
Figure GDA0003280952830000024
Figure GDA0003280952830000025
Figure GDA0003280952830000026
where N is a set of process nodes, N is O U {0} {0,1,2, L, TO }, where O is a set of all the processes {1,2, L, TO }, 0 is a virtual node, and TO is N × m × r in totalThe number of processes; u (O) is a set of last process steps for each PCB; the machining start time and the machining time in the virtual process 0 are set to zero; a is a combined arc set, and the combined arc describes sequential constraint of the same PCB process route and is unidirectional; u is a tail arc, describes that the last procedure of each PCB points to a virtual node 0 and is unidirectional; e is a disjunctive arc set which describes the front-back relation of the processing procedures on the same chip mounter, and the disjunctive arc orientation is undetermined and bidirectional before scheduling; re is a reentrant arc set proposed aiming at reentrant characteristics, describes the processing constraint of the same PCB on the same chip mounter and is unidirectional; siIs the starting time of step i, where s00; s is a vector formed by the starting processing time of all the procedures, namely a decision variable; p is a radical ofiA processing time of step i wherein p0＝0；μjThe last process of PCB j; (i)1,i2) For arcs with machining constraints, i.e. machining first1Post-processing i2；＜i1,i2The V-shaped is logic OR and describes the relation of the working procedures in the disjuncting arc; c. Ci、diAnd ωiRespectively the completion time, delivery date and delay weight of the PCB to which the working procedure i belongs;
Figure GDA0003280952830000031
delay time, T, for PCB jj＝max{0,cj-dj}; the process of determining the orientation of the disjunctive arc is the solving process of the scheduling problem;
the optimized scheduling method based on the improved sine and cosine algorithm specifically comprises the following steps:
step1, population initialization: generating an initialization population by adopting a random method according to an operation-based coding mode until the number of initial solutions meets the requirement of population scale, and determining the optimal individual G _ best in the current population; wherein the population size is NP; let t be 1, a be 2, Max _ t be 1000;
step2, population updating: sequencing individuals of the printed circuit board surface mounting production line procedures in the population and converting the individuals based on real number coding into each other by adopting an RSOV rule; let r1 be a-t (a/Max _ t), update all individuals by the following formula, change the individuals based on real number encoding into the individuals based on process encoding, and evaluate;
Figure GDA0003280952830000032
wherein r2 ═ 2 π × Rand, r3 ═ 2 × Rand, r4 ═ Rand, Rand is a random number between 0 and 1, and xt iI individuals in the population of the t generation;
step3, local search: determining the optimal individual G _ best in the current population, performing local search on the G _ best based on All _ Insert, and replacing the individual obtained by local search if the individual is better than the G _ best;
in the local search of the All _ Insert, a procedure is randomly selected, All the insertable positions are reached and evaluated, and the solution with the best target value is selected as the solution of the local search;
step4, judging termination conditions: if t is less than or equal to Max _ t, t is t +1, and Step2 is turned; otherwise, ending and outputting G _ best.
The invention has the beneficial effects that: the invention provides a printed circuit board surface mounting production line scheduling problem which takes total weighted delay as time as a target, establishes a disjunctive planning model, and utilizes an improved sine and cosine algorithm to effectively reduce the risk of falling into a local optimal solution, obtain a globally optimal solution of a PCB mounting sequence and realize the optimization of a mounting process; the method can improve the mounting efficiency by 12-20%, can reduce the production cost of a factory, can greatly meet the requirements of customers, and can improve the economic benefit and the credit of the factory.
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FIG. 1 is a general design flow diagram of the present invention;
FIG. 2 is an overall algorithm flow diagram of the present invention;
FIG. 3 is a diagram illustrating an All _ Insert neighborhood structure according to the present invention.
Detailed Description
Example 1: as shown in fig. 1-3, an optimized scheduling method for a printed circuit board surface mount production line, which establishes an extraction planning model and determines an optimized target through a scheduling process of the printed circuit board surface mount production line, and optimizes the target by using an optimized scheduling method based on an improved sine and cosine algorithm; the scheduling problem of the printed circuit board surface mounting production line is represented by an analytic graph G (N, A, E, Re), an analytic planning model is established according to the process number and the processing time of each PCB on each chip mounter and the description of the processing order of each PCB on each chip mounter in the analytic graph, and the optimization target is total weighted delay time; the disjunctive planning model is described as follows:
Figure GDA0003280952830000041
Figure GDA0003280952830000042
Figure GDA0003280952830000043
Figure GDA0003280952830000044
Figure GDA0003280952830000045
Figure GDA0003280952830000046
where N is a set of process nodes, N is O U {0} {0,1,2, L, TO }, where O is a set of all the processes, 0 is a virtual node, and TO is N × m × r is the total number of processes; u (O) is a set of last process steps for each PCB; the machining start time and the machining time in the virtual process 0 are set to zero; a is a combined arc set, and the combined arc describes sequential constraint of the same PCB process route and is unidirectional; u is a tail arc and is a tail arc,describing that the last procedure of each PCB points to a virtual node 0 and is unidirectional; e is a disjunctive arc set which describes the front-back relation of the processing procedures on the same chip mounter, and the disjunctive arc orientation is undetermined and bidirectional before scheduling; re is a reentrant arc set proposed aiming at reentrant characteristics, describes the processing constraint of the same PCB on the same chip mounter and is unidirectional; siIs the starting time of step i, where s00; s is a vector formed by the starting processing time of all the procedures, namely a decision variable; p is a radical ofiA processing time of step i wherein p0＝0；μjThe last process of PCB j; (i)1,i2) For arcs with machining constraints, i.e. machining first1Post-processing i2；＜i1,i2The V-shaped is logic OR and describes the relation of the working procedures in the disjuncting arc; c. Ci、diAnd ωiRespectively the completion time, delivery date and delay weight of the PCB to which the working procedure i belongs;
Figure GDA0003280952830000051
delay time, T, for PCB jj＝max{0,cj-dj}; the process of determining the orientation of the disjunctive arc is the solving process of the scheduling problem;
the optimized scheduling method based on the improved sine and cosine algorithm specifically comprises the following steps:
step1, population initialization: generating an initialization population by adopting a random method according to an operation-based coding mode until the number of initial solutions meets the requirement of population scale, and determining the optimal individual G _ best in the current population; wherein the population size is PopSize; let t be 1, a be 2, Max _ t be 1000;
step2, population updating: the mutual conversion of the individual pi in the procedure sequence of the surface mounting production line of the printed circuit board in the population and the individual x based on the real number coding is realized by adopting an RSOV rule; RSOV regular coding examples of n × m × r ═ 3 × 2 × 2 as in table 1;
table 1 expression of solutions of nxmxr ═ 3 × 2 × 2
Figure GDA0003280952830000052
Let r1 be a-t (a/Max _ t), update all individuals by the following formula, change the individuals based on real number encoding into the individuals based on process encoding, and evaluate;
Figure GDA0003280952830000053
wherein r2 ═ 2 π × Rand, r3 ═ 2 × Rand, r4 ═ Rand, Rand is a random number between 0 and 1, and xt iI individuals in the population of the t generation;
step3, local search: and determining the optimal individual G _ best in the current population, performing local search on the G _ best based on All _ Insert, and replacing the individual obtained by the local search if the individual is better than the G _ best.
The local search of All _ Insert is to randomly select a procedure, bring it to All insertable positions and evaluate it, and select the solution with the best target value as the solution of the local search.
Step4, judging termination conditions: if t is less than or equal to Max _ t, t is t +1, and Step2 is turned; otherwise, ending and outputting G _ best.
The population size PopSize is set to 100, the maximum iteration times Max _ t is set to 1000, the reentry times r are set to 3, and the processing time of each procedure is [10,50 ]]The PCB processing order constraints on the chip mounters are randomly generated according to uniformly distributed randomly generated integers, and the delivery date of each PCB is related to the total processing time of the PCB
Figure GDA0003280952830000061
μ:U[1,1.1×max{1,n(m×r)}]，OjFor the set of all processes for workpiece j, the delay weight for each workpiece is [0,1) and random numbers are generated in a uniform distribution. The values of the objective functions obtained for different problem scales are given in table 2.
TABLE 2 objective function values obtained for different problem scales
n×m 10×5 10×10 20×5 20×10 30×10 50×8 100×6
TWT 0 0 0 10.6 21.3 20.6 31.2
While the present invention has been described in detail with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art.

Claims (1)

1. An optimized scheduling method for a printed circuit board surface mounting production line is characterized by comprising the following steps: establishing a disjunctive planning model and determining an optimized target through a scheduling process of a printed circuit board surface mounting production line, and optimizing the target by using an optimized scheduling method based on an improved sine and cosine algorithm; the scheduling problem of the printed circuit board surface mounting production line is represented by an analytic graph G (N, A, E, Re), an analytic planning model is established according to the description constrained in the analytic graph by the process number and the processing time of each PCB on each chip mounter and the processing sequence of each PCB on each chip mounter, and the optimization target is Total Weighted delay time (Total Weighted Tardiness, TWT); the disjunctive planning model is described as follows:
Figure FDA0003276029830000011
Figure FDA0003276029830000012
Figure FDA0003276029830000013
Figure FDA0003276029830000014
Figure FDA0003276029830000015
Figure FDA0003276029830000016
where N is a set of process nodes, N ═ O ═ coot {0} ═ {0,1,2, …, TO }, where O ═ {1,2, …, TO } is a set of all the processes, 0 is a virtual node, and TO ═ N × m × r is the total number of processes; u (O) is a set of last process steps for each PCB; the machining start time and the machining time in the virtual process 0 are set to zero; a is a conjunctionThe arc set is a unidirectional arc combining and drawing description of sequential constraint of the same PCB process route; u is a tail arc, describes that the last procedure of each PCB points to a virtual node 0 and is unidirectional; e is a disjunctive arc set which describes the front-back relation of the processing procedures on the same chip mounter, and the disjunctive arc orientation is undetermined and bidirectional before scheduling; re is a reentrant arc set proposed aiming at reentrant characteristics, describes the processing constraint of the same PCB on the same chip mounter and is unidirectional; siIs the starting time of step i, where s00; s is a vector formed by the starting processing time of all the procedures, namely a decision variable; p is a radical ofiA processing time of step i wherein p0＝0；μjThe last process of PCBj; (i)1,i2) For arcs with machining constraints, i.e. machining first1Post-processing i2；<i1,i2>The process is a disjunctive arc with undetermined direction, and the V-shaped cluster is a logic OR and describes the relation of the processes in the disjunctive arc; c. Ci、diAnd ωiRespectively the completion time, delivery date and delay weight of the PCB to which the working procedure i belongs; t isjFor the delay time, T, of PCBjj＝max{0,cj-dj}，
Figure FDA0003276029830000017
Delay time of the last procedure of the PCBj; the process of determining the orientation of the disjunctive arc is the solving process of the scheduling problem;
the optimized scheduling method based on the improved sine and cosine algorithm specifically comprises the following steps:
step1, population initialization: generating an initialization population by adopting a random method according to an operation-based coding mode until the number of initial solutions meets the requirement of population scale, and determining the optimal individual G _ best in the current population; wherein the population size is NP; let t be 1, a be 2, Max _ t be 1000;
step2, population updating: sequencing individuals of the printed circuit board surface mounting production line procedures in the population and converting the individuals based on real number coding into each other by adopting an RSOV reentrant-small-order-value rule; let r1 be a-t (a/Max _ t), update all individuals by the following formula, change the individuals based on real number encoding into the individuals based on process encoding, and evaluate;
Figure FDA0003276029830000021
wherein r2 ═ (2 π). times. Rand, r3 ═ 2 × Rand, r4 ═ Rand, Rand is a random number between 0 and 1,
Figure FDA0003276029830000022
i individuals in the population of the t generation;
step3, local search: determining the optimal individual G _ best in the current population, performing local search on the G _ best based on All _ Insert, and replacing the individual obtained by local search if the individual is better than the G _ best;
in the local search of the All _ Insert, a procedure is randomly selected, All the insertable positions are reached and evaluated, and the solution with the best target value is selected as the solution of the local search;
step4, judging termination conditions: if t is less than or equal to Max _ t, t is t +1, and Step2 is turned; otherwise, ending and outputting G _ best.
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CN113806997B (en) * 2020-06-15 2023-11-24 英业达科技有限公司 Method for producing printed circuit board assembly scheme
CN112188825B (en) * 2020-10-12 2021-09-24 合肥安迅精密技术有限公司 Multi-head chip mounter mounting efficiency optimization method and system based on bat algorithm
CN112561381B (en) * 2020-12-24 2023-09-01 哈尔滨工业大学（深圳） Scheduling decoding method for reentrant job shop
CN113905606B (en) * 2021-09-13 2022-09-30 中国地质大学（武汉） Chip mounter surface mounting scheduling model training method based on deep reinforcement learning
CN114859832B (en) * 2022-04-24 2023-04-11 合肥工业大学 T-beam production control method and system

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101261516A (en) * 2008-04-08 2008-09-10 山东大学 Oil refinery real time intelligent dynamically optimized scheduling modelling approach based on affair logic
CN102306336A (en) * 2011-06-10 2012-01-04 浙江大学 Service selecting frame based on cooperative filtration and QoS (Quality of Service) perception
CN105512753A (en) * 2015-11-30 2016-04-20 清华大学 Hybrid harmony search-based flexible job shop scheduling method
CN107807623A (en) * 2017-11-24 2018-03-16 大连理工大学 Flexible machine adds the Dynamic Scheduling method, system and the application in high ferro motor-car parts group flexible machine adds production line of production line

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101261516A (en) * 2008-04-08 2008-09-10 山东大学 Oil refinery real time intelligent dynamically optimized scheduling modelling approach based on affair logic
CN102306336A (en) * 2011-06-10 2012-01-04 浙江大学 Service selecting frame based on cooperative filtration and QoS (Quality of Service) perception
CN105512753A (en) * 2015-11-30 2016-04-20 清华大学 Hybrid harmony search-based flexible job shop scheduling method
CN107807623A (en) * 2017-11-24 2018-03-16 大连理工大学 Flexible machine adds the Dynamic Scheduling method, system and the application in high ferro motor-car parts group flexible machine adds production line of production line

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
"A hybrid differential evolution algorithm for the multi-objective reentrant job-shop scheduling problem";QIAN B;《10th IEEE International Conference on Control and Automation》;20131231;第485-489页 *
"A modified shifting bottleneck heuristic for the reentrant job shop scheduling problem with makespan minimization";TOPALOGLU S;《International Journal of Advanced Manufacturing Technology》;20091231;第781-794页 *
"A simulated annealing algorithm based on block properties for the job shop scheduling problem with total weighted tardiness objective";ZHANG R;《Computers & Operations Research》;20110531;第854-867页 *
"Flower pollination algorithm for global";YANG X S;《nternational Conference on Unconventional Computation and Natural Computation》;20121231;第240-249页 *

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