CN108989258B - Modular implementation structure and implementation method of PRACH baseband signal - Google Patents

Modular implementation structure and implementation method of PRACH baseband signal Download PDF

Info

Publication number
CN108989258B
CN108989258B CN201810768157.7A CN201810768157A CN108989258B CN 108989258 B CN108989258 B CN 108989258B CN 201810768157 A CN201810768157 A CN 201810768157A CN 108989258 B CN108989258 B CN 108989258B
Authority
CN
China
Prior art keywords
module
bit
output
bits
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810768157.7A
Other languages
Chinese (zh)
Other versions
CN108989258A (en
Inventor
舒勇
翟大海
王昌庆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fifth Research Institute Of Telecommunications Technology Co ltd
Original Assignee
Fifth Research Institute Of Telecommunications Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fifth Research Institute Of Telecommunications Technology Co ltd filed Critical Fifth Research Institute Of Telecommunications Technology Co ltd
Priority to CN201810768157.7A priority Critical patent/CN108989258B/en
Publication of CN108989258A publication Critical patent/CN108989258A/en
Application granted granted Critical
Publication of CN108989258B publication Critical patent/CN108989258B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2626—Arrangements specific to the transmitter only
    • H04L27/2627—Modulators
    • H04L27/2634—Inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators in combination with other circuits for modulation
    • H04L27/2636—Inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators in combination with other circuits for modulation with FFT or DFT modulators, e.g. standard single-carrier frequency-division multiple access [SC-FDMA] transmitter or DFT spread orthogonal frequency division multiplexing [DFT-SOFDM]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2626—Arrangements specific to the transmitter only
    • H04L27/2627—Modulators
    • H04L27/2628—Inverse Fourier transform modulators, e.g. inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators

Landscapes

  • Physics & Mathematics (AREA)
  • Discrete Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

The invention discloses a module realization structure and a realization method of PRACH baseband signals, the structure is a field programmable gate array FPGA structure and is used for realizing the module calculation of 24576 by the product of two 15-bit unsigned integers x and y, the structure is characterized by comprising a first bit interceptor and a second bit interceptor which respectively intercept x and y, an S201 module, an S202 module, an S203 module, an S204 module, an S205 module, an S206 module, an S207 module, an S208 module, an S209 module, an S210 module, an adder, a subtracter, a judger and a selector, wherein the first bit interceptor and the second bit interceptor have the same structure and respectively comprise 10 sub-bit interceptors. According to the invention, the module calculation is simplified through layer-by-layer truncation, and further the calculation of IDFT in the signal generation process is simplified, so that the whole signal generation process is simplified.

Description

Modular implementation structure and implementation method of PRACH baseband signal
Technical Field
The present invention relates to the field of communications, and in particular, to a structure and a method for implementing modulo of a PRACH (Physical Random Access Channel) baseband signal.
Background
In the LTE protocol, a time-continuous random access signal s (t) on a PRACH channel is defined by:
Figure RE-GDA0001755350690000011
wherein T represents time, 0 ≦ T < TSEQ+TCP，TSEQ、TCPValues are related to preamble formats, see table 1. k is a radical of0Indicating the RB start position occupied by PRACH, K indicating the RB index within the occupied bandwidth, K indicating the subcarrier spacing difference between the random access preamble and the uplink data βPRACHDenotes PRACH signal transmission power coefficient, n denotes ZC sequence index, TCPDenotes the cyclic prefix length, fRAIndicating the random access sub-carrier spacing,
Figure RE-GDA0001755350690000012
indicating the frequency domain position, N, of the random access preamble in a resource blockZCThe length of the ZC sequence is shown, the value of which is related to the preamble format and is shown in Table 2.
Table 1 random access preamble parameters
Figure RE-GDA0001755350690000013
Table 2 random access parameters
Figure RE-GDA0001755350690000014
ZC sequences are defined as follows:
xu,v(n)＝xu((n+Cv)modNZC) (2)
Figure RE-GDA0001755350690000015
Cvthe time domain offset is a variable related to v when the preamble is calculated, and is considered as an independent variable with the value range of 0-Cv≤NZC-1。
Discrete form of baseband signal
In equation (1), β is omittedPRACHAnd setting the sampling time as Ts1/30.72MHz, t is iTsInto s (t), have
Figure RE-GDA0001755350690000021
Wherein T isCP＝NCPTs。
Format 0-3
Will be Δ fRASubstitution in equation (2) at 1250 and omitting TsIs provided with
Figure RE-GDA0001755350690000022
Wherein
Figure RE-GDA0001755350690000023
Equation (6) is a DFT transform.
Format 4
Will be Δ fRASubstitution into formula (2) at 7500 and omission of TsThe method comprises the following steps of (1) preparing,
Figure RE-GDA0001755350690000031
wherein
Figure RE-GDA0001755350690000032
Equation (8) is a DFT transform.
As can be seen from equations (5) and (7), the discrete signal baseband signal is divided into DFT conversion, IDFT conversion, carrier shifting, and CP adding processes, and the generation flow is shown in fig. 1. In fig. 1, for formats 0-3, M ═ 839 and N ═ 24576, one 839 point DFT transform and one 24576 point IDFT transform are required to complete PRACH baseband signal generation. For format 4, M139 and N4096, completing the PRACH baseband signal generation requires one 139-point DFT transform and one 4096-point IDFT transform.
The DFT/IDFT transform is a very complex operation, the complex number multiplication operation amount is directly proportional to the square of the point number when formula transform is directly used, so that the DFT/IDFT transform of the point number is not suitable for direct calculation, particularly the DFT/IDFT transform of the format 0-3, the calculation amount of the DFT/IDFT transform can be greatly reduced by using a fast algorithm (cooley-tukey) of the DFT/IDFT transform, but the cooley-tukey algorithm is a fast algorithm of the general signal DFT/IDFT transform, and if the algorithm is directly used for generating a baseband signal of a PRACH channel, the particularity of a ZC sequence is not fully utilized; moreover, the DFT operation is a prime point DFT operation (839 points or 139 points), and the decomposition is not suitable to be carried out by using a Cooley-tukey (Cooley-tukey) algorithm; the IDFT is 24576 points in the formats 0-3 and 4096 points in the format 4, and particularly is a large-point number IDFT operation in the formats 0-3, and still has a large operation amount by using a Cooley-tukey (Cooley-tukey) algorithm. In the format 0-3, the IDFT of the 24576 point is subjected to modulo of 24576, and the resource consumption of the existing implementation structure is large.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the problems in the prior art, the invention provides a structure and a method for realizing the modulus of a PRACH baseband signal, which simplify the modulus calculation through layer-by-layer truncation, further simplify the calculation of IDFT in the signal generation process, and further simplify the whole signal generation process.
The invention provides a modulus realization structure of a PRACH baseband signal, which is a Field Programmable Gate Array (FPGA) structure and is used for realizing the modulus of a product of two 15-bit unsigned integers x and y on 24576, and comprises a first bit interceptor and a second bit interceptor which respectively intercept x and y, an S201 module, an S202 module, an S203 module, an S204 module, an S205 module, an S206 module, an S207 module, an S208 module, an S209 module, an S210 module, an adder, a subtracter, a judger and a selector;
the truncator I and the truncator II have the same structure and comprise a sub truncator I, a sub truncator II, a sub truncator III, a sub truncator IV, a sub truncator V, a sub truncator VI, a sub truncator seven, a sub truncator eight, a sub truncator nine and a sub truncator ten, wherein the sub truncator I and the sub truncator II are respectively used for truncating the high 2 bits and the low 13 bits of x or y and keeping the high and low bit sequence unchanged as unsigned integers of x1 and x2 or y1 and y 2; the third sub-truncator and the fourth sub-truncator are respectively used for truncating the upper 6 bits and the lower 7 bits of the x2 or the y2 and keeping the order of the upper bits and the lower bits unchanged as unsigned integers of x21 and x22 or y21 and y 22; the fifth sub-truncator and the sixth sub-truncator are respectively used for truncating the upper 3 bits and the lower 3 bits of the x21 or the y21 and keeping the order of the upper bits and the lower bits unchanged as unsigned integers x211 and x212 or y211 and y 212; the seven sub-truncator and the eight sub-truncator are respectively used for truncating the upper 1 bit and the lower 6 bit of x22 or y22 and keeping the order of the upper bit and the lower bit unchanged as an unsigned integer x221 and x222 or y221 and y 222; the nine sub-truncator and the nine sub-truncator are respectively used for truncating the upper 3 bits and the lower 3 bits of the x222 or the y222 and keeping the sequence of the upper bits and the lower bits unchanged as unsigned integers x2221 and x2222 or y2221 and y 2222;
the S201 module is used for processing x1 and x2 and outputting x1mod3 and (x1+ x2) mod 3; the S202 module is used for processing y1 and y2 and outputting y1mod3 and (y1+ y2) mod 3; the S203 module is used for processing x21 and x221 and outputting x21mod3 and (x21+ x221) mod 3; the S204 module is used for processing y21 and y221 and outputting y21mod3 and (y21+ y221) mod 3; the S205 module is configured to process x222, x221, y221, and y222 and output p23 ═ x22 ═ y 22;
the S206 module is configured to process outputs of the S201 module and the S202 module and output p1 ═ (x1mod3 ═ (y1+ y2) mod3+ y1mod3 (x1+ x2) mod3) mod 3; the S207 module is configured to process the outputs of the S203 module and the S204 module and output p21+ p221 ═ (x21mod3 × (y21+ y221) mod3+ y21mod3 × (x21+ x221) mod3) mod 3; the S208 module is configured to process x211, x212, x2221, x2222, y211, y212, y2221, and y2222 and output m ═ x211 × y2222+ x212 × 2221+ y211 × 2222+ y212 × x2221, x211 × y2221+ y211 × 2221, and 128 (x212 × y2222+ y212 × 2222), where the first two outputs are inputs of the S209 module; the S209 module is configured to process the first two outputs of the S208 module and output x211 × y2221+ y211 × x2221+ m1 and 1024 × m 2; the S210 module is configured to process the outputs of the S206 and S207 modules and the outputs of the S209 module x211 × y2221+ y211 × 2221+ m1 and output 8192 × mod3 (p1+ p21+ p221+ x211 × y2221+ y211 × 2221+ m 1);
the adder is used for summing the outputs of the S210 module and the S205 module and the outputs 1024 × m2 of the S209 module and the outputs 128 × x2222 of the S208 module and outputting the sum as q; the subtracter is used for subtracting 24576 from q; the judger is used for judging whether the output of the subtracter is greater than or equal to 0, if so, the output is 1, otherwise, the output is 0; the top end input of the selector is the output of the judger, the first number input and the second number input are the output and the input of the subtracter respectively, the top end input value can only be 1 or 0, the first number is output when the top end input value is 1, and the second number is output when the top end input value is 0.
Further, the module S201 and the module S202 have the same structure, and include 4 adders, 12 truncators, and 2 modulo modules; the modulus calculating module comprises a subtracter, a judger and a selector, wherein the subtracter is used for subtracting 3 from the input of the modulus calculating module, the judger is used for judging whether the output of the subtracter is greater than or equal to 0, if yes, the output is 1, otherwise, the output is 0, the top end input of the selector is the output of the judger, the first number input and the second number input are respectively the output and the input of the subtracter, the top end input value can only be 1 or 0, the first number is output when the top end input value is 1, and the second number is output when the top end input value is 0;
the input of the 1 st to 7 th bit truncators are the output of the 1 st adder, the output of the 1 st bit truncators is the input of the 2 nd adder, and the 1 st bit to the 13 th bit, the 10 th to the 11 th bit, the 8 th to the 9 th bit, the 6 th to the 7 th bit, the 4 th to the 5 th bit, the 2 nd to the 3 rd bit and the 0 th to the 1 th bit of the output number of the 1 st adder are respectively intercepted and kept unchanged in the high-low order to be used as an unsigned integer;
the 8 th to 10 th bit truncators have the inputs of the 2 nd adder and the outputs of the 2 nd bit truncators are used as the inputs of the 3 rd adder, and are respectively used for truncating the 4 th bit, the 2 nd to 3 rd bit and the 0 th to 1 th bit of the output number of the 2 nd adder and keeping the high-low order unchanged to be used as an unsigned integer;
the inputs of 11 th to 12 th truncators are all the outputs of the 3 rd adder, the outputs of the truncators are all the inputs of the 4 th adder, and the truncators are respectively used for truncating the 2 nd bit and the 0 th to 1 th bits of the output number of the 3 rd adder and keeping the high-low order unchanged to be used as an unsigned integer;
the input of its 1 st modulo block is x1 or y1, and the input of its 2 nd modulo block is the output of its 4 th adder.
Further, the module S203 and the module S204 have the same structure, and include 5 truncators, 3 adders and 2 modulo modules;
the input of the 1 st to 3 rd truncators is x21 or y21, the output of the 1 st truncators is used as the input of the 1 st adder, and the 1 st to 3 rd bits, the 4 th to 5 th bits and the 0 th to 1 th bits of x21 or y21 are respectively truncated and kept unchanged in high and low order to form an unsigned integer; the 4 th-5 th bit truncator has the input of the 1 st adder and the output of the 1 st adder as the input of the 2 nd adder, and is used for truncating the 2 nd to 3 rd bits and the 0 th to 1 th bits of the output number of the 1 st adder and keeping the high and low order unchanged as an unsigned integer;
the 3 rd adder is used for summing the output of the 2 nd adder with x221 or y 221; the inputs of its 2 modulo modules are the outputs of the 2 nd and 3 rd adders respectively.
Further, the S206 module and the S207 module have the same structure, and each includes 2 multipliers, 3 modulo modules, and 1 adder;
the outputs of its 2 multipliers are respectively used as the inputs of 2 modulo modules, the outputs of these 2 modulo modules are all used as the input of its adder, and the output of the adder is used as the input of its 3 rd modulo module.
Further, the S209 module includes 12 truncators, 3 adders, 1 multiplier and 1 modulo module;
the inputs of the 1 st to 3 rd truncators are x211 x2221+ y211 x2221 and are respectively used for truncating the 4 th to 5 th bits, the 2 nd to 3 rd bits and the 0 th to 1 th bits of the input number and keeping the high and low order unchanged as an unsigned integer; the 4 th to 7 th bit truncators are used for truncating and keeping the order of the 7 th bit, the 5 th to 6 th bit, the 3 rd to 4 th bit and the 0 th to 2 nd bit of the input number m unchanged as an unsigned integer; the outputs of the 1 st to 6 th truncators are used as the input of the 1 st adder; the output of the 7 th truncator is used as the input of a multiplier which is used for multiplying the input of the multiplier by 1024;
the inputs of 8 th to 10 th truncators are all the outputs of the 1 st adder, the outputs of the truncators are all the inputs of the 2 nd adder, and the truncators are respectively used for truncating the 4 th bit, the 2 nd to 3 rd bit and the 0 th to 1 st bit of the output number of the 1 st adder and keeping the high-low order unchanged to be used as an unsigned integer;
the inputs of 11 th to 12 th bit truncators are all the outputs of the 2 nd adder, the outputs of the truncators are all the inputs of the 3 rd adder, and the truncators are respectively used for truncating the 2 nd bit and the 0 th to 1 th bits of the output number of the 2 th adder and keeping the high-low order unchanged to be used as an unsigned integer;
the input of the modulo block is the output of the 3 rd adder.
Further, the S210 module includes 2 truncators, 2 adders, 1 modulo module and 1 multiplier;
the input of 2 truncators is the output of the 1 st adder, the output of the 2 truncators is used as the input of the 2 nd adder, and the 2 nd to 3 rd bits and the 0 th to 1 th bits of the output number of the 1 st adder are respectively used for truncating and keeping the high-low order unchanged to be used as an unsigned integer;
the input of the modulus module is the output of the 2 nd adder; which multiplier is used to multiply the output of the modulo block by 8192.
Further, the S208 module includes an S301 module and an S302 module, the inputs of which are y2221 and x2221, respectively, and the two modules have the same structure and each include 2 truncators, 1 adder, and 1 modulo module;
the inputs of 2 truncators are y2221 or x2221, the outputs of the 2 truncators are used as the inputs of an adder, and the 2 nd bit and the 0 th bit to the 1 th bit of the input number of y2221 or x2221 are respectively intercepted and kept unchanged in high and low order to be used as an unsigned integer; the input of the modulo module is the output of the adder.
In another aspect of the present invention, a method for implementing modulo of a PRACH baseband signal is provided, where the method is used to implement modulo of a product of two 15-bit unsigned integers x and y, and is implemented by a field programmable gate array FPGA hardware platform, and includes:
the method for truncating by the truncator I and the truncator II is the same as that for truncating by the truncator I and the truncator Y respectively, and comprises the following steps: intercepting the upper 2 bits and the lower 13 bits of the input number x or y of the input number by a first sub-interceptor and a second sub-interceptor and keeping the sequence of the upper bits and the lower bits unchanged as unsigned integers x1 and x2 or y1 and y 2; intercepting the upper 6 bits and the lower 7 bits of x2 or y2 by a third sub-interceptor and a fourth sub-interceptor and keeping the sequence of the upper bits and the lower bits unchanged as unsigned integers of x21 and x22 or y21 and y 22; intercepting the upper 3 bits and the lower 3 bits of x21 or y21 by a fifth sub-interceptor and a sixth sub-interceptor and keeping the order of the upper bits and the lower bits unchanged as an unsigned integer of x211 and x212 or y211 and y 212; intercepting the upper 1 bit and the lower 6 bits of x22 or y22 by a seven sub-truncator and an eight sub-truncator and keeping the order of the upper bits and the lower bits unchanged as an unsigned integer x221 and x222 or y221 and y 222; intercepting the upper 3 bits and the lower 3 bits of x222 or y222 by a nine-bit truncator and a ten-bit truncator and keeping the sequence of the upper bits and the lower bits unchanged as an unsigned integer x2221 and x2222 or y2221 and y 2222;
processing x1 and x2 by the S201 module and outputting x1mod3 and (x1+ x2) mod 3; processing y1 and y2 by the S202 module and outputting y1mod3 and (y1+ y2) mod 3; processing x21 and x221 by the S203 module and outputting x21mod3 and (x21+ x221) mod 3; processing y21 and y221 through the S204 module and outputting y21mod3 and (y21+ y221) mod 3; processing x222, x221, y221 and y222 by the S205 module and outputting p23 ═ x22 ═ y 22;
processing, by the S206 module, the outputs of the S201 and S202 modules and outputting p1 (x1mod3 (y1+ y2) mod3+ y1mod3 (x1+ x2) mod3) mod 3; processing the outputs of the S203 and S204 modules by the S207 module and outputting p21+ p221 ═ (x21mod3 × (y21+ y221) mod3+ y21mod3 × (x21+ x221) mod3) mod 3; processing x211, x212, x2221, x2222, y211, y212, y2221 and y2222 by the S208 module and outputting m ═ x211 × y2222+ x212 × 2221+ y211 × 2222+ y212 × x2221, x211 × y2221+ y211 × 2221 and 128 (x212 × y2222+ y212 × 2222), and taking the first two outputs as the inputs of the S209 module; processing the first two outputs of the S208 module by the S209 module and outputting x211 x2221+ y211 x2221+ m1 and 1024 x m 2; processing the outputs of the S206 and S207 modules and the output of the S209 module x211 x2221+ y211 x2221+ m1 by the S210 module and outputting 8192 (p1+ p21+ p221+ x211 y2221+ y211 x2221+ m1) mod 3;
summing the outputs of the S210 and S205 modules and the outputs 1024 × m2 of the S209 and 128 × x2222 of the S208 module by an adder and outputting q; subtracting 24576 from q by a subtractor; judging whether the output of the subtracter is greater than or equal to 0 through a judger, if so, outputting to be 1, otherwise, outputting to be 0, and taking the output of the judger as the top end input of a selector; the output of the subtracter is output when the top input of the selector is 1, and the input of the subtracter is output when the top input is 0.
Compared with the prior art, the invention needs 11 unsigned integer multiplications and some simple operations such as truncation, addition (subtraction), comparison, selection and the like, and only one multiplication in 11 multiplications is 6 bits by 6 bits multiplication, and the other 10 multiplications are 2 bits by 2 bits or 3 bits by 3 bits or 2 bits by 3 bits, so that the resource consumption is less when the FPGA is implemented, and the whole signal generation process is simplified.
Drawings
The invention will now be described, by way of example, with reference to the accompanying drawings, in which:
FIG. 1 is a flow chart of baseband signal generation in the background of the invention;
FIG. 2 is a schematic diagram of a modulo structure according to an embodiment of the present invention;
fig. 3 is a structural diagram of an implementation of an S201 module and an S202 module in a modular structure according to an embodiment of the present invention;
fig. 4 is a structural diagram of an implementation of the S203 module and the S204 module in the modular structure according to the embodiment of the present invention;
fig. 5 is a structural diagram of an implementation of an S205 module in a modular structure according to an embodiment of the present invention;
fig. 6 is a structural diagram of an implementation of the S206 module and the S207 module in the modular structure according to the embodiment of the present invention;
fig. 7 is a structural diagram of an implementation of the S208 module in the modular structure according to the embodiment of the present invention;
fig. 8 is a structural diagram of an implementation of an S209 module in a modular structure according to an embodiment of the present invention;
fig. 9 is a structural diagram of an implementation of an S210 module in a modular structure according to an embodiment of the present invention;
fig. 10 is a structural diagram of an implementation of the S301 module and the S302 module in the S208 module according to the embodiment of the present invention.
Detailed Description
All of the features disclosed in this specification, or all of the steps in any method or process so disclosed, may be combined in any combination, except combinations of features and/or steps that are mutually exclusive.
Any feature disclosed in this specification may be replaced by alternative features serving equivalent or similar purposes, unless expressly stated otherwise. That is, unless expressly stated otherwise, each feature is only an example of a generic series of equivalent or similar features.
The modular algorithm principle and the implementation structure of the invention are specifically as follows.
The modulo structure of the present invention represents the modulo operation of 24576 after multiplication of two unsigned integers. The invention provides an algorithm which is simple and suitable for being realized on an FPGA. Let the two inputs be x, y, respectively, and the output be p, then
p＝(x*y)mod24576 (21)
In the LTE system, x, y, and p can all be represented by 15-bit width, and x, y is represented by truncation as follows:
x＝8192*x1+x2,y＝8192*y1+y2 (22)
x2＝128*x21+x22,y2＝128*y21+y22 (23)
x21＝8*x211+x212,y21＝8*y211+y212 (24)
x22＝64*x221+x222,y22＝64*y221+y222 (25)
x222＝8*x2221+x2222,y222＝8*y2221+y2222 (26)
wherein
x1, x2, y1, y2, x21, x22, y21, y22, x211, x212, y211, y212, x221, x222, y221, y222, x2221, x2222, y2221 and y2222 are unsigned integers, and their bit widths and meanings are shown in Table 3
TABLE 3 parameter bit widths
Parameter(s) Bit width Of significance
x1 2 x is high by 2
x2 13 x lower 13 bits
y1 2 High y2 position
y2 13 y lower 13 bits
x21 6 x2 high 6 position
x22 7 x2 low 7 bits
y21 6 High 6 position of y2
y22 7 Low 7 bits of y2
x211
3 x21 high 3 position
x212
3 x21 low 3 bits
y211 3 High 3 position of y21
y212 3 Low 3 position of y21
x221 1 x22 high 1 position
x222 6 x22 low 6 bits
y221 1 High 1 position of y22
y222 6 Low 6 bits of y22
x2221 3 x222 high 3 bit
x2222 3 x222 lower 3 bits
y2221 3 High 3 bits of y222
y2222 3 Low 3 bits of y222
Substituting equations (22) through (26) into equation (21) is:
p＝(x*y)mod24576
＝((8192*x1+x2)*(8192*y1+y2))mod24576
＝((x1*y1*2+x1*y2+x2*y1)mod3*8192+x2*y2)mod24576
＝(8192*p1+p2)mod24576 (27)
wherein
p1＝(x1*y1*2+x1*y2+x2*y1)mod3
＝(x1 mod3*(y1+y2)mod3+y1 mod3*(x1+x2)mod3)mod3 (28)
p2＝(x2*y2)mod24576
＝(128*x21+x22)*(128*y21+y22)mod24576
＝(8192*p21+128*p22+p23)mod24576 (29)
Wherein p21 ═ (2 × x21 × 21) mod3, p22 ═ (x21 × y22+ y21 × 22) mod192, and p23 ═ x22 × y22
p22＝(x21*y22+y21*x22)mod192
＝(x21*(64*y221+y222)+y21*(64*x221+x222))mod192
＝(64*p221+p222)mod192 (30)
Wherein p221 (x21 y221+ y21 x221) mod3, p222 (x21 y222+ y21 x222) mod192
p222＝(x21*y222+y21*x222)mod192
＝((8*x211+x212)*(8*y2221+y2222)+(8*y211+y212)*(8*x2221+x2222))mod192
＝(64*(x211*y2221+y211*x2221)mod3+ 8*(x211*y2222+x212*y2221+y211*x2222+y212*x2221)+ x212*y2222+y212*x2222)mod192 (31)
Thus, it is possible to provide
p＝(x*y)mod24576
＝(p1*8192+p2)mod24576
＝(p1*8192+8192*p21+128*p22+p23)mod24576
＝(p1*8192+8192*p21+128*((64*p221+p222)mod192)+p23)mod24576
＝(8192*(p1+p21)mod3+8192*p221mod3+128*p222mod192+p23)mod24576
＝(8192*(p1+p21+p221+x211*y2221+y211*x2221)mod3+ 1024*(x211*y2222+x212*y2221+y211*x2222+y212*x2221)mod24+128*(x212*y2222+y212*x2222)mod192+p23)mod24576 (32)
Let m ═ x211 × y2222+ x212 × 2221+ y211 × 2222+ y212 × 2221 ═ 8 × m1+ m2, m is an 8-bit unsigned integer, m1 is a 5-bit unsigned integer, m2 is a 3-bit unsigned integer, then
mmod24＝(8*m1+m2)mod24＝8*m1mod3+m2 (33)
Is combined with
p＝(x*y)mod24576
＝(p1*8192+p2)mod24576
＝(p1*8192+8192*p21+128*p22+p23)mod24576
＝(p1*8192+8192*p21+128*((64*p221+p222)mod192)+p23)mod24576
＝(8192*(p1+p21)mod3+8192*p221mod3+128*p222mod192+p23)mod24576
＝(8192*(p1+p21+p221+x211*y2221+y211*x2221+m1)mod3+ 1024*m2+ 128*(x212*y2222+y212*x2222)+ p23)mod24576
＝qmod24576 (34)
Wherein
q＝(8192*(p1+p21+p221+x211*y2221+y211*x2221+m1)mod3+ 1024*m2+128*(x212*y2222+y212*x2222)+p23 (35)
Since q is 40065 as shown by the formula (35), the compound
Figure RE-GDA0001755350690000111
Therefore, only the q value needs to be calculated, and the p value can be simply calculated. In the q value calculation process, except for the mod3 operation, common addition and multiplication operations are performed. The algorithm principle for implementation of mod3 operations on an FPGA is described below.
Without loss of generality, let w ═ (a × u + b × v) mod3, and a, u, b, v are all 8-bit unsigned integers, a ═ { a ═ b } v0,a1,a2,a3,a4,a5,a6,a7}，a0,a1,a2,a3,a4,a5,a6,a7Respectively representing the lowest bit and the second lowest bit of a. Denote a as
a＝a1+4*a2+16*a3+64*a4 (37)
Then a1 ═ a0,a1},a2＝{a2,a3}，a3＝{a4,a5}，a4＝{a6,a7}。
a mod3 (a1+4 a2+16 a3+64 a4) mod3 (a1+ a2+ a3+ a4) mod3, and a1+ a2+ a3+ a4 is regarded as a 4-bit unsigned integer, and amod3 can be finally calculated by repeatedly using formula (37). Similarly, values for bmod3, umod3, vmod3, (amod3 x umod3) mod3, (bmod3 x vmod3) mod3 can be calculated.
Then
Figure RE-GDA0001755350690000121
Where k ═ mod3+ (bmod3 × vmod3) mod3 (amod3 × umod 3).
As shown in fig. 2, the same bit-truncating process is performed on x and y by a bit-truncator, and then corresponding data is processed by an S201 module, an S202 module, an S203 module, an S204 module, an S205 module, an S206 module, an S207 module, an S208 module, an S209 module, an S210 module, an adder, a subtractor, a judger, and a selector. The truncation processing of x and y requires 10 truncators, the 1 st of the 10 truncators is used for truncating the 13 th bit to the 14 th bit of the input number and keeping the high and low order unchanged as an unsigned integer, and the rest truncators are analogized. The selector has three inputs, the top input value can only be 1 or 0, the first number is output when the value is 1, and the second number is output when the value is 0. The implementation structures of the S201 module, the S202 module, the S203 module, the S204 module, the S205 module, the S206 module, the S207 module, the S208 module, the S209 module and the S210 module are respectively shown in fig. 3-9. The truncators and selectors etc. in fig. 3-10 are similar to the corresponding modules described above.
The S201 module and the S202 module have the same structure, as shown in fig. 3, and include 4 adders, 12 truncators, and 2 modulo modules; the modulus calculating module comprises a subtracter, a judger and a selector, wherein the subtracter is used for subtracting 3 from the input of the modulus calculating module, the judger is used for judging whether the output of the subtracter is greater than or equal to 0, if yes, the output is 1, otherwise, the output is 0, the top end input of the selector is the output of the judger, the first number input and the second number input are respectively the output and the input of the subtracter, the top end input value can only be 1 or 0, the first number is output when the top end input value is 1, and the second number is output when the top end input value is 0; the input of the 1 st to 7 th bit truncators are the output of the 1 st adder, the output of the 1 st bit truncators is the input of the 2 nd adder, and the 1 st bit to the 13 th bit, the 10 th to the 11 th bit, the 8 th to the 9 th bit, the 6 th to the 7 th bit, the 4 th to the 5 th bit, the 2 nd to the 3 rd bit and the 0 th to the 1 th bit of the output number of the 1 st adder are respectively intercepted and kept unchanged in the high-low order to be used as an unsigned integer; the 8 th to 10 th bit truncators have the inputs of the 2 nd adder and the outputs of the 2 nd bit truncators are used as the inputs of the 3 rd adder, and are respectively used for truncating the 4 th bit, the 2 nd to 3 rd bit and the 0 th to 1 th bit of the output number of the 2 nd adder and keeping the high-low order unchanged to be used as an unsigned integer; the inputs of 11 th to 12 th truncators are all the outputs of the 3 rd adder, the outputs of the truncators are all the inputs of the 4 th adder, and the truncators are respectively used for truncating the 2 nd bit and the 0 th to 1 th bits of the output number of the 3 rd adder and keeping the high-low order unchanged to be used as an unsigned integer; the input of its 1 st modulo block is x1 or y1, and the input of its 2 nd modulo block is the output of its 4 th adder.
The S203 module and the S204 module have the same structure, as shown in fig. 4, and include 5 truncators, 3 adders, and 2 modulo modules; the input of the 1 st to 3 rd truncators is x21 or y21, the output of the 1 st truncators is used as the input of the 1 st adder, and the 1 st to 3 rd bits, the 4 th to 5 th bits and the 0 th to 1 th bits of x21 or y21 are respectively truncated and kept unchanged in high and low order to form an unsigned integer; the 4 th-5 th bit truncator has the input of the 1 st adder and the output of the 1 st adder as the input of the 2 nd adder, and is used for truncating the 2 nd to 3 rd bits and the 0 th to 1 th bits of the output number of the 1 st adder and keeping the high and low order unchanged as an unsigned integer; the 3 rd adder is used for summing the output of the 2 nd adder with x221 or y 221; the inputs of its 2 modulo modules are the outputs of the 2 nd and 3 rd adders respectively.
As shown in fig. 5, the S205 module includes 1 and module, 2 selectors, 3 multipliers and 1 adder, the selectors of which are similar to the selectors described above.
The S206 module and the S207 module have the same structure, and as shown in fig. 6, each module includes 2 multipliers, 3 modulo modules, and 1 adder; the outputs of its 2 multipliers are respectively used as the inputs of 2 modulo modules, the outputs of these 2 modulo modules are all used as the input of its adder, and the output of the adder is used as the input of its 3 rd modulo module.
As shown in fig. 7, the S208 module only needs 9 multipliers, 3 adders, and the S301 module and the S302 module, and the implementation structures of the S301 module and the S302 module are shown in fig. 10. The S301 module and the S302 module respectively comprise 2 truncators, 1 adder and 1 modulus module; the inputs of 2 truncators are y2221 or x2221, the outputs of the 2 truncators are used as the inputs of an adder, and the 2 nd bit and the 0 th bit to the 1 th bit of the input number of y2221 or x2221 are respectively intercepted and kept unchanged in high and low order to be used as an unsigned integer; the input of the modulo module is the output of the adder.
As shown in fig. 8, the S209 module includes 12 truncators, 3 adders, 1 multiplier, and 1 modulo module; the inputs of the 1 st to 3 rd truncators are x211 x2221+ y211 x2221 and are respectively used for truncating the 4 th to 5 th bits, the 2 nd to 3 rd bits and the 0 th to 1 th bits of the input number and keeping the high and low order unchanged as an unsigned integer; the 4 th to 7 th bit truncators are used for truncating and keeping the order of the 7 th bit, the 5 th to 6 th bit, the 3 rd to 4 th bit and the 0 th to 2 nd bit of the input number m unchanged as an unsigned integer; the outputs of the 1 st to 6 th truncators are used as the input of the 1 st adder; the output of the 7 th truncator is used as the input of a multiplier which is used for multiplying the input of the multiplier by 1024; the inputs of 8 th to 10 th truncators are all the outputs of the 1 st adder, the outputs of the truncators are all the inputs of the 2 nd adder, and the truncators are respectively used for truncating the 4 th bit, the 2 nd to 3 rd bit and the 0 th to 1 st bit of the output number of the 1 st adder and keeping the high-low order unchanged to be used as an unsigned integer; the inputs of 11 th to 12 th bit truncators are all the outputs of the 2 nd adder, the outputs of the truncators are all the inputs of the 3 rd adder, and the truncators are respectively used for truncating the 2 nd bit and the 0 th to 1 th bits of the output number of the 2 th adder and keeping the high-low order unchanged to be used as an unsigned integer; the input of the modulo block is the output of the 3 rd adder.
As shown in fig. 9, the S210 module includes 2 truncators, 2 adders, 1 modulo module, and 1 multiplier; the input of 2 truncators is the output of the 1 st adder, the output of the 2 truncators is used as the input of the 2 nd adder, and the 2 nd to 3 rd bits and the 0 th to 1 th bits of the output number of the 1 st adder are respectively used for truncating and keeping the high-low order unchanged to be used as an unsigned integer; the input of the modulus module is the output of the 2 nd adder; which multiplier is used to multiply the output of the modulo block by 8192.
The invention is not limited to the foregoing embodiments. The invention extends to any novel feature or any novel combination of features disclosed in this specification and any novel method or process steps or any novel combination of features disclosed.

Claims (8)

1. A modulus realization device of PRACH baseband signals is of a Field Programmable Gate Array (FPGA) structure and is used for realizing the modulus of a product of two 15-bit unsigned integers x and y on 24576, and is characterized by comprising a first bit interceptor and a second bit interceptor which respectively intercept x and y, an S201 module, an S202 module, an S203 module, an S204 module, an S205 module, an S206 module, an S207 module, an S208 module, an S209 module, an S210 module, an adder, a subtracter, a judger and a selector;
the truncator I and the truncator II have the same structure and comprise a sub truncator I, a sub truncator II, a sub truncator III, a sub truncator IV, a sub truncator V, a sub truncator VI, a sub truncator seven, a sub truncator eight, a sub truncator nine and a sub truncator ten, wherein the sub truncator I and the sub truncator II are respectively used for truncating the high 2 bits and the low 13 bits of x or y and keeping the high and low bit sequence unchanged as unsigned integers of x1 and x2 or y1 and y 2; the third sub-truncator and the fourth sub-truncator are respectively used for truncating the upper 6 bits and the lower 7 bits of the x2 or the y2 and keeping the order of the upper bits and the lower bits unchanged as unsigned integers of x21 and x22 or y21 and y 22; the fifth sub-truncator and the sixth sub-truncator are respectively used for truncating the upper 3 bits and the lower 3 bits of the x21 or the y21 and keeping the order of the upper bits and the lower bits unchanged as unsigned integers x211 and x212 or y211 and y 212; the seven sub-truncator and the eight sub-truncator are respectively used for truncating the upper 1 bit and the lower 6 bit of x22 or y22 and keeping the order of the upper bit and the lower bit unchanged as an unsigned integer x221 and x222 or y221 and y 222; the nine sub-truncator and the nine sub-truncator are respectively used for truncating the upper 3 bits and the lower 3 bits of the x222 or the y222 and keeping the sequence of the upper bits and the lower bits unchanged as unsigned integers x2221 and x2222 or y2221 and y 2222;
the S201 module is used for processing x1 and x2 and outputting x1mod3 and (x1+ x2) mod 3; the S202 module is used for processing y1 and y2 and outputting y1mod3 and (y1+ y2) mod 3; the S203 module is used for processing x21 and x221 and outputting x21mod3 and (x21+ x221) mod 3; the S204 module is used for processing y21 and y221 and outputting y21mod3 and (y21+ y221) mod 3; the S205 module is configured to process x222, x221, y221, and y222 and output p23 ═ x22 ═ y 22;
the S206 module is configured to process outputs of the S201 module and the S202 module and output p1 ═ (x1mod3 ═ (y1+ y2) mod3+ y1mod3 (x1+ x2) mod3) mod 3; the S207 module is configured to process the outputs of the S203 module and the S204 module and output p21+ p221 ═ (x21mod3 × (y21+ y221) mod3+ y21mod3 × (x21+ x221) mod3) mod 3; the S208 module is configured to process x211, x212, x2221, x2222, y211, y212, y2221, and y2222 and output m ═ x211 × y2222+ x212 × 2221+ y211 × 2222+ y212 × x2221, x211 × y2221+ y211 × 2221, and 128 (x212 × y2222+ y212 × 2222), where the first two outputs are inputs of the S209 module; the S209 module is configured to process the first two outputs of the S208 module and output x211 × y2221+ y211 × x2221+ m1 and 1024 × m 2; the S210 module is configured to process the outputs of the S206 and S207 modules and the outputs of the S209 module x211 × y2221+ y211 × 2221+ m1 and output 8192 × mod3 (p1+ p21+ p221+ x211 × y2221+ y211 × 2221+ m 1);
the adder is used for summing the outputs of the S210 module and the S205 module and the outputs 1024 × m2 of the S209 module and the outputs 128 × x2222 of the S208 module and outputting the sum as q; the subtracter is used for subtracting 24576 from q; the judger is used for judging whether the output of the subtracter is greater than or equal to 0, if so, the output is 1, otherwise, the output is 0; the top end input of the selector is the output of the judger, the first number input and the second number input are the output and the input of the subtracter respectively, the top end input value can only be 1 or 0, the first number is output when the top end input value is 1, and the second number is output when the top end input value is 0.
2. The apparatus of claim 1, wherein the S201 module and the S202 module have the same structure and include 4 adders, 12 truncators, and 2 modulo modules; the modulus calculating module comprises a subtracter, a judger and a selector, wherein the subtracter is used for subtracting 3 from the input of the modulus calculating module, the judger is used for judging whether the output of the subtracter is greater than or equal to 0, if yes, the output is 1, otherwise, the output is 0, the top end input of the selector is the output of the judger, the first number input and the second number input are respectively the output and the input of the subtracter, the top end input value can only be 1 or 0, the first number is output when the top end input value is 1, and the second number is output when the top end input value is 0;
the input of the 1 st to 7 th bit truncators are the output of the 1 st adder, the output of the 1 st bit truncators is the input of the 2 nd adder, and the 1 st bit to the 13 th bit, the 10 th to the 11 th bit, the 8 th to the 9 th bit, the 6 th to the 7 th bit, the 4 th to the 5 th bit, the 2 nd to the 3 rd bit and the 0 th to the 1 th bit of the output number of the 1 st adder are respectively intercepted and kept unchanged in the high-low order to be used as an unsigned integer;
the 8 th to 10 th bit truncators have the inputs of the 2 nd adder and the outputs of the 2 nd bit truncators are used as the inputs of the 3 rd adder, and are respectively used for truncating the 4 th bit, the 2 nd to 3 rd bit and the 0 th to 1 th bit of the output number of the 2 nd adder and keeping the high-low order unchanged to be used as an unsigned integer;
the inputs of 11 th to 12 th truncators are all the outputs of the 3 rd adder, the outputs of the truncators are all the inputs of the 4 th adder, and the truncators are respectively used for truncating the 2 nd bit and the 0 th to 1 th bits of the output number of the 3 rd adder and keeping the high-low order unchanged to be used as an unsigned integer;
the input of its 1 st modulo block is x1 or y1, and the input of its 2 nd modulo block is the output of its 4 th adder.
3. The apparatus of claim 2, wherein the S203 module and the S204 module have the same structure and include 5 truncators, 3 adders and 2 modulo modules;
the input of the 1 st to 3 rd truncators is x21 or y21, the output of the 1 st truncators is used as the input of the 1 st adder, and the 1 st to 3 rd bits, the 4 th to 5 th bits and the 0 th to 1 th bits of x21 or y21 are respectively truncated and kept unchanged in high and low order to form an unsigned integer; the 4 th-5 th bit truncator has the input of the 1 st adder and the output of the 1 st adder as the input of the 2 nd adder, and is used for truncating the 2 nd to 3 rd bits and the 0 th to 1 th bits of the output number of the 1 st adder and keeping the high and low order unchanged as an unsigned integer;
the 3 rd adder is used for summing the output of the 2 nd adder with x221 or y 221; the inputs of its 2 modulo modules are the outputs of the 2 nd and 3 rd adders respectively.
4. The apparatus of claim 3, wherein the S206 module and the S207 module have the same structure and each include 2 multipliers, 3 modulo modules, and 1 adder; the outputs of its 2 multipliers are respectively used as the inputs of 2 modulo modules, the outputs of these 2 modulo modules are all used as the input of its adder, and the output of the adder is used as the input of its 3 rd modulo module.
5. The apparatus of claim 4, wherein the S209 module comprises 12 truncators, 3 adders, 1 multiplier and 1 modulo module;
the inputs of the 1 st to 3 rd truncators are x211 x2221+ y211 x2221 and are respectively used for truncating the 4 th to 5 th bits, the 2 nd to 3 rd bits and the 0 th to 1 th bits of the input number and keeping the high and low order unchanged as an unsigned integer; the 4 th to 7 th bit truncators are used for truncating and keeping the order of the 7 th bit, the 5 th to 6 th bit, the 3 rd to 4 th bit and the 0 th to 2 nd bit of the input number m unchanged as an unsigned integer; the outputs of the 1 st to 6 th truncators are used as the input of the 1 st adder; the output of the 7 th truncator is used as the input of a multiplier which is used for multiplying the input of the multiplier by 1024;
the inputs of 8 th to 10 th truncators are all the outputs of the 1 st adder, the outputs of the truncators are all the inputs of the 2 nd adder, and the truncators are respectively used for truncating the 4 th bit, the 2 nd to 3 rd bit and the 0 th to 1 st bit of the output number of the 1 st adder and keeping the high-low order unchanged to be used as an unsigned integer;
the inputs of 11 th to 12 th bit truncators are all the outputs of the 2 nd adder, the outputs of the truncators are all the inputs of the 3 rd adder, and the truncators are respectively used for truncating the 2 nd bit and the 0 th to 1 th bits of the output number of the 2 th adder and keeping the high-low order unchanged to be used as an unsigned integer;
the input of the modulo block is the output of the 3 rd adder.
6. The apparatus of claim 5, wherein the S210 module comprises 2 truncators, 2 adders, 1 modulo module, and 1 multiplier;
the input of 2 truncators is the output of the 1 st adder, the output of the 2 truncators is used as the input of the 2 nd adder, and the 2 nd to 3 rd bits and the 0 th to 1 th bits of the output number of the 1 st adder are respectively used for truncating and keeping the high-low order unchanged to be used as an unsigned integer;
the input of the modulus module is the output of the 2 nd adder; which multiplier is used to multiply the output of the modulo block by 8192.
7. The apparatus of claim 6, wherein the S208 module comprises an S301 module and an S302 module, inputs of which are y2221 and x2221, respectively, and the two modules have the same structure and each include 2 truncators, 1 adder, and 1 modulo module;
the inputs of 2 truncators are y2221 or x2221, the outputs of the 2 truncators are used as the inputs of an adder, and the 2 nd bit and the 0 th bit to the 1 th bit of the input number of y2221 or x2221 are respectively intercepted and kept unchanged in high and low order to be used as an unsigned integer; the input of the modulo module is the output of the adder.
8. A method for realizing the modulus of a PRACH baseband signal is used for realizing the modulus of a product of two 15-bit unsigned integers x and y on 24576 and is realized by a Field Programmable Gate Array (FPGA) hardware platform, and is characterized by comprising the following steps:
the method for truncating by the truncator I and the truncator II is the same as that for truncating by the truncator I and the truncator Y respectively, and comprises the following steps: intercepting the upper 2 bits and the lower 13 bits of the input number x or y of the input number by a first sub-interceptor and a second sub-interceptor and keeping the sequence of the upper bits and the lower bits unchanged as unsigned integers x1 and x2 or y1 and y 2; intercepting the upper 6 bits and the lower 7 bits of x2 or y2 by a third sub-interceptor and a fourth sub-interceptor and keeping the sequence of the upper bits and the lower bits unchanged as unsigned integers of x21 and x22 or y21 and y 22; intercepting the upper 3 bits and the lower 3 bits of x21 or y21 by a fifth sub-interceptor and a sixth sub-interceptor and keeping the order of the upper bits and the lower bits unchanged as an unsigned integer of x211 and x212 or y211 and y 212; intercepting the upper 1 bit and the lower 6 bits of x22 or y22 by a seven sub-truncator and an eight sub-truncator and keeping the order of the upper bits and the lower bits unchanged as an unsigned integer x221 and x222 or y221 and y 222; intercepting the upper 3 bits and the lower 3 bits of x222 or y222 by a nine-bit truncator and a ten-bit truncator and keeping the sequence of the upper bits and the lower bits unchanged as an unsigned integer x2221 and x2222 or y2221 and y 2222;
processing x1 and x2 by the S201 module and outputting x1mod3 and (x1+ x2) mod 3; processing y1 and y2 by the S202 module and outputting y1mod3 and (y1+ y2) mod 3; processing x21 and x221 by the S203 module and outputting x21mod3 and (x21+ x221) mod 3; processing y21 and y221 through the S204 module and outputting y21mod3 and (y21+ y221) mod 3; processing x222, x221, y221 and y222 by the S205 module and outputting p23 ═ x22 ═ y 22;
processing, by the S206 module, the outputs of the S201 and S202 modules and outputting p1 (x1mod3 (y1+ y2) mod3+ y1mod3 (x1+ x2) mod3) mod 3; processing the outputs of the S203 and S204 modules by the S207 module and outputting p21+ p221 ═ (x21mod3 × (y21+ y221) mod3+ y21mod3 × (x21+ x221) mod3) mod 3; processing x211, x212, x2221, x2222, y211, y212, y2221 and y2222 by the S208 module and outputting m ═ x211 × y2222+ x212 × 2221+ y211 × 2222+ y212 × x2221, x211 × y2221+ y211 × 2221 and 128 (x212 × y2222+ y212 × 2222), and taking the first two outputs as the inputs of the S209 module; processing the first two outputs of the S208 module by the S209 module and outputting x211 x2221+ y211 x2221+ m1 and 1024 x m 2; processing the outputs of the S206 and S207 modules and the output of the S209 module x211 x2221+ y211 x2221+ m1 by the S210 module and outputting 8192 (p1+ p21+ p221+ x211 y2221+ y211 x2221+ m1) mod 3;
summing the outputs of the S210 and S205 modules and the outputs 1024 × m2 of the S209 and 128 × x2222 of the S208 module by an adder and outputting q; subtracting 24576 from q by a subtractor; judging whether the output of the subtracter is greater than or equal to 0 through a judger, if so, outputting to be 1, otherwise, outputting to be 0, and taking the output of the judger as the top end input of a selector; the output of the subtracter is output when the top input of the selector is 1, and the input of the subtracter is output when the top input is 0.
CN201810768157.7A 2018-07-13 2018-07-13 Modular implementation structure and implementation method of PRACH baseband signal Active CN108989258B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810768157.7A CN108989258B (en) 2018-07-13 2018-07-13 Modular implementation structure and implementation method of PRACH baseband signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810768157.7A CN108989258B (en) 2018-07-13 2018-07-13 Modular implementation structure and implementation method of PRACH baseband signal

Publications (2)

Publication Number Publication Date
CN108989258A CN108989258A (en) 2018-12-11
CN108989258B true CN108989258B (en) 2020-04-21

Family

ID=64537291

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810768157.7A Active CN108989258B (en) 2018-07-13 2018-07-13 Modular implementation structure and implementation method of PRACH baseband signal

Country Status (1)

Country Link
CN (1) CN108989258B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1567178A (en) * 2003-07-04 2005-01-19 中国科学院微电子中心 Multiplier restructuring algorithm and circuit thereof
WO2014180354A1 (en) * 2013-05-10 2014-11-13 华为技术有限公司 Method and device for sending user-specific reference signal
CN106797533A (en) * 2014-10-09 2017-05-31 高通股份有限公司 Random access procedure in honeycomb Internet of things system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1567178A (en) * 2003-07-04 2005-01-19 中国科学院微电子中心 Multiplier restructuring algorithm and circuit thereof
WO2014180354A1 (en) * 2013-05-10 2014-11-13 华为技术有限公司 Method and device for sending user-specific reference signal
CN106797533A (en) * 2014-10-09 2017-05-31 高通股份有限公司 Random access procedure in honeycomb Internet of things system

Also Published As

Publication number Publication date
CN108989258A (en) 2018-12-11

Similar Documents

Publication Publication Date Title
US8743982B2 (en) Systems for the multicarrier transmission of digital data and transmission methods using such systems
JP4823107B2 (en) OFDM modulator
US7756216B2 (en) Signal peak voltage suppression apparatus
EP2525539B1 (en) Method and apparatus for implementing preamble generation
CN103491045B (en) Multi-carrier peak-clipping processing method and device
CN112838995B (en) Broadband digital predistortion method and digital predistorter
CN107637036B (en) Method for reducing crest factor, emitter and user equipment
CN109525256B (en) Channelized transmitting structure of narrow-transition-band filter bank based on FPGA
Vinod et al. FIR filter implementation by efficient sharing of horizontal and vertical common sub-expressions
CN113792305A (en) Encryption and decryption method, system, equipment and computer readable storage medium
CN201360268Y (en) Peak clipping device based on peak detection
CN108989258B (en) Modular implementation structure and implementation method of PRACH baseband signal
WO2022121646A1 (en) Signal generation method and apparatus, storage medium, chip, and related device
CN108965191B (en) Implementation structure and implementation method for PRACH baseband signal generation
CN103117730A (en) Multichannel comb filter and implement method thereof
CN108933752B (en) IDFT (inverse discrete Fourier transform) implementation structure and implementation method of PRACH (physical random Access channel) baseband signal
CN101242168B (en) A realization method and device for FIR digital filter direct-connection
KR20060039599A (en) Method for transforming data using look-up table in ifft/fft processor
CN108809883B (en) DFT implementation system and method for PRACH baseband signal
CN109379191B (en) Dot multiplication operation circuit and method based on elliptic curve base point
Varahram et al. FPGA implementation of novel peak-to-average power ratio reduction in orthogonal frequency division multiplexing systems
KR101318992B1 (en) Modulo n calculation method and apparatus thereof
CN104468438A (en) Coefficient optimizing method for a digital pre-distortion system
Yang et al. A novel 3780-point FFT
EP3136200B1 (en) Method of and apparatus for providing a sample vector representing at least a portion of a multi-carrier modulated signal

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant