CN104468438A - Coefficient optimizing method for a digital pre-distortion system - Google Patents
Coefficient optimizing method for a digital pre-distortion system Download PDFInfo
- Publication number
- CN104468438A CN104468438A CN201310433492.9A CN201310433492A CN104468438A CN 104468438 A CN104468438 A CN 104468438A CN 201310433492 A CN201310433492 A CN 201310433492A CN 104468438 A CN104468438 A CN 104468438A
- Authority
- CN
- China
- Prior art keywords
- binary sequence
- coefficient
- optimization method
- bit
- progression
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The invention discloses a coefficient optimizing method for a digital pre-distortion system, wherein the coefficient includes i binary sequences Ai, and a fixed point quantization bit length of the binary sequences Ai is F. The coefficient optimizing method comprises: determining a minimum efficient bit length L of the binary sequence Ai according to a predetermined precision; recording bit digit number Ci being consecutively 0 or being consecutively 1 from the high bit of the binary sequence Ai, and determining series of the Ai according to the Ci; representing the series as a binary sequence Gi according to a predetermined mapping relationship; taking out consecutive L bits of the binary sequence Ai starting from a Ci-th bit from the high bit to obtain an L bit binary sequence Ai'; and joining the binary sequence Gi to the binary sequence Ai' to obtain an optimized binary sequence Ai''. The optimizing method of the invention can take fluctuation range and precision of the digital pre-distortion coefficient into account, without occupying too much hardware processing resources.
Description
Technical field
The present invention relates to field of digital information processing, particularly relate to a kind of coefficient optimization method for digital pre-distortion system.
Background technology
DPD(Digital Predistortion, digital pre-distortion) algorithm is the very effective approach improving power amplification efficiency in wireless transmission link, is widely used in the base station of mobile communication, repeater etc.Its core thinking is the phenomenon such as nonlinear distortion and memory effect according to power amplifier, the distortion phenomenon of power amplifier is described as a multistage multiple-harmonic composite model.According to this model, a DPD system can be constructed in advance on transmitting chain, make its characteristic contrary with the distorted characteristic of power amplifier, thus the signal of transmitting is corrected.DPD system be have a mind to introduce wireless transmission link the pre-change system of waveform, to offset the distortion effect of transmission channel thereafter or noise decrease to the impact of signal.
Fig. 1 is the schematic diagram of wireless transmission link, illustrated therein is the model structure of DPD system.In this model structure, the square frame being marked with " D " represents differential delay cells, and the multiple circles being marked with A00, A01 etc. are the multiplier coefficients of DPD.The transfer function of this DPD system is expressed as follows:
Wherein n is the time sequence number of digital signal y and x, x (n) namely inputs the baseband signal of digital pre-distortion system for base band exports, the output that y (n) is digital pre-distortion system, M is the difference order of supplementary memory effect, and Q is the exponential of high order harmonic component.
The distorted signal of system acquisition power amplifier and the primary signal of base band, by certain algorithm, calculate the coefficient A of digital pre-distortion system
qk, be updated in predistortion model.
FPGA(Field Programable Gate Array is often adopted, field programmable gate array in engineer applied) this high-speed parallel processing apparatus realizes above-mentioned DPD system.Restriction due to device and the demand to speed, in Project Realization, generally by the coefficient A in the transfer function of DPD system
qkfixed-point number (being such as quantified as symbol complement of two's two's complement form) being quantified as 16bits, 18bits or 24bits etc., so that realize.
Because business demand is different, the baseband signal characteristic of radio communication base station also embodies huge difference, and such as baseband signal is single carrier sometimes, is sometimes continuous multicarrier, is sometimes discrete multitone, DMT.The change of characteristics of signals, violent fluctuation is there is by causing the coefficient of DPD system, the problem caused like this is: for a specific digital pre-distortion system, after the fixed point bit length of its coefficient selected, if meet the fluctuation range that coefficient is huge, certainly will precision be sacrificed, digital pre-distortion impaired performance may be caused; And if only meet required precision, then fluctuation range may be caused wide not, equally also may cause digital pre-distortion impaired performance; If take into account coefficient fluctuation range and precision these two aspects, certainly will will expand the bit wide that binary sequence quantizes, this causes FPGA to call more hardware multiplier to realize required multiplication bit wide, thus will take too much resource.
Summary of the invention
In order to solve the problems of the technologies described above, the present invention adopts the virtual floating-point quantification manner of binary system, virtual floating-point quantification is carried out to the coefficient in the transfer function of the DPD system that prior art is calculated, to optimize RF algorithms, evade above-mentioned digital pre-distortion impaired performance or take the problem of excess resource.
For this reason, the invention provides a kind of coefficient optimization method for digital pre-distortion system, it is optimized for the coefficient in the transfer function to described digital pre-distortion system, described coefficient comprises i binary sequence Ai, it is F that the fixed point of described binary sequence Ai quantizes bit length, and described coefficient optimization method comprises: step S01: the minimum effective bit length L determining described binary sequence Ai according to predetermined precision; Step S02: by binary sequence Ai from a high position be continuously 0 or from a high position be continuously 1 bit figure place Ci carry out record, and determine the progression of Ai according to Ci, the size rank of described series expression coefficient; Step S03: be binary sequence Gi by described series expression according to predetermined mapping relations; Step S04: the binary sequence Ai' that continuous print L position obtains L position is intercepted out from the Ci position that a high position starts to binary sequence Ai; Step S05: connect binary sequence Gi with binary sequence Ai' the binary sequence Ai'' combining and obtain through optimizing.
By the coefficient optimized algorithm for digital pre-distortion system of the present invention, DPD coefficient fluctuation range and precision can be taken into account, too much hardware processing resources need not be taken simultaneously, effectively can improve the digital information processing efficiency of wireless radio-frequency link.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of wireless transmission link, illustrated therein is the model structure of DPD system;
Fig. 2 is the flow chart of the coefficient optimization method for digital pre-distortion system of the present invention;
Fig. 3 is the schematic diagram of an embodiment of the coefficient optimization method for digital pre-distortion system of the present invention.
Embodiment
The present invention is described in detail with reference to the accompanying drawings.
Coefficient A in the transfer function of DPD system
qkin each comprise real part and imaginary part two binary sequences, in the present invention, by all coefficient A
qkreal part binary sequence and the sum of imaginary part binary sequence be designated as i, i.e. coefficient A
qkcomprise i binary sequence Ai, and the fixed point of this binary sequence quantification bit length is designated as F.
Fig. 2 is the flow chart of the coefficient optimization method for digital pre-distortion system of the present invention.As shown in Figure 2, the coefficient optimization method for digital pre-distortion system of the present invention comprises:
Step S01: according to minimum effective bit length L of predetermined precision determination binary sequence Ai;
In this step, the predetermined precision required by computing determines the minimum effective bit length of binary sequence Ai needing to optimize, the figure place that when namely carrying out the multiplying shown in Fig. 1, each coefficient participates in.
Step S02: by binary sequence Ai from a high position be continuously 0 or from a high position be continuously 1 bit figure place Ci carry out record, and determine the progression of Ai according to Ci, the size rank of described series expression coefficient;
In this step, from a high position of each binary sequence Ai be continuously 0 or be continuously 1 bit figure place be recorded as Ci, and determine the progression of Ai according to Ci.Be continuously 0 or be continuously 1 figure place more, progression is larger, represents that the absolute value of this binary sequence is less.
Undertaken corresponding by Linear Mapping or Nonlinear Mapping relation between progression with Ci.For the less DPD coefficient of fluctuation, Linear Mapping relation can be adopted, such as, the value of progression can be defined as Ci-1, like this, when binary sequence Ai from a high position be continuously 0 number be 1,2 and 3 time, corresponding progression is respectively 0,1 and 2; For the coefficient that fluctuation is larger, Nonlinear Mapping relation can be adopted, such as, the value of described progression is defined as the minimum value within the scope of the predetermined value at Ci-1 place.In an embodiment of the invention, when binary sequence Ai from a high position be continuously 0 number be 3 and 4 time, equal scale of visibility number is 2; When binary sequence Ai from a high position be continuously 0 number be 5,6 and 7 time, equal scale of visibility number is 4.By Nonlinear Mapping like this, the value of the binary sequence Gi corresponding to compressible progression, reduces the quantification bit figure place of Gi.
Step S03: be binary sequence Gi by described series expression according to predetermined mapping relations;
In this step, the progression determined in step S03 is expressed as binary sequence Gi according to predetermined mapping relations.Such as progression directly can be set to the numerical values recited of Gi, or after progression is deducted the numerical value such as 1 or 2, again the numerical value of acquisition be set to the numerical values recited of Gi.In addition, all right self-defined mapping relations, such as, when progression is 0, are set to 7 by the numerical values recited of Gi; When progression is 1, the numerical values recited of Gi is set to 6, etc.Predetermined various mapping relations can be carried out as required, to compress the value of Gi, reduce the quantification bit figure place of Gi.
Step S04: the binary sequence Ai' that continuous print L position obtains L position is intercepted out from the Ci position that a high position starts to binary sequence Ai;
In this step, from Ai, intercept out the numerical part meeting operational precision and require, the figure place after the L number that intercepts out cast out.
Step S05: connect binary sequence Gi with binary sequence Ai' the binary sequence Ai'' combining and obtain through optimizing.
In this step, connect the binary sequence Gi of the progression of expression binary sequence Ai with the binary sequence Ai' obtained through extracting minimum effective bit figure place from binary sequence Ai the binary sequence Ai'' combining and obtain through optimizing.
By coefficient optimization method of the present invention, make the figure place of Ai'' be less than original length F, decrease the figure place of the coefficient participating in multiplying, too much hardware processing resources need not be taken, effectively can improve the digital information processing efficiency of wireless radio-frequency link.
In one embodiment of the invention, in above-mentioned steps S03, obtain the figure place of described binary sequence Gi by following formulae discovery: G=ceil(log2(F-L+1)), wherein ceil() represent the number that rounds up.By this embodiment, can, while the bit figure place as far as possible reducing Gi, guarantee to allow the data through optimizing that upset or saturated occurs in the process of the digital processings such as multiplying.Except the method for this calculating Gi figure place, also can adopt the method for other self-defined figure places, as long as can guarantee that the figure place of the binary sequence Ai'' through optimizing is less than original length L and can reaches the object improving operation efficiency.
In one embodiment of the invention, in above-mentioned steps S05, after binary sequence Gi can being connected on the lowest order of corresponding binary sequence Ai' or carry out combining the binary sequence Ai'' obtained through optimizing before highest order.So, the binary sequence Ai'' through optimizing can comprise the progression information before optimization and meet the data bits subscribing precision, realizes virtual floating-point and quantizes.
In one embodiment of the invention, in step S02, using Ci minimum in h corresponding for h binary sequence Ai Ci as this h the Ci that binary sequence Ai is common, to determine this h the progression that binary sequence Ai is common.After this common progression is expressed as common binary sequence Gi according to predetermined mapping relations, in described step S05, this common binary sequence Gi is divided into h subsequence, and this h subsequence is connected with described h binary sequence Ai' respectively to combining and obtain the binary sequence Ai'' of h through optimizing.This embodiment shares a progression by allowing multiple binary sequence Ai, can reduce the figure place of the binary sequence Ai'' after optimizing further.
As an example in the embodiment of above-mentioned shared progression, can take to allow each A
qkthe real part of (plural number) and two of imaginary part binary sequence Ai carry out a shared progression, be equivalent to find out maximum absolute value value from real part and imaginary part, using the progression of maximum as common progression, the Gi that this progression is corresponding becomes two parts according to certain regular partition, piece together respectively the corresponding binary sequence Ai of real part and imaginary part below or above, thus realize the further optimization to DPD coefficient.
Fig. 3 is the schematic diagram of an embodiment of the coefficient optimization method for digital pre-distortion system of the present invention.
See Fig. 3, calculate A based on prior art
qkafterwards, recording its bit length after quantizing of generally fixing a point is F, and the F in the present embodiment is for 28bit.Adopt coefficient optimization method of the present invention to carry out the virtual floating-point of binary system and quantize the rear coefficient obtained, its length is T.
Obtain the coefficient of 20bits after quantizing for the fixed point coefficient virtual floating-point of 28bits in the present embodiment, do not represent the present invention and be only applicable to 20bits.
First the minimum effective bit length needed for the coefficient in the transfer function of predetermined operational precision determination digital pre-distortion system, be designated as F, the F in the present embodiment is 16.
To each A
qkreal part and the binary sequence Ai of imaginary part, according to sign, record is the bit figure place Ci of 0 or 1 continuously from a high position, during the complement of two's two's complement of positive number, record is the bit figure place of 0 continuously, during the complement of two's two's complement of negative, record is the bit figure place of 1 continuously, then according to Ci, classification is carried out to coefficient magnitude, and record its rank.
With the complement of two's two's complement of positive number for example, the highest bit is 0, calculates from high-order toward low level, be continuously the bit figure place of 0 for foundation, 1 is labeled as 0, and two are labeled as 1, and three are labeled as 2, and the rest may be inferred.According to A
qkquantification length F and minimum effective length L, need mark progression be F-L+1; Get the figure place G=ceil (log2 (F-L+1)) of Gi, wherein, ceil () expression rounds up, and each number of stages being turned to the binary sequence Gi of G bits, is 4 according to the Gi figure place G that this formula can obtain in the present embodiment.
For 0 DBMS, getting high L position, to 1 DBMS, get time high-order continuous L position started, by that analogy, being designated as binary sequence Ai' by intercepting the L bit sequence obtained.
Being connected by Ai' and Gi corresponding for each Ai and be combined into a new sequence, be recorded as Ai'', is exactly that the final virtual floating-point through optimizing quantizes to export.
In FPGA side, receive Ai'', according to the length G of the good binary sequence Gi of system negotiates, intercept the high L position in Ai'' i.e. Ai' subparticipation multiplying, then before the Output rusults of multiplier, add sign bit, the figure place of interpolation is exactly progression corresponding to Gi.
In the present embodiment, adopt after virtual floating-point quantification manner is optimized DPD coefficient, for the coefficient of 28bits, if minimum effective bit length is 16bits, after so quantizing, just only need 20bits, and the bit wide participating in multiplying is 16bits.
In addition, in the embodiment shown in fig. 3, if adopt the real part of previously described same coefficient and imaginary part to share the method for a progression, then only 18bits is needed after quantizing.
The present invention is not limited to above-mentioned particular implementation example; do not deviating under the present invention's spirit and real situation thereof; those skilled in the art can make various corresponding change and distortion according to the present invention, but these corresponding changes and distortion all should belong within claims protection range of the present invention.
Claims (10)
1. the coefficient optimization method for digital pre-distortion system, it is optimized for the coefficient in the transfer function to described digital pre-distortion system, described coefficient comprises i binary sequence Ai, it is F that the fixed point of described binary sequence Ai quantizes bit length, it is characterized in that, described coefficient optimization method comprises:
Step S01: the minimum effective bit length L determining described binary sequence Ai according to predetermined precision;
Step S02: by binary sequence Ai from a high position be continuously 0 or from a high position be continuously 1 bit figure place Ci carry out record, and determine the progression of Ai according to Ci, the size rank of described series expression coefficient;
Step S03: be binary sequence Gi by described series expression according to predetermined mapping relations;
Step S04: the binary sequence Ai' that continuous print L position obtains L position is intercepted out from the Ci position that a high position starts to binary sequence Ai;
Step S05: connect binary sequence Gi with binary sequence Ai' the binary sequence Ai'' combining and obtain through optimizing.
2. coefficient optimization method as claimed in claim 1, is characterized in that, in described step S02, the value of described progression is defined as Ci-1.
3. coefficient optimization method as claimed in claim 1, is characterized in that, in described step S02, the value of described progression is defined as the minimum value within the scope of the predetermined value at Ci-1 place.
4. coefficient optimization method as claimed in claim 1, be is characterized in that, in described step S03, obtained the figure place of described binary sequence Gi: G=ceil(log2(F-L+1 by following formulae discovery)), wherein ceil() represent the number that rounds up.
5. coefficient optimization method as claimed in claim 1, is characterized in that, in described step S05,
After binary sequence Gi being connected on the lowest order of corresponding binary sequence Ai' or the binary sequence Ai'' obtained before highest order through optimizing.
6. coefficient optimization method as claimed in claim 1, is characterized in that, also comprise in described step S02:
Using Ci minimum in h corresponding for h binary sequence Ai Ci as this h the Ci that binary sequence Ai is common, determine described h the progression that binary sequence Ai is common according to this Ci,
Then in described step S05: binary sequence Gi is divided into h subsequence, and this h subsequence is connected with h binary sequence Ai' respectively to combining and obtain the binary sequence Ai'' of h through optimizing.
7. coefficient optimization method as claimed in claim 6, it is characterized in that, h equals 2, and described h binary sequence Ai is respectively real part and the imaginary part of same digital pre-distortion coefficient.
8. the coefficient optimization method according to any one of claim 1 to 7, is characterized in that, described binary sequence is the complement of two's two's complement.
9. coefficient optimization method as claimed in claim 8, it is characterized in that, described binary sequence is positive number, then in described step S02, by binary sequence Ai from a high position be continuously 0 bit figure place Ci carry out record.
10. coefficient optimization method as claimed in claim 8, it is characterized in that, described binary sequence is negative, then in described step S02, by binary sequence Ai from a high position be continuously 1 bit figure place Ci carry out record.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310433492.9A CN104468438A (en) | 2013-09-22 | 2013-09-22 | Coefficient optimizing method for a digital pre-distortion system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310433492.9A CN104468438A (en) | 2013-09-22 | 2013-09-22 | Coefficient optimizing method for a digital pre-distortion system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104468438A true CN104468438A (en) | 2015-03-25 |
Family
ID=52913828
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310433492.9A Pending CN104468438A (en) | 2013-09-22 | 2013-09-22 | Coefficient optimizing method for a digital pre-distortion system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104468438A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108123907A (en) * | 2017-11-24 | 2018-06-05 | 浙江天则通信技术有限公司 | A kind of low complex degree equalization method for single carrier frequency domain equalization channel |
| CN114553247A (en) * | 2022-04-08 | 2022-05-27 | 上海星思半导体有限责任公司 | Radio frequency circuit, and method and device for determining digital predistortion coefficient set |
-
2013
- 2013-09-22 CN CN201310433492.9A patent/CN104468438A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108123907A (en) * | 2017-11-24 | 2018-06-05 | 浙江天则通信技术有限公司 | A kind of low complex degree equalization method for single carrier frequency domain equalization channel |
| CN108123907B (en) * | 2017-11-24 | 2020-08-25 | 浙江天则通信技术有限公司 | Low-complexity equalization method for single carrier frequency domain equalization channel |
| CN114553247A (en) * | 2022-04-08 | 2022-05-27 | 上海星思半导体有限责任公司 | Radio frequency circuit, and method and device for determining digital predistortion coefficient set |
| CN114553247B (en) * | 2022-04-08 | 2023-07-28 | 上海星思半导体有限责任公司 | Radio frequency circuit, method and device for determining digital predistortion coefficient set |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102195912B (en) | Digital pre-distortion processing equipment and method | |
| CN103975564A (en) | Processor having instruction set with user-defined non-linear functions for digital pre-distortion (DPD) and other non-linear applications | |
| US20100153049A1 (en) | Apparatus, system, and method for calculating a non-linearity metric | |
| CN106708468B (en) | Division operation device | |
| CN104868854A (en) | Digital predistortion system | |
| Singh et al. | Non linearity analysis of high power amplifier in OFDM system | |
| CN102497350A (en) | OFDM (Orthogonal Frequency Division Multiplexing) peak-to-average power ratio lowering method based on constellation linear expansion | |
| CN103685110B (en) | Predistortion processing method and system and predistortion factor arithmetic unit | |
| CN104468438A (en) | Coefficient optimizing method for a digital pre-distortion system | |
| CN102437838A (en) | Transmitting a signal from a power amplifier | |
| CN104468439A (en) | Lookup table optimization method for digital predistortion system | |
| CN103401831A (en) | FPGA (Field Programmable Gate Array)-based LTE (Long Term Evolution) digital intermediate frequency crest factor reduction method and device | |
| WO2023236610A1 (en) | Signal detection method and apparatus, and electronic device and storage medium | |
| CN107704656A (en) | The design and implementation methods for being parameterized into mode filter based on FPGA | |
| CN104994051B (en) | Based on instantaneously the signal transmitting with the linear-scale conversion of the raising mixed carrier system PA efficiency of average power ratio and method of reseptance | |
| CN102403965B (en) | Volterra-model-based power amplifier simulation method | |
| CN108833043B (en) | AWGN channel realization method and device based on Polar method improvement | |
| CN114077605A (en) | Data processing method and device | |
| CN113132279A (en) | Pre-distortion processing method, device, equipment and storage medium | |
| CN100480987C (en) | Method and device for execution multiplication or division operation in electronic circuit | |
| CN111131104B (en) | Pre-distortion processing method, device, storage medium and equipment | |
| CN103297378B (en) | Look-up table pre-distortion method based on orthogonal frequency-division multiplex singal amplitude characteristic | |
| CN103888312A (en) | Alarm method and device of pre-distortion system | |
| CN205039844U (en) | OFDM receiver | |
| CN113515259B (en) | Complex number approximate modulus realization circuit and method suitable for floating point format |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150325 |