CN108988797A - Low-noise amplifier and electronic equipment - Google Patents
Low-noise amplifier and electronic equipment Download PDFInfo
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- CN108988797A CN108988797A CN201810609088.5A CN201810609088A CN108988797A CN 108988797 A CN108988797 A CN 108988797A CN 201810609088 A CN201810609088 A CN 201810609088A CN 108988797 A CN108988797 A CN 108988797A
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- 230000001629 suppression Effects 0.000 claims abstract description 15
- 230000002708 enhancing effect Effects 0.000 claims abstract description 5
- 230000001939 inductive effect Effects 0.000 claims description 13
- 239000003990 capacitor Substances 0.000 claims description 10
- 230000005611 electricity Effects 0.000 claims description 3
- 230000003139 buffering effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 230000003321 amplification Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
- H03F3/16—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
- H03F3/165—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices with junction-FET's
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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Abstract
The embodiment of the present application provides a kind of low-noise amplifier and electronic equipment, low-noise amplifier includes: input terminal, output end, common source pole unit, common gate unit, input resistant matching unit, output impedance matching unit, gain suppression unit, the gain suppression unit is for carrying out enhancing processing to the input voltage for being loaded into the input resistant matching unit by input terminal, the common source pole unit is used to enhanced input voltage being converted to input current, the common gate unit is for buffering the input current, and output voltage to the output end and the input voltage are isolated, the input impedance unit is the equivalent impedance of the input terminal, the output impedance matching is the equivalent impedance of the output end, current efficiency with higher and good input and output matching.
Description
Technical field
The invention relates to field of circuit technology more particularly to a kind of low-noise amplifiers and electronic equipment.
Background technique
Low noise amplifier (low-noise amplifier, abbreviation LNA) is mainly used in communication system will be received from day
The signal of line amplifies, in order to which the electronic equipment of rear class is handled.Since the signal from antenna is usually quite faint, low noise
Amplifier is respectively positioned on the position very close to antenna under normal circumstances, to reduce loss of the signal by transmission line.
It is located at entire receiver close to the level-one at first of antenna just because of low noise amplifier, its characteristic directly affects
Entire receiver receive the quality of signal.In order to ensure antenna received signal can receiver afterbody it is correct
Recovery, a good low noise amplifier needs generate alap noise and distortion while amplified signal.
But there is urgently improved technological deficiency in existing low-noise amplifier, for example, current efficiency is lower, or
Input and output matching is poor.
Summary of the invention
In view of this, one of the technical issues of the embodiment of the present application is solved is to provide a kind of low-noise amplifier and electricity
Sub- equipment, to overcome or alleviate above-mentioned technological deficiency in the prior art.
The embodiment of the present application provides a kind of low-noise amplifier comprising: input, output end, is total to common source pole unit
Grid unit, input resistant matching unit, output impedance matching unit, gain suppression unit, the gain suppression unit are used for
Enhancing processing is carried out to the input voltage for being loaded into the input resistant matching unit by input terminal, the common source pole unit is used
In enhanced input voltage is converted to input current, the common gate unit is used to buffer the input current,
And output voltage to the output end and the input voltage are isolated, the input impedance unit is the input terminal
Equivalent impedance, the output impedance matching are the equivalent impedance of the output end.
The embodiment of the present application also provides a kind of electronic equipment comprising the low-noise amplifier.Such as eventually for intelligence
End or server.
In technical solution provided by the embodiments of the present application, low-noise amplifier includes: input, output end, common source list
Member, common gate unit, input resistant matching unit, output impedance matching unit, gain suppression unit, the gain suppression unit
For carrying out enhancing processing, the common source list to the input voltage for being loaded into the input resistant matching unit by input terminal
Member is for being converted to input current for enhanced input voltage, and the common gate unit is for delaying the input current
Punching, and output voltage to the output end and the input voltage are isolated, the input impedance unit is the input
The equivalent impedance at end, output impedance matching are the equivalent impedance of the output end, current efficiency with higher and good
Good input and output matching.
Detailed description of the invention
The some specific of the embodiment of the present application is described in detail by way of example and not limitation with reference to the accompanying drawings hereinafter
Embodiment.Identical appended drawing reference denotes same or similar part or part in attached drawing.Those skilled in the art should manage
Solution, the drawings are not necessarily drawn to scale.In attached drawing:
Fig. 1 is the structural schematic diagram of one low-noise amplifier of the embodiment of the present application；
Fig. 2 is the structural schematic diagram of two low-noise amplifier of the embodiment of the present application；
Fig. 3 is the structural schematic diagram of low-noise amplifier in the embodiment of the present application three.
Specific embodiment
Any technical solution for implementing the embodiment of the present application must be not necessarily required to reach simultaneously above all advantages.
Below in conjunction with attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Usually exist
The component of the embodiment of the present invention described and illustrated in attached drawing can be arranged and be designed with a variety of different configurations herein.Cause
This, is not intended to limit claimed invention to the detailed description of the embodiment of the present invention provided in the accompanying drawings below
Range, but it is merely representative of selected embodiment of the invention.Based on the embodiment of the present invention, those skilled in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall within the protection scope of the present invention.
In order to make those skilled in the art more fully understand the technical solution in the embodiment of the present application, below in conjunction with the application
Attached drawing in embodiment, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described reality
Applying example only is the embodiment of the present application a part of the embodiment, instead of all the embodiments.Based on the implementation in the embodiment of the present application
The range of the embodiment of the present application protection all should belong in example, those of ordinary skill in the art's every other embodiment obtained.
Further illustrate that the embodiment of the present application implements below with reference to the embodiment of the present application attached drawing.
Fig. 1 is the structural schematic diagram of one low-noise amplifier of the embodiment of the present application；In the present embodiment, with the low noise amplification
Device is illustrated for the function of being equal to low-noise amplifier can be implemented separately.
Shown in Figure 1, low-noise amplifier includes: the first common source pole unit, the first common gate unit, the first input resistance
Anti- matching unit, the first output impedance matching unit, the first common source pole unit are used to input voltage Vi being converted to input
Electric current, the first common gate unit are used to buffer the input current, and to the output of first output end electricity
Pressure Vo and first input voltage are isolated, and the first input impedance unit is the equivalent resistance of the first input end
Anti-, the output impedance matching is the equivalent impedance of the output end.
Optionally, in any embodiment of the application, the first end of the first common source pole unit is total with described first
The second end of grid unit connects, and the second end of the first common gate unit and the first output impedance matching unit connect
It connects, the third end of the first common source pole unit is connect with the first voltage Vdd.
Optionally, in any embodiment of the application, the third end of the first common gate unit and first voltage connect
It connects.
In a concrete application scene, the first common source pole unit is the second NMOS tube M0, the first common gate list
Member is the first NMOS tube M1.Refer again to Fig. 1, the first end of the first NMOS and the second NMOS tube is respectively drain terminal, the first NMOS tube
It is source with the second end of the second NMOS tube, the third end of the first NMOS tube and the second NMOS tube is grid end.
At the same time, in the concrete application scene, the first input resistant matching unit include: the first equivalent inductance L1 and
Second equivalent inductance L2；Second output impedance matching unit includes: the 0th equivalent inductance L0 and the 0th equivalent capacity C0.
Based on the specific type selecting of device in above-mentioned concrete application scene, the connection relationship of each device is specific as follows:
The source of first NMOS tube is connect with the drain terminal of the 2nd NMOS unit, the drain terminal of first NMOS tube
It is connect with the first output impedance matching unit, the grid end of first NMOS tube is connect with the first voltage Vdd.Specifically
Ground, the drain terminal of first NMOS tube is connect with the 0th equivalent inductance L0 in the first output impedance matching unit, into one
Step is connect by the 0th equivalent inductance L0 in the first output impedance matching unit with first voltage Vdd, and described first
The grid end of NMOS tube is connect with the first voltage Vdd.Specifically, one end of the 0th equivalent inductance L0 and first voltage Vdd connect
It connects, other end is connect with the drain terminal of first NMOS tube.The drain terminal of 0th one end equivalent capacity C0 and the first NMOS tube connects
It connects, the other end is used for transmission the first output voltage Vo i.e. output voltage of the first output end as the first output end.
The source of second NMOS tube is connect with the first input resistant matching unit, the grid of second NMOS tube
End is connect by the first input resistant matching unit with input voltage Vi.Specifically, the source of second NMOS tube with
The second equivalent inductance L2 connection in the first input resistant matching unit, the grid end of second NMOS tube pass through described the
The first equivalent inductance L1 in one input resistant matching unit is connect with input voltage Vi.
For the circuit of above-mentioned Fig. 1, there are following relationships:
Av=gmn*ZL
In above-mentioned formula (1), gmn indicates the mutual conductance of the second NMOS tube, and Av indicates that the voltage gain of integrated circuit, ZL indicate
The capacitive reactance of 0th equivalent capacity, un indicate the mobility of the second NMOS tube, and cox indicates the oxidation layer parameter of the second NMOS tube, W/L
Indicate the breadth length ratio of the second NMOS tube, Id indicates the electric current of the second NMOS tube.
Fig. 1 circuit structure as described in the examples, since the first common source pole unit is used to convert input voltage Vi
For input current, the first common gate unit is used to buffer the input current, and to first output end
Output voltage Vo and first input voltage are isolated, the first input impedance unit be the first input end etc.
Impedance is imitated, the output impedance matching is the equivalent impedance of the output end, to preferably realize input/output impedance
Match, while there is lower noise.
Fig. 2 is the structural schematic diagram of two low-noise amplifier of the embodiment of the present application；In the present embodiment, with the low noise amplification
Device is illustrated for the function of being equal to low-noise amplifier can be implemented separately.
Shown in Figure 2, which includes the second common source pole unit, the second common gate unit, the second input
Impedance matching unit, the second output impedance matching unit, the second common source pole unit are defeated for being converted to input voltage Vi
Enter electric current, the second common gate unit is used to buffer the input current, and to the output voltage of the output end
Vo and the input voltage are isolated, and the second input impedance unit is the equivalent impedance of input terminal, the output impedance
Matching is the equivalent impedance of the output end.
Specifically, in the present embodiment, the first end of the second common source pole unit and the second common gate unit
First end connection, the second common source pole unit second end ground connection, the third end of the second common source pole unit with it is described defeated
Enter voltage connection.
Specifically, in the present embodiment, the second end of the second common gate unit is connect with the first voltage Vdd,
The third end of the second common gate unit is connect with the third end of the second common source pole unit.In addition, circuit shown in Fig. 2
On be additionally provided with feedback resistance R1, feedback resistance R1 is across between the grid end and drain terminal of the second PMOS tube and the second NMOS tube.
In a concrete application scene, the second common source pole unit is third NMOS tube M0, and the second common gate unit is
4th PMOS tube M1, the first end of third NMOS tube are drain terminal, and the second end of third NMOS tube is source, the of third NMOS tube
Three ends are grid end, and the first end of the 4th PMOS tube is drain terminal, and the second end of the 3rd NMOS is source, and the third end of the 3rd NMOS is
Grid end.The drain terminal of the third NMOS tube is connect with the drain terminal of the 4th PMOS, the source ground connection of the third NMOS tube, institute
The grid end for stating third NMOS tube is connect with the input voltage Vi.
Second input resistant matching unit includes the first equivalent inductance L1, and the second output impedance matching unit includes 0th etc.
Capacitor C0 is imitated, the grid end of the 3rd NMOS is connect by the first equivalent inductance L1 with input voltage Vi, and the drain terminal of the 4th PMOS passes through
0th equivalent capacity C0 forms the output end and transmits output voltage Vo.It should be noted that the second input impedance here
The 0th equivalent capacity C0 label that the first equivalent inductance L1, the second output impedance matching unit for including with unit include although with
Related device in above-mentioned Fig. 1 is identical, and not representing is that its impedance value is centainly identical or same device.
For the circuit of above-mentioned Fig. 1, there are following relationships:
Av=(gmn+gmp) * ZL
In above-mentioned formula (2), gmp indicates the mutual conductance of the 4th PMOS tube, and gmn indicates the mutual conductance of third NMOS tube, and Av is indicated
The voltage gain of integrated circuit, ZL indicate the impedance of feedback resistance, and up indicates the mobility of the 4th PMOS tube, and cox " indicates the 4th
The oxidation layer parameter of PMOS tube, W/L " indicate the breadth length ratio of the 4th PMOS tube, and Id " indicates the electric current of the 4th PMOS tube.Un is indicated
The mobility of third NMOS tube, cox' indicate that the oxidation layer parameter of third NMOS tube, W/L' indicate the breadth length ratio of third NMOS tube,
The electric current of Id' expression third NMOS tube.
Embodiment shown in Fig. 2 compares above-mentioned formula (2), since the second common source pole unit is used to turn input voltage Vi
It is changed to input current, the second common gate unit is used to buffer the input current, and to the defeated of the output end
Voltage Vo and the input voltage are isolated out, and the second input impedance unit is the equivalent impedance of input terminal, described defeated
Impedance matching is the equivalent impedance of the output end out, so as to realize higher current efficiency.
Fig. 3 is the structural schematic diagram of low-noise amplifier in the embodiment of the present application three；As shown in figure 3, in the present embodiment, it is low
Noise amplifier includes: input, output end, third common source pole unit, third common gate unit, third input resistant matching list
Member, third output impedance matching unit, gain suppression unit, the gain suppression unit is for being loaded into institute to by input terminal
The input voltage for stating third input resistant matching unit carries out enhancing processing, and the third common source pole unit is used for will be enhanced
Input voltage is converted to input current, and the third common gate unit is used to buffer the input current, and to described
The output voltage of output end and the input voltage are isolated, and the input impedance unit is the equivalent resistance of the input terminal
Anti-, the output impedance matching is the equivalent impedance of the output end.
In the present embodiment, the first end of the second end of the third common gate unit and the third common source pole unit connects
It connects, the first end of the third common gate unit is connect with the third output impedance matching unit, the third common source list
The third end of member is connect with first voltage Vdd.
In the present embodiment, the second end of the third common source pole unit is connect with the third input resistant matching unit,
The third end of the third common source pole unit is connect with the gain suppression unit.
In the present embodiment, the third input resistant matching unit passes through the second capacitor and the third common source pole unit
The connection of third end.
In a concrete application scene, the third common gate unit is the 5th NMOS tube M1, the third common source list
Member is the 6th NMOS tube M0.The first end of 5th NMOS tube and the 6th NMOS tube is drain terminal, and second end is source, third end
For grid end.
In the present embodiment, the source of the 5th NMOS tube is connect with the drain terminal of the 6th NMOS tube, and the described 5th
The drain terminal of NMOS tube is connect with the third output impedance matching unit, the grid end and first voltage Vdd of the 5th NMOS tube
Connection.
In the present embodiment, the source of the 6th NMOS tube is connect with the third input resistant matching unit, and described
The grid end of six NMOS tubes is connect with the gain suppression unit.
In the present embodiment, the gain suppression unit includes: third capacitor C3, first resistor R1, amplifier tube M3, and described
Three capacitor C3, first resistor R1 are connect with the third end (such as grid end) of the amplifier tube M3 (PMOS tube), the amplifier tube
Second end (such as source) is electrically connected second voltage VDD, the first end (such as drain terminal) of the amplifier tube and the 5th NMOS tube
Second end (such as source) connection.At the same time, third capacitor C3 is connect with the first equivalent inductive reactance L1 and the second capacitor C2.
In the present embodiment, the third input resistant matching unit passes through the grid of the second capacitor C2 and the 6th NMOS tube
End connection.
In the present embodiment, the third output impedance matching unit includes the 0th equivalent inductive reactance L0 and the 0th equivalent capacitive reactance
One end of C0, the 0th equivalent inductive reactance are connect with the drain terminal of the 5th NMOS tube, and other end and first voltage Vdd connect
It connects, one end of the 0th equivalent capacitive reactance is connect with the drain terminal of the 5th NMOS tube, and other end is as output end for defeated
Voltage Vo out.
In the present embodiment, the third input resistant matching unit includes the first equivalent inductive reactance L1 and the second equivalent inductive reactance
L2, first equivalent inductive reactance are connect with the grid end of the 6th NMOS tube, second equivalent inductive reactance and the 6th NMOS tube
Source connection.
For the circuit of above-mentioned Fig. 3, there are following relationships:
Av=(gmn+gmp) * ZL
In above-mentioned formula (3), gmn indicates the mutual conductance of the 5th NMOS tube, and gmp indicates the mutual conductance of amplifier tube M3 pipe, and Av is indicated
The voltage gain of integrated circuit, ZL indicate the impedance of feedback resistance, and un indicates the mobility of the 5th NMOS tube, and cox' indicates the 5th
The oxidation layer parameter of NMOS tube, W/L' indicate the breadth length ratio of the 5th NMOS tube, and Id' indicates the electric current of the 5th NMOS tube.Up is indicated
The mobility of amplifier tube M3, cox " indicate that the oxidation layer parameter of amplifier tube M3, W/L " indicate the breadth length ratio of amplifier tube M3, Id " table
Show the electric current of amplifier tube M3.
Referring to above-mentioned formula (3), compared with the circuit structure of Fig. 1 and Fig. 2, the circuit structure of Fig. 3 has merged Fig. 1 and Fig. 2
Preferable input/output impedance matching, while current efficiency with higher may be implemented in the structure of circuit.
The apparatus embodiments described above are merely exemplary, wherein described, module can as illustrated by the separation member
It is physically separated with being or may not be, the component shown as module may or may not be physics mould
Block, it can it is in one place, or may be distributed on multiple network modules.It can be selected according to the actual needs
In some or all of the modules achieve the purpose of the solution of this embodiment.Those of ordinary skill in the art are not paying creativeness
Labour in the case where, it can understand and implement.
Finally, it should be noted that above embodiments are only to illustrate the technical solution of the embodiment of the present application, rather than it is limited
System；Although the application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: its
It is still possible to modify the technical solutions described in the foregoing embodiments, or part of technical characteristic is equal
Replacement；And these are modified or replaceed, each embodiment technical solution of the application that it does not separate the essence of the corresponding technical solution
Spirit and scope.
Claims (10)
1. a kind of low-noise amplifier characterized by comprising input, output end, common source pole unit, common gate unit, defeated
Enter impedance matching unit, output impedance matching unit, gain suppression unit, the gain suppression unit is used for passing through input terminal
The input voltage for being loaded into the input resistant matching unit carries out enhancing processing, and the common source pole unit is used for will be enhanced
Input voltage is converted to input current, and the common gate unit is used to buffer the input current, and to the output
The output voltage at end and the input voltage are isolated, and the input impedance unit is the equivalent impedance of the input terminal, institute
State the equivalent impedance that output impedance matching is the output end.
2. low-noise amplifier according to claim 1, which is characterized in that the first end of the common gate unit with it is described
The first end of common source pole unit connects, and the second end of the common gate unit is connect with the output impedance matching unit, described
The third end of common source pole unit is connect with first voltage.
3. the low-noise amplifier according to claim, which is characterized in that the second end of the common source pole unit with it is described
The connection of input resistant matching unit, the third end of the common source pole unit is connect with the gain suppression unit.
4. low-noise amplifier according to claim 1, which is characterized in that the common gate unit is NMOS tube, described
Common source pole unit is PMOS tube.
5. low-noise amplifier according to claim 1, which is characterized in that the gain suppression unit includes: the first electricity
Appearance, first resistor, amplifier tube, the first capacitor, first resistor are connect with the third end of the amplifier tube, the amplifier tube
Second end be electrically connected second voltage, the first end of the amplifier tube connect with the common gate unit.
6. low-noise amplifier according to claim 5, which is characterized in that the first capacitor is used for direct-current blocking-up, institute
First resistor is stated for dividing, the amplifier tube is used for enhanced processing.
7. low-noise amplifier according to claim 5, which is characterized in that the input resistant matching unit passes through second
Capacitor is connect with the third end of the common source pole unit.
8. low-noise amplifier according to claim 1, which is characterized in that the input resistant matching unit includes first
Equivalent inductive reactance and the second equivalent inductive reactance, first equivalent inductive reactance are connect with the third end of the common source pole unit, and described second
Equivalent inductive reactance is connect with the second end of institute's common source pole unit.
9. low-noise amplifier according to claim 1, which is characterized in that the output impedance matching unit includes the 0th
One end of equivalent inductive reactance and the 0th equivalent capacitive reactance, the 0th equivalent inductive reactance is connect with the second end of the common gate unit, separately
Outer one end is connect with first voltage, and one end of the third equivalent capacitive reactance is connect with the second end of the common gate unit, in addition
One end is as output end.
10. a kind of electronic equipment, which is characterized in that including the described in any item low-noise amplifiers of claim 1-9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810609088.5A CN108988797B (en) | 2018-06-13 | 2018-06-13 | Low noise amplifier and electronic device |
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|---|---|---|---|
| CN201810609088.5A CN108988797B (en) | 2018-06-13 | 2018-06-13 | Low noise amplifier and electronic device |
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| CN108988797B CN108988797B (en) | 2022-07-12 |
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| CN108988797B (en) | 2022-07-12 |
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