CN108987860B - SIW plane filter - Google Patents
SIW plane filter Download PDFInfo
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- CN108987860B CN108987860B CN201811022672.7A CN201811022672A CN108987860B CN 108987860 B CN108987860 B CN 108987860B CN 201811022672 A CN201811022672 A CN 201811022672A CN 108987860 B CN108987860 B CN 108987860B
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- 239000002184 metal Substances 0.000 claims abstract description 281
- 229910052751 metal Inorganic materials 0.000 claims abstract description 281
- 239000011888 foil Substances 0.000 claims abstract description 118
- 239000000463 material Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000011889 copper foil Substances 0.000 claims description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 2
- 238000003780 insertion Methods 0.000 abstract description 14
- 230000037431 insertion Effects 0.000 abstract description 14
- 230000005540 biological transmission Effects 0.000 abstract description 10
- 230000008054 signal transmission Effects 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 description 8
- 238000004891 communication Methods 0.000 description 6
- 238000004088 simulation Methods 0.000 description 6
- 230000008859 change Effects 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 230000007704 transition Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000005259 measurement Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/20—Frequency-selective devices, e.g. filters
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/20—Frequency-selective devices, e.g. filters
- H01P1/201—Filters for transverse electromagnetic waves
- H01P1/203—Strip line filters
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Abstract
The invention discloses a SIW plane filter, which comprises a top metal foil, a dielectric plate and a bottom metal foil, wherein a left port microstrip outgoing line is arranged on the left side of the top metal foil, a right port microstrip outgoing line is arranged on the right side of the top metal foil, the left port microstrip outgoing line and the right port microstrip outgoing line deviate relative to a horizontal center line, a plurality of first metal through holes are arranged on the periphery of the top metal foil, a left metal through hole is arranged on the left side of the center of the top metal foil, a right metal through hole is arranged on the right side of the center of the top metal foil, a plurality of middle metal through holes are arranged on the vertical center line of the top metal foil, a left clearance groove, a right clearance groove, a left upper metal through hole and a right upper metal through hole are arranged on the surface of the top metal foil, and the first metal through holes, the left metal through holes, the right metal through holes, the middle metal through holes, the left upper metal through holes and the right upper metal through holes are all penetrated through the dielectric plate and the bottom metal foil. The invention has small volume, light weight, small signal transmission loss, low insertion loss and high return loss, and improves the transmission performance.
Description
Technical Field
The invention belongs to the technical field of wireless communication, and particularly relates to a SIW plane filter.
Background
In the years, under the high-speed development of wireless communication technology, the projects related to a microwave communication system are more and more, and a filter is an indispensable component part of a modern microwave relay communication system, a microwave satellite communication system, an electronic countermeasure system and the like, and is also the most important microwave passive device with the highest technical content. With the development of modern electronics technology, available spectrum resources are increasingly strained, so that requirements on frequency selection characteristics of filters are increasingly higher. In order to improve the transmission performance of the filter, the filter is required to have low insertion loss and high return loss, and more importantly, in order to meet the miniaturization trend of modern communication terminals, the filter is required to have smaller volume and weight, and sometimes the size of the filter is even more important than the performance. The insertion loss of the traditional filter is larger, the return loss is smaller, the transmissibility is poorer, and the traditional rectangular waveguide has large volume and large weight. Therefore, there is an urgent need for a miniaturized and high-transmission filter to solve the above-mentioned problems.
Disclosure of Invention
The invention aims to solve the technical problems of providing the SIW plane filter aiming at the defects of the prior art, and the SIW plane filter has the advantages of simple structure, small volume, light weight, low cost, small signal transmission loss, low insertion loss and high return loss, and improves the transmission performance of the filter.
In order to achieve the technical purpose, the invention adopts the following technical scheme:
the SIW planar filter comprises a top metal foil, a dielectric plate and a bottom metal foil, wherein the top metal foil, the dielectric plate and the bottom metal foil are tightly attached from top to bottom, a left port microstrip lead-out line is arranged on the left side of the top metal foil, a right port microstrip lead-out line is arranged on the right side of the top metal foil, the left port microstrip lead-out line and the right port microstrip lead-out line deviate relative to the horizontal central line of the top metal foil, a first slot line and a second slot line are arranged on the left side of the top metal foil, the left port microstrip lead-out line is positioned between the first slot line and the second slot line, a third slot line and a fourth slot line are arranged on the right side of the top metal foil, a plurality of first metal through holes are arranged on the periphery of the top metal foil and are positioned on the upper side and the lower side of the left port microstrip lead-out line and the right port microstrip lead-out line, the left side at top layer metal foil center has been seted up left metal via hole and the right side at center has been seted up right metal via hole, left side metal via hole and right metal via hole all are located the horizontal center line of top layer metal foil, the middle part on the vertical center line of top layer metal foil is equipped with a plurality of well metal via holes, left clearance recess and right clearance recess have been seted up on the surface of top layer metal foil, left clearance recess is located between left metal via hole and the first slot line, right clearance recess is located between right metal via hole and the third slot line, upper left metal via hole and upper right metal via hole have been seted up on the surface of top layer metal foil, upper left metal via hole is located the top of first slot line and is located the left side of left clearance recess, upper right metal via hole is located the top of third slot line and is located the right side of right clearance recess, first metal via hole, left metal via hole, the right metal via hole, the middle metal via hole, the left upper metal via hole and the right upper metal via hole penetrate through the top metal foil, the dielectric plate and the bottom metal foil.
As a further improved technical scheme of the invention, the left port microstrip outgoing line and the right port microstrip outgoing line are symmetrically arranged relative to the vertical central line of the top metal foil, the left metal via hole and the right metal via hole are symmetrically arranged relative to the vertical central line of the top metal foil, the left clearance groove and the right clearance groove are symmetrically arranged relative to the vertical central line of the top metal foil, and the left upper metal via hole and the right upper metal via hole are symmetrically arranged relative to the vertical central line of the top metal foil.
As a further improved technical scheme of the invention, the first groove line, the second groove line, the third groove line and the fourth groove line have the same structure and are L-shaped, the first groove line and the second groove line are symmetrically arranged relative to the horizontal direction, and the third groove line and the fourth groove line are symmetrically arranged relative to the horizontal direction.
As a further improved technical scheme of the invention, the left port microstrip outgoing line and the right port microstrip outgoing line are connected with SMA connectors.
As a further improved technical scheme of the invention, the left port microstrip outgoing line and the right port microstrip outgoing line are SIW characteristic impedance matching microstrip lines with 50 ohms.
As a further improved technical scheme of the invention, the first metal via hole, the left metal via hole, the right metal via hole, the middle metal via hole, the left upper metal via hole and the right upper metal via hole are all round, penetrate through holes of the top metal foil, the dielectric plate and the bottom metal foil, are subjected to metallization treatment, and are connected with the top metal foil and the bottom metal foil.
As a further improved technical scheme of the invention, the diameters of the first metal through holes are 0.6mm, the center distance between two adjacent first metal through holes is 1mm, the diameters of the left metal through hole, the right metal through hole, the middle metal through hole, the upper left metal through hole and the upper right metal through hole which are loaded in the inside are all 0.4mm, and 3 middle metal through holes are arranged.
As a further improved technical scheme of the invention, the top metal foil and the bottom metal foil are both copper foils, the dielectric plate is made of F4B material and has a relative dielectric constant of 2.65, the thickness of the dielectric plate is 0.508mm, and the thicknesses of the left port microstrip outgoing line and the right port microstrip outgoing line are 0.035mm.
As a further improved technical scheme of the invention, the length L of the top metal foil 1 Width W of top metal foil =22 mm 1 Distance L between upper end of third slot line and lower end of fourth slot line parallel to vertical direction =19 mm 2 Distance W between upper edge of third slot line and lower edge of fourth slot line parallel to horizontal direction =5.84 mm 4 Width W of right port microstrip lead-out line =2.35 mm 2 The long side of the right clearance groove is parallel to the vertical direction and the short side is parallel to the horizontal direction, wherein the length L of the right clearance groove is =1.55 mm 3 =5.22 mm, width of right clearance groove W 3 Horizontal distance L between center of left metal via and center of middle metal via =0.5 mm 5 Vertical distance D between center of left metal via and center of uppermost middle metal via =2.4mm 2 Distance D between centers of metal vias in 2 adjacent vias =1.5mm 1 Vertical distance L between second slot line and center of first metal via hole on left side =1 mm 6 The horizontal distance between the left side of the top metal foil and the left side of the dielectric plate is equal to the horizontal distance between the right side of the top metal foil and the right side of the dielectric plate, and the horizontal distance L is =7.1 mm 7 Vertical spacing S between lower edge of left port microstrip lead wire and lower edge of top metal foil =4.5 mm 1 Vertical spacing S between upper edge of first slot line parallel to horizontal direction and upper left metal via =6.38 mm 2 Vertical spacing S between lower end of left clearance groove and center of center metal via located below =2.27 mm 3 =5.3mm。
The beneficial effects of the invention are as follows:
the transition structure of the left port microstrip outgoing line and the right port microstrip outgoing line adopted by the invention not only can realize transition, transmission and conversion of energy, but also is beneficial to effective integration of the filter, thereby realizing further miniaturization of the final structure; the transition structure of the left port microstrip outgoing line and the right port microstrip outgoing line overcomes the reflection problem of direct transition, solves the problem of large structure of conical transition, and has small influence on an internal field; the left port microstrip outgoing line and the right port microstrip outgoing line deviate relative to the horizontal center line of the top metal foil, so that the passband of the filter is wider; the invention realizes better return loss and improves the transmission characteristic by designing the first metal via hole, the left metal via hole, the right metal via hole and the middle metal via hole; the integral structure design of the invention can ensure that the return loss reaches the maximum value when the insertion loss reaches the minimum value; the filter frequency band is between 10.5 and 12.5GHz, the center frequency is about 11GHz, the insertion loss is lower than 0.3dB, the return loss is greater than 30dB, two transmission zeros are generated, and the filter is a high-performance SIW plane filter with low insertion loss and high return loss; in addition, the invention has small volume, light weight and low cost, is a plane circuit, is easy to be highly integrated with other plane circuits, and is favorable for further realizing high performance and miniaturization of radio frequency and microwave circuit design. In summary, the present invention improves miniaturization of the SIW structure and further optimizes its transmission characteristics.
Drawings
Fig. 1 is a schematic diagram of the front structure of the present invention.
Fig. 2 is a schematic view of the back structure of the present invention.
Fig. 3 is a dimension identification chart of the present invention.
Fig. 4 is a frequency characteristic diagram of the filter of the present invention.
Fig. 5 is a graph showing the comparison between actual measurement and simulation of return loss of a filter according to the present invention.
Fig. 6 is a graph showing the comparison of the actual measurement and simulation of the insertion loss of the filter according to the present invention.
Detailed Description
The following further describes embodiments of the present invention with reference to fig. 1 to 6:
referring to fig. 1 and 2, the present embodiment provides a SIW planar filter, which is composed of a three-layer structure, and includes a top metal foil 1, a dielectric plate 2 and a bottom metal foil 3, wherein the top metal foil 1, the dielectric plate 2 and the bottom metal foil 3 are tightly attached from top to bottom, the top metal foil 1 and the bottom metal foil 3 are both made of copper foil, the dielectric plate 2 is made of F4B material and has a relative dielectric constant of 2.65, and the thickness of the dielectric plate 2 is 0.508mm.
Referring to fig. 1, a left port microstrip lead-out line 4 is arranged on the left side of a top metal foil 1, a right port microstrip lead-out line 5 is arranged on the right side of the top metal foil 1, the left port microstrip lead-out line 4 and the right port microstrip lead-out line 5 deviate relative to the horizontal center line of the top metal foil 1, a first slot line 6 and a second slot line 7 are arranged on the left side of the top metal foil 1, the left port microstrip lead-out line 4 is positioned between the first slot line 6 and the second slot line 7, and the first slot line 6 is positioned above the second slot line 7; a third slot line 8 and a fourth slot line 9 are arranged on the right side edge of the top metal foil 1, the right port microstrip outgoing line 5 is positioned between the third slot line 8 and the fourth slot line 9, and the third slot line 8 is positioned above the fourth slot line 9. The left port microstrip outgoing line 4 and the right port microstrip outgoing line 5 are symmetrically arranged relative to the vertical center line of the top metal foil 1, and the left port microstrip outgoing line 4 and the right port microstrip outgoing line 5 adopt 50 ohm SIW characteristic impedance matching microstrip lines. The left port microstrip outgoing line 4 and the right port microstrip outgoing line 5 are welded with SMA connectors so as to be connected with a test or a circuit.
In the process of designing the microstrip line, the connection position of the microstrip line and the substrate integrated waveguide has great influence. This is because when the position of the microstrip line changes, not only the electric field inside the substrate integrated waveguide changes, but also the external coupling coefficient is affected by it. Referring to fig. 1, the left port microstrip lead-out line 4 and the right port microstrip lead-out line 5 are positioned at two sides of the substrate integrated waveguide, and the vertical distance between the central lines of the left port microstrip lead-out line 4 and the right port microstrip lead-out line 5 and the horizontal central line of the top metal foil 1 is changed, so that the influence of the change of the vertical distance on the transmission frequency is observed. When the left port microstrip lead-out line 4 and the right port microstrip lead-out line 5 are positioned at the midpoint of the horizontal center line of the top metal foil 1, only the sum mode is excited (two modes of the sum mode transverse electric mode TE); when the left port microstrip lead-out line 4 and the right port microstrip lead-out line 5 deviate from the horizontal center line, the mode is excited, so that the passband of the filter is wider, and the mode must be excited, so that the left port microstrip lead-out line 4 and the right port microstrip lead-out line 5 deviate from the horizontal center line of the top metal foil 1. The thickness of the left port microstrip outgoing line 4 and the right port microstrip outgoing line 5 is 0.035mm.
Referring to fig. 1, a plurality of first metal vias 10 are arranged around a top metal foil 1 of the siw planar filter, and the first metal vias 10 are located on upper and lower sides of a left port microstrip outgoing line 4 and a right port microstrip outgoing line 5. The first metal via 10 penetrates the top metal foil 1, the dielectric plate 2 and the bottom metal foil 3. The diameter of the first metal via 10 is 0.6mm, and the center distance between two adjacent first metal vias 10 is 1mm.
In order to change the field distribution and the resonance frequency of the main mode when designing the substrate integrated waveguide filter, a metal via hole is constructed in the cavity of the base structure, in this embodiment, a left metal via hole 11 is formed on the left side of the center of the top metal foil 1, a right metal via hole 12 is formed on the right side of the center, and both the left metal via hole 11 and the right metal via hole 12 are located on the horizontal center line of the top metal foil 1. The left metal via 11 and the right metal via 12 are symmetrically arranged with respect to the vertical center line of the top metal foil 1. The distance between the left metal via 11 and the center of the top metal foil 1 or the distance between the right metal via 12 and the center of the top metal foil 1 has an influence on the mode and the resonant frequency of the mode, and the distance between the left metal via 11 and the center of the top metal foil 1 or the distance between the right metal via 12 and the center of the top metal foil 1 can be determined by analyzing the change of the resonant frequency of the mode and the mode along with the position of the left metal via 11 or the right metal via 12. If it is desired to change the resonance frequency of a certain mode significantly, the position of the left metal via 11 or the right metal via 12 should be loaded at the strongest of the generated electric field.
A plurality of middle metal vias 13 are provided in the middle of the vertical center line of the top metal foil 1. The left metal via 11, the right metal via 12 and the middle metal via 13 penetrate through the top metal foil 1, the dielectric plate 2 and the bottom metal foil 3.
In order to change the resonant frequency of the main mode, it is also possible to implement by constructing a gap groove on the top metal foil 1, in addition to constructing metal vias (left metal via 11, right metal via 12, and middle metal via 13) inside the substrate integrated waveguide. When the gap grooves are formed in the top metal foil 1, the field distribution and the resonant frequency inside the substrate integrated waveguide are also affected, that is, referring to fig. 1, the surface of the top metal foil 1 is provided with a rectangular left gap groove 14 and a rectangular right gap groove 15, the left gap groove 14 is located between the left metal via 11 and the first slot line 6, and the right gap groove 15 is located between the right metal via 12 and the third slot line 8. The influence of the loaded left and right gap grooves 14 and 15 on the main mode frequency was analyzed by changing the lengths and widths of the left and right gap grooves 14 and 15, and when the values of the lengths and widths of the left or right gap grooves 14 and 15 are larger, the resonance frequency is lower, in other words, the larger the size of the gap groove is, the influence on the field distribution is also increased. Changing the horizontal distance between the left gap groove 14 and the right gap groove 15 and the center of the substrate integrated waveguide respectively, namely changing the position of the gap groove on the horizontal line, so as to analyze the influence of the gap groove on the mode and the mode frequency: after loading the clearance groove, its corresponding frequency will decrease. When the gap grooves are positioned at the strongest electric field, the frequency of the blocked mode of the current on the surface is greatly reduced, and the frequencies of other modes are not changed, so that 2 symmetrical gap grooves (namely a left gap groove 14 and a right gap groove 15) can be loaded at the strongest electric field; the left and right clearance grooves 14, 15 are symmetrically arranged with respect to the vertical center line of the top metal foil 1.
Referring to fig. 1, the top metal foil 1 is provided with an upper left metal via 16 and an upper right metal via 17 on the surface, the upper left metal via 16 is located above the first slot line 6 and on the left side of the left gap groove 14, the upper right metal via 17 is located above the third slot line 8 and on the right side of the right gap groove 15, and the upper left metal via 16 and the upper right metal via 17 penetrate through the top metal foil 1, the dielectric plate 2 and the bottom metal foil 3. The upper left metal via 16 and the upper right metal via 17 are symmetrically arranged with respect to the vertical center line of the top metal foil 1.
Referring to fig. 1, the first slot line 6, the second slot line 7, the third slot line 8 and the fourth slot line 9 in the present embodiment have the same structure and are all L-shaped, the first slot line 6 and the second slot line 7 are symmetrically arranged with respect to the horizontal direction, and the third slot line 8 and the fourth slot line 9 are symmetrically arranged with respect to the horizontal direction.
Referring to fig. 1, in this embodiment, the first metal via 10, the left metal via 11, the right metal via 12, the middle metal via 13, the upper left metal via 16, and the upper right metal via 17 are all circular, and penetrate through the holes of the top metal foil 1, the dielectric plate 2, and the bottom metal foil 3 to be metallized and connected with the top metal foil 1 and the bottom metal foil 3.
In fabricating a SIW bandpass filter, a model is first built in HFSS software, the structure being symmetrical about the perpendicular bisector. The diameter of the first metal via 10 at the periphery of the SIW filter designed in this embodiment is 0.6mm, the center distance between the two first metal vias 10 is 1mm, the diameters of the left metal via 11, the right metal via 12, the middle metal via 13, the upper left metal via 16 and the upper right metal via 17 which are loaded inside are all 0.4mm, and 3 middle metal vias 13 are provided. The values of other important parameters are compared after HFSS simulation optimization, and the value of the values is determined.
Referring to FIG. 3, D in FIG. 3 1 ，D 2 ，L 5 ，L 6 Is four important parameters, and the values of the four unknowns have a considerable influence on the return loss. For testing to obtain the optimal values, optimization was performed in HFSS software with the following results: horizontal spacing L between center of left metal via 11 and center of center metal via 13 5 =2.4 mm; the vertical distance D between the center of the left metal via 11 and the center of the uppermost middle metal via 13 2 Distance D between centers of metal vias 13 in 2 adjacent vias =1.5mm 1 Vertical spacing L between second slot line 7 and center of first metal via 10 located on left side =1 mm 6 =7.1mm。
Specific values of the other parameters in fig. 3 are as follows: length L of top metal foil 1 1 =22 mm; width W of top metal foil 1 1 =19 mm; between the upper end of the third slot line 8 and the lower end of the fourth slot line 9 parallel to the vertical directionDistance L 2 =5.84 mm; a distance W between the upper side of the third slot line 8 and the lower side of the fourth slot line 9 parallel to the horizontal direction 4 =2.35 mm; width W of right port microstrip lead-out line 5 2 =1.55mm; the long side of the right clearance groove 15 is parallel to the vertical direction and the short side is parallel to the horizontal direction, wherein the length L of the right clearance groove 15 3 =5.22 mm; the width of the right clearance groove 15 is W 3 =0.5 mm; the horizontal distance between the left side edge of the top metal foil 1 and the left side edge of the dielectric plate 2 is equal to the horizontal distance between the right side edge of the top metal foil 1 and the right side edge of the dielectric plate 2, and the horizontal distance L 7 =4.5 mm; vertical spacing S between lower edge of left port microstrip lead-out line 4 and lower edge of top metal foil 1 1 =6.38 mm; vertical spacing S between upper edge of first slot line 6 and upper left metal via 16 parallel to horizontal direction 2 =2.27 mm; vertical spacing S between lower end of left clearance groove 14 and center of center metal via 13 located below 3 =5.3mm。
Simulations were performed in HFSS to see return loss and insertion loss, and the results are as follows, and referring to fig. 4, it is not difficult to see that the designed filter basically meets the requirements of the design index. From fig. 4, it can be seen that the filter band is between 10.5 and 12.5GHz, the center frequency is around 11GHz, the insertion loss is lower than 0.3dB, the return loss is greater than 30dB, and two transmission zeros are generated.
The return loss and the insertion loss of the physical SIW planar filter were tested by using a network analyzer, and the test results are shown in fig. 5 and 6: wherein the solid line is the simulation result and the dotted line is the physical test result. When the insertion loss reaches the minimum value (-1.3 dB), the return loss also reaches the maximum value (-30 dB), the center band is located around 11.5G, the bandwidth reaches 1.5GHz and two transmission zeros are generated, which means that the performance of the filter manufactured according to the embodiment is ensured. In the figure, the simulation result and the entity test result are basically identical. Wherein the measurement errors are due to actual process variations and unstable electrical constants of the substrate material. If the processing accuracy is improved, the performance of the filter is also improved.
The invention designs a SIW planar filter with low insertion loss, high return loss, frequency band of 10-12GHz and center frequency of 11GHz, which solves the technical problems of relatively large insertion loss and relatively small return loss of the filter in the prior art, thus causing relatively poor transmissibility. The invention belongs to a high-performance band-pass filter.
The scope of the present invention includes, but is not limited to, the above embodiments, and any alterations, modifications, and improvements made by those skilled in the art are intended to fall within the scope of the invention.
Claims (7)
1. A SIW planar filter, characterized by: including top layer metal foil (1), medium board (2) and bottom metal foil (3), top layer metal foil (1), medium board (2) and bottom metal foil (3) are closely laminated from the top down, the left side of top layer metal foil (1) is equipped with left port microstrip lead-out wire (4), the right side is equipped with right port microstrip lead-out wire (5) and left port microstrip lead-out wire (4) and right port microstrip lead-out wire (5) take place the skew relative horizontal central line of top layer metal foil (1), first slot line (6) and second slot line (7) have been seted up on the left side of top layer metal foil (1) and left port microstrip lead-out wire (4) are located in the middle of first slot line (6) and second slot line (7), third slot line (8) and fourth slot line (9) have been seted up on the right side of top layer metal foil (1) and right side microstrip lead-out wire (5) are located in the middle of third slot line (8) and fourth slot line (9), the center line (12) have been seted up on top layer metal foil (1) around being provided with a plurality of first metal via hole (10) and left and right port microstrip lead-out wire (4) are located on the right side of top layer metal foil (1), the left metal via hole (11) and the right metal via hole (12) are both positioned on the horizontal center line of the top metal foil (1), a plurality of middle metal via holes (13) are arranged in the middle of the vertical center line of the top metal foil (1), a left clearance groove (14) and a right clearance groove (15) are formed in the surface of the top metal foil (1), the left clearance groove (14) is positioned between the left metal via hole (11) and the first groove line (6), the right clearance groove (15) is positioned between the right metal via hole (12) and the third groove line (8), a left upper metal via hole (16) and a right upper metal via hole (17) are formed in the surface of the top metal foil (1), the left upper metal via hole (16) is positioned above the first groove line (6) and is positioned on the left side of the left clearance groove (14), the right upper metal via hole (17) is positioned above the third groove line (8) and is positioned on the right side of the right clearance groove (15), and the first metal via hole (10), the left metal via hole (11), the right upper metal via hole (12), the right upper metal via hole (17) and the top metal via hole (3) penetrate through the top metal foil (3) and the top metal via hole (17) and the bottom (2) of the top metal foil (1) respectively.
The left port microstrip outgoing line (4) and the right port microstrip outgoing line (5) are symmetrically arranged relative to the vertical center line of the top-layer metal foil (1), the left metal via hole (11) and the right metal via hole (12) are symmetrically arranged relative to the vertical center line of the top-layer metal foil (1), the left clearance groove (14) and the right clearance groove (15) are symmetrically arranged relative to the vertical center line of the top-layer metal foil (1), and the left upper metal via hole (16) and the right upper metal via hole (17) are symmetrically arranged relative to the vertical center line of the top-layer metal foil (1);
the first groove line (6), the second groove line (7), the third groove line (8) and the fourth groove line (9) are identical in structure and are L-shaped, the first groove line (6) and the second groove line (7) are symmetrically arranged relative to the horizontal direction, and the third groove line (8) and the fourth groove line (9) are symmetrically arranged relative to the horizontal direction.
2. The SIW planar filter of claim 1, wherein: and the left port microstrip outgoing line (4) and the right port microstrip outgoing line (5) are connected with SMA connectors.
3. The SIW planar filter of claim 2, wherein: the left port microstrip outgoing line (4) and the right port microstrip outgoing line (5) are SIW characteristic impedance matching microstrip lines with 50 ohms.
4. The SIW planar filter of claim 1, wherein: the first metal via hole (10), the left metal via hole (11), the right metal via hole (12), the middle metal via hole (13), the left upper metal via hole (16) and the right upper metal via hole (17) are all round, penetrate through holes of the top metal foil (1), the dielectric plate (2) and the bottom metal foil (3), are subjected to metallization treatment, and are connected with the top metal foil (1) and the bottom metal foil (3).
5. The SIW planar filter of claim 4, wherein: the diameters of the first metal through holes (10) are 0.6mm, the center distance between two adjacent first metal through holes (10) is 1mm, the diameters of the left metal through hole (11), the right metal through hole (12), the middle metal through hole (13), the upper left metal through hole (16) and the upper right metal through hole (17) which are loaded in the inside are all 0.4mm, and the number of the middle metal through holes (13) is 3.
6. The SIW planar filter according to any one of claims 1 to 5, characterized in that: copper foil is adopted for both the top metal foil (1) and the bottom metal foil (3), F4B material is adopted for the dielectric plate (2) and the relative dielectric constant is 2.65, the thickness of the dielectric plate (2) is 0.508mm, and the thicknesses of the left port microstrip outgoing line (4) and the right port microstrip outgoing line (5) are 0.035mm.
7. The SIW planar filter of claim 6, wherein: length L of top metal foil (1) 1 Width W of top metal foil (1) =22 mm 1 Distance L between upper end of third slot line (8) and lower end of fourth slot line (9) parallel to vertical direction =19 mm 2 =5.84 mm, the spacing W between the upper edge of the third slot line (8) and the lower edge of the fourth slot line (9) parallel to the horizontal direction 4 =2.35 mm, right endWidth W of mouth microstrip lead-out wire (5) 2 The long side of the right clearance groove (15) is parallel to the vertical direction and the short side is parallel to the horizontal direction, wherein the length L of the right clearance groove (15) 3 =5.22 mm, width of right clearance groove (15) is W 3 The horizontal distance L between the center of the left metal via (11) and the center of the middle metal via (13) 5 The vertical distance D between the center of the left metal via (11) and the center of the uppermost middle metal via (13) =2.4 mm 2 Distance D between centers of metal vias (13) in 2 adjacent vias =1.5mm 1 Vertical spacing L of center of second slot line (7) and first metal via hole (10) at left side 6 The horizontal distance between the left side of the top metal foil (1) and the left side of the dielectric plate (2) is equal to the horizontal distance between the right side of the top metal foil (1) and the right side of the dielectric plate (2) and is equal to the horizontal distance L 7 The vertical spacing S between the lower edge of the left port microstrip lead wire (4) and the lower edge of the top metal foil (1) =4.5 mm 1 =6.38 mm, vertical spacing S between the upper edge of the first slot line (6) parallel to the horizontal direction and the upper left metal via (16) 2 The vertical spacing S between the lower end of the left clearance groove (14) and the center of the center metal via hole (13) positioned below is =2.27 mm 3 =5.3mm。
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| CN112563724A (en) * | 2020-12-04 | 2021-03-26 | 西安电子科技大学 | Low-profile half-mode substrate integrated waveguide filter antenna with high frequency selectivity |
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| CN105932379A (en) * | 2016-06-17 | 2016-09-07 | 中国电子科技集团公司第十研究所 | SIW (substrate integrated waveguide) filter with ports on different planes |
| CN106410337A (en) * | 2016-09-29 | 2017-02-15 | 上海航天测控通信研究所 | Single-cavity substrate integrated waveguide multi-transmission-zero-point filter |
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| CN106410337A (en) * | 2016-09-29 | 2017-02-15 | 上海航天测控通信研究所 | Single-cavity substrate integrated waveguide multi-transmission-zero-point filter |
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| 基于SIW和槽线DGS的Wi-Fi带通滤波器的设计;张衡伏;杨永侠;;计算机与数字工程(第12期);全文 * |
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