CN108962932A - 1D1R memory of single stacked structure and preparation method thereof - Google Patents
1D1R memory of single stacked structure and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 30
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 230000006870 function Effects 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 6
- 238000002207 thermal evaporation Methods 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 3
- 230000014759 maintenance of location Effects 0.000 description 10
- 238000012360 testing method Methods 0.000 description 10
- 238000006243 chemical reaction Methods 0.000 description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- -1 oxonium ion Chemical class 0.000 description 2
- 238000011056 performance test Methods 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000008569 process Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/257—Multistable switching devices, e.g. memristors having switching assisted by radiation or particle beam, e.g. optically controlled devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention provides a kind of 1D1R memory, it include: Si substrate layer, the metal electrode layer on metal oxide layer and the metal oxide layer on the Si substrate layer, wherein, the Si substrate layer and the metal oxide layer constitute pn heterojunction structure, the resistivity of the Si substrate layer is 0.01-0.05 Ω * cm, and the resistivity of the metal oxide layer is 104‑105Ω * cm, the work function of the metal electrode layer and the fermi level of the metal oxide layer match.1D1R memory of the invention is single stacked structure, and preparation process is simple, and longitudinal 3D integration density is high.
Description
Technical field
The invention belongs to area information storages more particularly to the 1D1R memory of single stacked structure and preparation method thereof.
Background technique
With the development of the society, traditional nonvolatile memory is no longer satisfied people to high speed, high density, low
Therefore the requirement of energy consumption is badly in need of the nonvolatile memory of exploitation a new generation.Resistive formula random access memory (RRAM) is due to its knot
The characteristic that structure is simple, storage density is high, conversion speed is high, energy consumption is lower and the retention time is long non-volatile is deposited numerous
Show one's talent in reservoir.
In order to realize the large-area applications of RRAM device, crucial be exactly realize the integrated of a large amount of RRAM devices, but this
Kind integrated circuit device arranged vertically and horizontally can encounter string sound problem.In order to overcome the problems, such as string sound, it has been proposed that some device junctions
Structure, such as one memory (1D1R) of a Diode series, selector are connected a memory (1S1R) and complementary
Resistance converts (CRS).Wherein, traditional 1D1R device is usually to be connected using RRAM and diode, this nothing
It doubts the complexity that will increase preparation process and makes higher cost.
Summary of the invention
Therefore, it is an object of the invention to overcome the defect of the above-mentioned prior art, a kind of 1D1R memory is provided, comprising:
The metal electrode layer on metal oxide layer and the metal oxide layer on Si substrate layer, the Si substrate layer,
In, the Si substrate layer and the metal oxide layer constitute pn heterojunction structure, and the resistivity of the Si substrate layer is 0.01-
0.05 Ω * cm, the resistivity of the metal oxide layer are 104-105Ω * cm, the work function of the metal electrode layer with it is described
The fermi level of metal oxide layer matches.
1D1R memory according to the present invention, it is preferable that the metal oxide layer with a thickness of 40-100nm.
1D1R memory according to the present invention, it is preferable that the metal oxide layer with a thickness of 60nm.
1D1R memory according to the present invention, it is preferable that the metal electrode layer with a thickness of 80-150nm.
1D1R memory according to the present invention, it is preferable that the shape of the metal electrode layer is circular array.
1D1R memory according to the present invention, it is preferable that the material of the metal oxide layer be p-type NiO, N-shaped ZnO or
N-shaped TiO.
1D1R memory according to the present invention, it is preferable that the material of the metal electrode layer is Pt or Al.
The present invention also provides a kind of preparation methods of 1D1R memory, include the following steps:
Step 1: metal oxide layer is prepared on Si substrate layer using magnetically controlled sputter method；
Step 2: metal electrode layer is prepared on the metal oxide layer using thermal evaporation method.
The preparation method of 1D1R memory according to the present invention, it is preferable that the step 1 further includes cleaning the Si lining
Bottom.
Compared with prior art, 1D1R memory of the invention is single stacked structure, has rectification and resistive simultaneously
Characteristic effectively inhibits the problem of concatenating in integrating process, simplifies preparation process, increases 3D integration density.
Detailed description of the invention
Embodiments of the present invention is further illustrated referring to the drawings, in which:
Fig. 1 is the structural schematic diagram according to the 1D1R memory of first embodiment of the invention.
Fig. 2 is the I-E characteristic test curve figure according to the 1D1R memory of first embodiment of the invention.
Fig. 3 is to restrain oneself characteristic test figure according to the resistance of the 1D1R memory of first embodiment of the invention.
Fig. 4 is the resistance retention performance test chart according to the 1D1R memory of first embodiment of the invention.
Fig. 5 is the structural schematic diagram according to the 1D1R memory of second embodiment of the invention.
Fig. 6 is the I-E characteristic test curve figure according to the 1D1R memory of second embodiment of the invention.
Fig. 7 is to restrain oneself characteristic test figure according to the resistance of the 1D1R memory of second embodiment of the invention.
Fig. 8 is the resistance retention performance test chart according to the 1D1R memory of second embodiment of the invention.
Fig. 9 is the schematic diagram of 1D1R memory according to the present invention.
Specific embodiment
In order to make the purpose of the present invention, technical solution and advantage are more clearly understood, and are passed through below in conjunction with attached drawing specific real
Applying example, the present invention is described in more detail.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention,
It is not intended to limit the present invention.
First embodiment
The embodiment provides a kind of 1D1R memory of single stacked structure, and structure is as shown in Figure 1, include that N-shaped Si is served as a contrast
Pt film on bottom, the p-type NiO film of N-shaped Si substrate and p-type NiO film, wherein the electricity of the N-shaped Si substrate
Resistance rate is about 0.01-0.05 Ω * cm, and the resistivity of the p-type NiO film is about 104-105Ω * cm, thickness are about 60nm, institute
The circular array that the thickness for stating Pt film is about 150nm, shape is 400 μm of diameter.
In this embodiment, N-shaped Si substrate and p-type NiO film constitute pn heterojunction structure (1D), so that being formed by device
With rectification characteristic, meanwhile, N-shaped Si substrate may be used as hearth electrode, p-type NiO film due to its low-resistivity and high conductivity
Due to its high resistivity and low conductivity may be used as change resistance layer (1R) realize device high low-resistance conversion；Pt film is used as gold
Belong to film top electrode, work function is matched with the fermi level of p-type NiO film, to reduce Pt film and p-type NiO film
Between potential barrier influence.
The preparation method of the 1D1R memory of the single stacked structure of the present embodiment includes the following steps:
Step 1: it uses and either physically or chemically N-shaped Si substrate is started the cleaning processing；
Step 2: the p-type NiO film that deposition thickness is about 60nm on N-shaped Si substrate using magnetically controlled sputter method, specifically
Condition are as follows: room temperature is lower than 5.0 × 10-4The base vacuum of Pa, the high purity oxygen gas that ratio is 1:1 and sputtering argon, 2Pa
The sputtering power of growth pressure, NiO ceramic sputter targets and 90W；
Step 3: using thermal evaporation method evaporation thickness on p-type NiO film is the Pt film of 150nm as top electrode,
Make 400 μm of shape diameter of circular array of top electrode using mask plate, thermal evaporation vacuum degree is 3.0 × 10-4Pa, final
N is arrived+- Si/p-NiO/Pt resistive device, i.e., the 1D1R memory of single stacked structure, symbol "+" indicate heavily doped.
Fig. 2 shows the n of embodiment preparation+The I-E characteristic test curve of-Si/p-NiO/Pt resistive device.
Rated current is positive direction from p-type NiO to the direction of N-shaped Si.Metal oxide NiO is as a kind of semiconductor material, so that just
The resistive device of beginning illustrates a high resistance state.Figure it is seen that when applying a positive scanning voltage to device
When (0-8V), the unlatching of device is realized after the forward bias for applying about 7V, to be converted into low resistance state from high-impedance state.When
When applying positive scanning voltage (0-5V) again, device realizes the closing of device in the forward bias of about 4V, from low-resistance
State has been returned to high-impedance state, completes the circulation of primary high low resistance state.Additionally, it was found that rectification spy is all presented in high low resistance state in device
Property, the 1D1R conversion of device may be implemented.The present inventor has also carried out resistive loop test and resistance state repeatedly to the device
Retention time test, is read out the high low resistance of device under the voltage of 2V.Fig. 3 and Fig. 4 respectively shows the embodiment
The n of preparation+The resistance of-Si/p-NiO/Pt resistive device restrains oneself and retention performance, after the conversion of continuous 100 resistance, high resistant
The sign of any decline is not occurred with low-resistance.In addition, device has good retention performance, 104The high resistant of device after s
It is kept approximately constant with low-resistance.
Second embodiment
The embodiment provides the 1D1R memory of another single stacked structure, and structure is as shown in figure 5, include p-type Si
Substrate, the N-shaped ZnO film of p-type Si substrate and the Al film on N-shaped ZnO film, wherein the p-type Si substrate
Resistivity is about 0.01-0.05 Ω * cm, and the resistivity of the N-shaped ZnO film is about 104-105Ω * cm, thickness are about 100nm,
The thickness of the Al film is about 80nm.
In this embodiment, p-type Si substrate and N-shaped ZnO film constitute pn heterojunction structure (1D), so that being formed by device
With rectification characteristic, meanwhile, p-type Si substrate may be used as hearth electrode, N-shaped ZnO film due to its low-resistivity and high conductivity
Due to its high resistivity and low conductivity may be used as change resistance layer (1R) realize device high low-resistance conversion；Al film is used as gold
Belong to film top electrode, work function is matched with the fermi level of N-shaped ZnO film, to reduce Al film and N-shaped ZnO film
Between potential barrier influence.
The preparation method of the 1D1R memory of the single stacked structure of the present embodiment includes the following steps:
Step 1: it uses and either physically or chemically p-type Si substrate is started the cleaning processing；
Step 2: using the magnetically controlled sputter method N-shaped ZnO film that deposition thickness is about 100nm on p-type Si substrate, tool
Concrete conditions in the establishment of a specific crime are as follows: room temperature is lower than 5.0 × 10-4The base vacuum of Pa, the high purity oxygen gas and sputtering argon, 2Pa that ratio is 1:1
Growth pressure, ZnO ceramic sputter targets and 90W sputtering power；
Step 3: using thermal evaporation method evaporation thickness on p-type ZnO film is the Al film of 80nm as top electrode,
Thermal evaporation vacuum degree is 3.0 × 10-4Pa has finally obtained p+- Si/n-ZnO/Al resistive device.
Fig. 6 shows the p of embodiment preparation+The I-E characteristic test curve of-Si/n-ZnO/Al resistive device.
Rated current is positive direction from p-type Si to the direction of N-shaped ZnO.Metal oxide ZnO is as a kind of semiconductor material, so that just
One high resistance state of the device exhibits of beginning.From fig. 6, it can be seen that when applying a positive scanning voltage (0- to device
When 8V), device realizes unlatching after the forward bias of about 7V, to be converted into low resistance state from high-impedance state.When applying one again
When scanning voltage (0-5V) of a forward direction, device realizes closing in the forward bias of about 3.7V, has been returned to height from low resistance state
Resistance state completes the circulation of primary high low resistance state.In addition, rectification characteristic is all presented in high low resistance state in device, device is realized
1D1R conversion.The present inventor has carried out resistive loop test and the test of resistance state retention time repeatedly to this device.Fig. 7 and Fig. 8
The resistance for respectively showing device restrains oneself and retention performance, and it is 1V that the high low resistance of device, which reads voltage,.In continuous 100 electricity
After resistance conversion, high low-resistance does not occur the sign of any decline.In addition, device has good retention performance, 104After s
The high low-resistance of device is kept approximately constant.
Fig. 9 is the schematic diagram of 1D1R memory according to the present invention, and it illustrates resistive models, when forward voltage acts on
When p-type layer side, with the increase of voltage, pn-junction can be turned on, electric field main function to sull.Due to the work of electric field
With wherein oxonium ion can migrate, and will form conductive filament channel inside oxide, and device is converted to low-resistance by high-impedance state
State.Due to the influence of built in field, oxonium ion is difficult to migrate in depletion region, therefore does not form conductive filament in depletion region,
Device still has rectification characteristic under low resistance state.When another voltage functioning devices, due to the effect of Joule heat, conductive filament
It can blow, device is returned to high-impedance state.Realize 1D1R conversion.
According to other embodiments of the invention, intermediate change resistance layer can use metal oxide well known in the art, as long as
Its resistivity meets 104-105Ω * cm, such as TiO.In addition, the doping type phase of Si substrate layer and metal oxide layer
Instead, to constitute pn heterojunction structure.
According to other embodiments of the invention, the metal oxide layer with a thickness of 40-100nm.
According to other embodiments of the invention, top electrode layer can use other any metals well known in the art, as long as
The fermi level of its work function and metal oxide layer matches.In addition, the shape to top electrode layer does not limit, it can
To use arbitrary shape well known in the art, the area of top electrode layer is the smaller the better.
It is according to the present invention single compared to a traditional diode and a concatenated 1D1R device of resistive formula memory
The 1D1R memory of stacked structure simplifies preparation process, and can longitudinally increase 3D integration density.
Although the present invention has been described by means of preferred embodiments, the present invention is not limited to described here
Embodiment, without departing from the present invention further include made various changes and variation.
Claims (9)
1. a kind of 1D1R memory, comprising: metal oxide layer and the metal oxygen on Si substrate layer, the Si substrate layer
Metal electrode layer on compound layer, wherein the Si substrate layer and the metal oxide layer constitute pn heterojunction structure, described
The resistivity of Si substrate layer is 0.01-0.05 Ω * cm, and the resistivity of the metal oxide layer is 104-105Ω * cm, the gold
The fermi level of the work function and the metal oxide layer that belong to electrode layer matches.
2. 1D1R memory according to claim 1, wherein the metal oxide layer with a thickness of 40-100nm.
3. 1D1R memory according to claim 2, wherein the metal oxide layer with a thickness of 60nm.
4. 1D1R memory according to claim 1, wherein the metal electrode layer with a thickness of 80-150nm.
5. 1D1R memory according to claim 1, wherein the shape of the metal electrode layer is circular array.
6. 1D1R memory according to any one of claim 1 to 5, wherein the material of the metal oxide layer is p
Type NiO, N-shaped ZnO or N-shaped TiO.
7. 1D1R memory according to any one of claim 1 to 5, wherein the material of the metal electrode layer is Pt
Or Al.
8. a kind of preparation method of 1D1R memory described in any one of -7 according to claim 1, includes the following steps:
Step 1: metal oxide layer is prepared on Si substrate layer using magnetically controlled sputter method；
Step 2: metal electrode layer is prepared on the metal oxide layer using thermal evaporation method.
9. according to the method described in claim 8, wherein, the step 1 further includes cleaning the Si substrate layer.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113643741A (en) * | 2021-08-16 | 2021-11-12 | 湖北大学 | Logic operation unit and operation method based on 1S1R |
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| CN101414481A (en) * | 2008-11-25 | 2009-04-22 | 中国科学院上海微***与信息技术研究所 | Phase-change memory cell based on SiSb composite material |
| CN102214790A (en) * | 2011-06-10 | 2011-10-12 | 清华大学 | Resistive random access memory with self-rectifying effect |
| CN103579499A (en) * | 2012-08-10 | 2014-02-12 | 中国科学院微电子研究所 | Resistive random access memory device with rectification characteristic and manufacturing method thereof |
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- 2017-05-24 CN CN201710372385.8A patent/CN108962932A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101414481A (en) * | 2008-11-25 | 2009-04-22 | 中国科学院上海微***与信息技术研究所 | Phase-change memory cell based on SiSb composite material |
| CN102214790A (en) * | 2011-06-10 | 2011-10-12 | 清华大学 | Resistive random access memory with self-rectifying effect |
| CN103579499A (en) * | 2012-08-10 | 2014-02-12 | 中国科学院微电子研究所 | Resistive random access memory device with rectification characteristic and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113643741A (en) * | 2021-08-16 | 2021-11-12 | 湖北大学 | Logic operation unit and operation method based on 1S1R |
| CN113643741B (en) * | 2021-08-16 | 2023-12-15 | 湖北大学 | 1S 1R-based logic operation unit and operation method |
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