CN108962767A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

Info

Publication number
CN108962767A
CN108962767A CN201710363176.7A CN201710363176A CN108962767A CN 108962767 A CN108962767 A CN 108962767A CN 201710363176 A CN201710363176 A CN 201710363176A CN 108962767 A CN108962767 A CN 108962767A
Authority
CN
China
Prior art keywords
substrate
plastic packaging
semiconductor structure
forming method
packaging layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710363176.7A
Other languages
English (en)
Other versions
CN108962767B (zh
Inventor
陈福成
陆建刚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201710363176.7A priority Critical patent/CN108962767B/zh
Priority to US15/986,023 priority patent/US10685831B2/en
Publication of CN108962767A publication Critical patent/CN108962767A/zh
Application granted granted Critical
Publication of CN108962767B publication Critical patent/CN108962767B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3731—Ceramic materials or glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/11013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the bump connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

本发明提供一种半导体结构及其形成方法，其中，所述形成方法包括：提供衬底，所述衬底包括相对的第一面和第二面，所述第一面为功能面；在所述衬底第一面上形成塑封层；形成所述塑封层之后，对所述衬底第二面进行减薄处理。其中，进行所述减薄处理之前，在所述衬底第一面上形成塑封层。所述塑封层能够在所述减薄处理过程中，对所述衬底进行支撑，抑制塑封层发生褶皱或破碎。所述塑封层还用作对所述衬底进行封装的材料，所述减薄处理之后，所述塑封层不需要去除，从而能够简化工艺流程，降低工艺成本。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
随着集成电路集成度的提高，封装技术越来越成为了微电子行业关注的热点。晶圆减薄是先进封装技术的组成部分，在芯片封装中具有重要应用。
减薄后的晶圆厚度很小，为了防止晶圆发生褶皱或断裂。现有技术对晶圆进行减薄的步骤包括：提供载片；将晶圆与载片进行键合；将晶圆与载片进行键合之后，对所述载片暴露出的晶圆表面进行减薄处理；所述减薄处理之后，对所述载片进行解键合，从而去除所述载片。
然而，现有的半导体结构的形成方法工艺复杂，生产成本较高。
发明内容
本发明解决的问题是提供一种半导体结构及其形成方法，能够简化工艺流程，降低生产成本。
为解决上述问题，本发明提供一种半导体结构的形成方法，包括：提供衬底，所述衬底包括相对的第一面和第二面，所述第一面为功能面；在所述衬底第一面上形成塑封层；形成所述塑封层之后，对所述衬底第二面进行减薄处理。
可选的，所述塑封层的材料为聚合物。
可选的，形成所述塑封层的步骤包括：在所述衬底第一面上形成前驱体；对所述前驱体进行加热处理，使所述前驱体固化，形成所述塑封层。
可选的，所述塑封层的厚度为100μm～600μm。
可选的，所述减薄处理的工艺包括：化学机械抛光工艺或TAIKO工艺。
可选的，所述减薄处理之前，还包括：在所述塑封层上形成覆盖层；所述减薄处理之后，去除所述覆盖层。
可选的，所述覆盖层的材料为玻璃。
可选的，所述减薄处理之后，还包括：在所述塑封层上形成第一连接层和位于所述第一连接层上的第一散热板。
可选的，所述减薄处理之后，还包括：在所述衬底第二面上形成第二连接层和第二散热板，所述第二连接层位于所述衬底第二面和所述第二散热板之间。
可选的，所述减薄处理之后，还包括：在所述衬底第二面上形成第二连接层和第二散热板，所述第二连接层位于所述衬底第二面和所述第二散热板之间，所述第一散热板和第二散热板的材料为陶瓷。
可选的，所述衬底第一面上具有焊盘；形成所述塑封层之前，还包括：在所述焊盘上形成连接柱。
可选的，所述连接柱的材料为铜或铝。
可选的，形成所述连接柱的步骤包括：在所述衬底第一面上和所述焊盘表面形成种子层；在所述种子层上形成第一光刻胶，所述第一光刻胶暴露所述焊盘表面的种子层；在所述第一光刻胶暴露出的种子层上形成连接柱。
可选的，所述塑封层覆盖所述连接柱侧壁和顶部表面；所述减薄处理之后，还包括：对所述塑封层进行打孔处理，在所述塑封层中形成焊孔，所述焊孔底部暴露出所述连接柱顶部表面；在所述焊孔中形成焊料层。
可选的，所述连接柱的材料为铜，所述焊料层的材料为锡。
可选的，所述打孔处理的工艺包括激光打孔。
可选的，所述打孔处理的工艺参数包括：激光波长为532nm。
可选的，所述焊料层表面高于所述塑封层表面。
可选的，形成所述焊料层的步骤包括：在所述塑封层上形成第二光刻胶，所述第二光刻胶暴露出所述焊料孔底部的连接柱顶部表面；在所述焊料孔中形成焊料层。
相应的，本发明还提供一种由上述形成方法形成的半导体结构。
与现有技术相比，本发明的技术方案具有以下优点：
本发明技术方案提供的半导体结构的形成方法中，进行所述减薄处理之前，在所述衬底第一面上形成塑封层。所述塑封层能够在所述减薄处理过程中，对所述衬底进行支撑，抑制塑封层发生褶皱或破碎。所述塑封层还用作对所述衬底进行封装的材料，所述减薄处理之后，所述塑封层不需要去除，从而能够简化工艺流程，降低工艺成本。
进一步，所形成的半导体结构包括第一散热板和第二散热板，所述衬底可以通过第一散热板和第二散热板进行散热，从而有利于增加衬底的散热，提高所形成半导体结构的性能。
附图说明
图1至图4是一种半导体结构的形成方法各步骤的结构示意图；
图5至图14是本发明半导体结构的形成方法一实施例各步骤的结构示意图。
具体实施方式
半导体结构及其形成方法存在诸多问题，例如：半导体结构的形成方法工艺复杂，生产成本较高。
现结合现一种半导体结构的形成方法，分析所述形成方法形成的半导体结构性能较差的原因：
图1至图4是一种半导体结构的形成方法各步骤的结构示意图。
请参考图1，提供初始基底，所述初始基底包括：衬底100，所述衬底100包括相对的第一面101和第二面102；位于所述衬底100第一面101上的焊盘110；位于所述焊盘110和衬底100上的钝化层111，所述钝化层111暴露出部分焊盘110表面。
继续参考图1，提供载晶圆120；通过胶合剂121将所述载晶圆120与所述钝化层111和焊盘110进行键合。
请参考图2，所述键合之后，对所述衬底100第二面102进行减薄处理，形成主衬底103和位于所述主衬底103周围的支撑衬底104。
请参考图3，所述减薄处理之后，去除所述载晶圆120使所述初始基底形成基底10。
请参考图4，提供基板11，所述基板11上具有散热板12，所述散热板12上具有分立的第一导电层13和第二导电层14；使所述基底10第二面102通过焊层15与所述第二导电层14连接；通过导线16使所述基底10中的焊盘110与所述第一导电层13相连。
其中，在所述减薄处理过程中，所述主衬底103的厚度逐渐减小。为了防止所述主衬底103在减薄处理过程中发生褶皱或开裂，需要使所述初始基底与所述载晶圆键合。所述减薄处理之后，需要通过解键合去除所述载晶圆。所述工艺过程较复杂。
为解决所述技术问题，本发明提供了一种半导体结构的形成方法，包括：提供衬底，所述衬底包括相对的第一面和第二面，所述第一面为功能面；在所述衬底第一面上形成塑封层；形成所述塑封层之后，对所述衬底第二面进行减薄处理。
其中，进行所述减薄处理之前，在所述衬底第一面上形成塑封层。所述塑封层能够在所述减薄处理过程中，对所述衬底进行支撑，抑制塑封层发生褶皱或破碎。所述塑封层还用做对所述衬底进行封装的材料，所述减薄处理之后，所述塑封层不需要去除，从而能够简化工艺流程，降低工艺成本。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图5至图14是本发明半导体结构的形成方法一实施例各步骤的结构示意图。
请参考图5，提供衬底200，所述衬底200包括相对的第一面201和第二面202，所述第一面201为功能面。
本实施例中，所述衬底200为芯片或晶圆。
所述第一面201为功能面，所述功能面为具有半导体器件的面。
所述衬底200第一面201具有半导体器件。具体的，本实施例中，所述半导体器件包括IGBT。在其他实施例中，所述半导体器件还可包括MOS晶体管、二级管、三级管或电阻。
所述IGBT包括：位于所述衬底200中的漂移区；位于所述漂移区中的栅极结构，位于所述栅极结构两侧漂移区中的阱区；位于所述阱区中的发射区。
本实施例中，所述衬底200上具有焊盘210。在其他实施例中，所述衬底上还可以不具有所述焊盘。
本实施例中，所述焊盘210的个数为多个(图中示出一个)，所述焊盘210分别连接所述发射区和栅极结构。
所述焊盘210的材料为铜或铝。
本实施例中，所述衬底200和所述焊盘210上还具有钝化层211。所述钝化层211用于保护所述衬底200，减小外界环境对所述衬底200的影响。
本实施例中，所述钝化层211的材料为氮化硅或聚酰胺。
后续在所述焊盘210上形成连接柱。
本实施例中，形成所述连接柱的步骤如图6和图7所示。
请参考图6，在所述钝化层211和所述焊盘210表面形成种子层212。
所述种子层212用于为后续形成连接柱220提供籽晶。
本实施例中，所述种子层212的材料为铜。
本实施例中，形成所述种子层212的工艺包括物理气相沉积工艺。
如果所述种子层212的厚度过小，不容易为后续形成的连接柱220提供完整的晶格结构；如果所述种子层212的厚度过大，容易加大工艺难度。具体的，所述种子层212的厚度为1000埃～6000埃。
本实施例中，形成所述种子层212之前，还包括：在所述钝化层211和焊盘210上形成阻挡层(图中未示出)。
所述阻挡层用于隔离所述钝化层211与所述种子层212，抑制所述种子层212材料原子向所述钝化层211扩散。
所述阻挡层的材料为氮化钛、氮化钽、钛或钽。
如果所述阻挡层的厚度过小，不利于阻挡种子层212材料原子向所述钝化层211扩散；如果所述阻挡层的厚度过大，容易加大工艺难度。具体的，所述阻挡层的材料为100埃～500埃。
继续参考图6，在所述种子层212上形成第一光刻胶221，所述第一光刻胶221暴露出所述焊盘210表面的种子层212。
所述第一光刻胶221用于定义后续形成的连接柱的尺寸和位置。
本实施例中，形成所述第一光刻胶221的工艺包括旋涂工艺。
请参考图7，在所述第一光刻胶221暴露出的种子层212上形成连接柱220。
所述连接柱220用于实现所述焊盘210与后续形成的第一连接层之间的电连接。
本实施例中，所述连接柱220的材料为铜。在其他实施例中，所述连接柱的材料还可以为铝或钨。
本实施例中，形成所述连接柱220的工艺包括电化学镀膜工艺。
在所述第一光刻胶221暴露出的种子层212上形成连接柱220之后，还包括：去除所述第一光刻胶221。
请参考图8，在所述衬底200第一面201上形成塑封层240。
所述塑封层240用于在后续减薄处理过程中支撑所述衬底200，防止所述衬底200破碎。所述塑封层240还可以用做封装材料，隔离所述衬底200与外界环境，从而防止外界环境对所述衬底200的影响。
本实施例中，所述塑封层240覆盖所述连接柱220顶部和侧壁表面。在其他实施例中，所述塑封层还可以暴露出所述连接柱顶部。
本实施例中，所述塑封层240的材料为聚合物。
本实施例中，形成所述塑封层240的步骤包括：在所述衬底200第一面201上形成前驱体；对所述前驱体进行加热处理，使所述前驱体固化形成所述塑封层240。
所述前驱体为流体对所述连接柱220的覆盖性好，能够充分隔离外界环境与所述衬底200；所述前驱体固化之后形成的塑性层具有较强的硬度，能够在后续减薄处理过程中对衬底200进行支撑。
如果所述塑封层240的厚度过小，不利于对所述衬底200进行支撑和保护；如果所述塑封层240的厚度过大，容易增加工艺难度。具体的，所述塑封层240的厚度为100μm～600μm。
请参考图9，在所述塑封层240上形成覆盖层230。
所述覆盖层230用于保护所述塑封层240，防止所述塑封层240被划伤。
本实施例中，所述塑封层240的材料为玻璃。在其他实施例中，所述塑封层的材料还可以为硅。
需要说明的是，在其他实施例中还可以不形成所述塑封层。
请参考图10，形成所述塑封层240之后，对所述衬底200第二面202进行减薄处理。
本实施例中，形成所述覆盖层230之后，对所述衬底200第二面202进行减薄处理。
本实施例中，所述减薄处理的工艺为化学机械抛光工艺。在其他实施例中，所述减薄处理的工艺还可以为TAIKO工艺。所述第二面包括中心区域和包围所述中心区域的***区域；TAIKO工艺是指在所述减薄处理对所述第二面的中心区域的去除量大于所述***区域的去除量，从而使所述***区域的衬底厚度大于所述中心区域衬底厚度，因此所述***区域衬底能够为中心区域衬底提供支撑。
需要说明的是，进行所述减薄处理之前，在所述衬底200第一面201上形成塑封层240。所述塑封层240能够在所述减薄处理过程中，对所述衬底200进行支撑，抑制塑封层240发生褶皱或破碎。所述塑封层240用作对所述衬底200进行封装的材料，所述减薄处理之后，所述塑封层240不需要去除，从而能够简化工艺流程，降低工艺成本。
请参考图11，所述减薄处理之后，在所述衬底200第二面202上形成第二连接层242。
所述第二连接层242用于实现衬底200第二面202与外部电路的电连接。
所述第二连接层242的材料为铜。在其他实施例中，所述第二连接层的材料还可以为铝。
形成所述第二连接层242的工艺包括电化学镀膜工艺。
本实施例中，所述衬底中具有IGBT，形成所述第二连接层242之前，还包括：对所述衬底200第二面202进行离子注入，形成集电区。所述第二连接层242用于实现所述集电区与外部电路的电连接。
所述减薄处理之后，形成所述第二连接层242之前，所述形成方法还包括：去除所述覆盖层230。
请参考图12，所述减薄处理之后，对所述塑封层240进行打孔处理，在所述塑封层240中形成焊孔231，所述焊孔231底部暴露出所述连接柱220顶部表面。
所述焊孔231用于后续容纳焊料层。
本实施例中，所述打孔处理的工艺包括激光打孔。
本实施例中，所述打孔工艺的参数包括：激光波长为532nm。
结合参考图13，在所述焊孔231中形成焊料层260。
所述焊料层260用于实现所述连接柱220与后续形成的第一连接层之间的连接。
本实施例中，所述焊料层260的材料为锡。
本实施例中，焊料层260表面高于所述塑封层240表面。焊料层260表面高于所述塑封层240表面有利于焊料层260与后续形成的第一连接层241良好接触。在其他实施例中，焊料层表面可以齐平于所述塑封层表面。
本实施例中，形成所述焊料层260的步骤包括：在所述塑封层240上形成第二光刻胶222，所述第二光刻胶222暴露出所述焊料孔231(如图12所示)底部的连接柱220顶部表面；在所述焊料孔231中形成焊料层260。
形成所述焊料层260之后，所述形成方法还包括：去除所述第二光刻胶222。
请参考图14，在所述塑封层240和焊料层260上形成第一连接层241和第一散热板251，所述第一连接层241位于所述第一散热板251和焊料层260之间、以及所述第一散热板251和塑封层240之间；在所述第二连接层242表面形成第二散热板252，所述第二连接层242位于所述第二散热板252与所述衬底200第二面202之间。
本实施例中，所述第二连接层242的材料为铜。在其他实施例中，所述第二连接层的材料还可以为铝。
本实施例中，所述第一散热板251和第二散热板252的材料为陶瓷。
需要说明的是，所形成的半导体结构包括第一散热板251和第二散热板252，所述衬底200可以通过第一散热板251和第二散热板252进行散热，从而有利于增加衬底200的散热，提高所形成半导体结构的性能。
综上，本发明实施例提供的半导体结构的形成方法中，进行所述减薄处理之前，在所述衬底第一面上形成塑封层。所述塑封层能够在所述减薄处理过程中，对所述衬底进行支撑，抑制塑封层发生褶皱或破碎。所述塑封层还用做对所述衬底进行封装的材料，所述减薄处理之后，所述塑封层不需要去除，从而能够简化工艺流程，降低工艺成本。
进一步，所形成的半导体结构包括第一散热板和第二散热板，所述衬底可以通过第一散热板和第二散热板进行散热，从而有利于增加衬底的散热，提高所形成半导体结构的性能。
本发明还提供一种由图5至图14所示的方法形成的半导体结构。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

1.一种半导体结构的形成方法，其特征在于，包括：
提供衬底，所述衬底包括相对的第一面和第二面，所述第一面为功能面；
在所述衬底第一面上形成塑封层；
形成所述塑封层之后，对所述衬底第二面进行减薄处理。
2.如权利要求1所述的半导体结构的形成方法，其特征在于，所述塑封层的材料为聚合物。
3.如权利要求2所述的半导体结构的形成方法，其特征在于，形成所述塑封层的步骤包括：在所述衬底第一面上形成前驱体；对所述前驱体进行加热处理，使所述前驱体固化，形成所述塑封层。
4.如权利要求1所述的半导体结构的形成方法，其特征在于，所述塑封层的厚度为100μm～600μm。
5.如权利要求1所述的半导体结构的形成方法，其特征在于，所述减薄处理的工艺包括：化学机械抛光工艺或TAIKO工艺。
6.如权利要求1所述的半导体结构的形成方法，其特征在于，所述减薄处理之前，还包括：在所述塑封层上形成覆盖层；所述减薄处理之后，去除所述覆盖层。
7.如权利要求1所述的半导体结构的形成方法，其特征在于，所述覆盖层的材料为玻璃。
8.如权利要求1所述的半导体结构的形成方法，其特征在于，所述减薄处理之后，还包括：在所述塑封层上形成第一连接层和位于所述第一连接层上的第一散热板。
9.如权利要求1或8所述的半导体结构的形成方法，其特征在于，所述减薄处理之后，还包括：在所述衬底第二面上形成第二连接层和第二散热板，所述第二连接层位于所述衬底第二面和所述第二散热板之间。
10.如权利要求9所述的半导体结构的形成方法，其特征在于，所述减薄处理之后，还包括：在所述衬底第二面上形成第二连接层和第二散热板，所述第二连接层位于所述衬底第二面和所述第二散热板之间，所述第一散热板和第二散热板的材料为陶瓷。
11.如权利要求1所述的半导体结构的形成方法，其特征在于，所述衬底第一面上具有焊盘；形成所述塑封层之前，还包括：在所述焊盘上形成连接柱。
12.如权利要求11所述的半导体结构的形成方法，其特征在于，所述连接柱的材料为铜或铝。
13.如权利要求11所述的半导体结构的形成方法，其特征在于，形成所述连接柱的步骤包括：在所述衬底第一面上和所述焊盘表面形成种子层；在所述种子层上形成第一光刻胶，所述第一光刻胶暴露出所述焊盘表面的种子层；在所述第一光刻胶暴露出的种子层上形成连接柱。
14.如权利要求11所述的半导体结构的形成方法，其特征在于，所述塑封层覆盖所述连接柱侧壁和顶部表面；
所述减薄处理之后，还包括：对所述塑封层进行打孔处理，在所述塑封层中形成焊孔，所述焊孔底部暴露出所述连接柱顶部表面；在所述焊孔中形成焊料层。
15.如权利要求14所述的半导体结构的形成方法，其特征在于，所述连接柱的材料为铜，所述焊料层的材料为锡。
16.如权利要求14所述的半导体结构的形成方法，其特征在于，所述打孔处理的工艺包括激光打孔。
17.如权利要求16所述的半导体结构的形成方法，其特征在于，所述打孔处理的工艺参数包括：激光波长为532nm。
18.如权利要求14所述的半导体结构的形成方法，其特征在于，所述焊料层表面高于所述塑封层表面。
19.如权利要求18所述的半导体结构的形成方法，其特征在于，形成所述焊料层的步骤包括：在所述塑封层上形成第二光刻胶，所述第二光刻胶暴露出所述焊料孔底部的连接柱顶部表面；在所述焊料孔中形成焊料层。
20.一种由权利要求1至19任意一项权利要求所述的形成方法形成的半导体结构。
CN201710363176.7A 2017-05-22 2017-05-22 半导体结构及其形成方法 Active CN108962767B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201710363176.7A CN108962767B (zh) 2017-05-22 2017-05-22 半导体结构及其形成方法
US15/986,023 US10685831B2 (en) 2017-05-22 2018-05-22 Semiconductor structures and fabrication methods thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710363176.7A CN108962767B (zh) 2017-05-22 2017-05-22 半导体结构及其形成方法

Publications (2)

Publication Number Publication Date
CN108962767A true CN108962767A (zh) 2018-12-07
CN108962767B CN108962767B (zh) 2020-06-09

Family

ID=64272424

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710363176.7A Active CN108962767B (zh) 2017-05-22 2017-05-22 半导体结构及其形成方法

Country Status (2)

Country Link
US (1) US10685831B2 (zh)
CN (1) CN108962767B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109729639B (zh) * 2018-12-24 2020-11-20 奥特斯科技(重庆)有限公司 在无芯基板上包括柱体的部件承载件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050035983A1 (en) * 2002-11-12 2005-02-17 Nanoink, Inc. Methods and apparatus for ink delivery to nanolithographic probe systems
CN103441080A (zh) * 2013-08-28 2013-12-11 江苏长电科技股份有限公司 一种芯片正装bga封装方法
CN103594441A (zh) * 2012-08-14 2014-02-19 台湾积体电路制造股份有限公司 半导体封装件及其制造方法
CN103681535A (zh) * 2012-09-01 2014-03-26 万国半导体股份有限公司 带有厚底部基座的晶圆级封装器件及其制备方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7838985B2 (en) * 2007-07-12 2010-11-23 Vishay General Semiconductor Llc Semiconductor assembly that includes a power semiconductor die located on a cell defined by first and second patterned polymer layers
US9536808B1 (en) * 2015-06-16 2017-01-03 Macronix International Co., Ltd. Photo pattern method to increase via etching rate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050035983A1 (en) * 2002-11-12 2005-02-17 Nanoink, Inc. Methods and apparatus for ink delivery to nanolithographic probe systems
CN103594441A (zh) * 2012-08-14 2014-02-19 台湾积体电路制造股份有限公司 半导体封装件及其制造方法
CN103681535A (zh) * 2012-09-01 2014-03-26 万国半导体股份有限公司 带有厚底部基座的晶圆级封装器件及其制备方法
CN103441080A (zh) * 2013-08-28 2013-12-11 江苏长电科技股份有限公司 一种芯片正装bga封装方法

Also Published As

Publication number Publication date
US20180337038A1 (en) 2018-11-22
US10685831B2 (en) 2020-06-16
CN108962767B (zh) 2020-06-09

Similar Documents

Publication Publication Date Title
US11721676B2 (en) Package structure with dummy die
TWI705508B (zh) 半導體元件及其製造方法
US20230378078A1 (en) Package with fan-out structures
TWI585920B (zh) 半導體裝置及製造方法
US20180182727A1 (en) Embedded silicon substrate fan-out type packaging structure and manufacturing method therefor
TWI415236B (zh) 封裝結構
CN103681613B (zh) 具有离散块的半导体器件
US8526186B2 (en) Electronic assembly including die on substrate with heat spreader having an open window on the die
TWI567897B (zh) 薄型扇出式多晶片堆疊封裝構造與製造方法
US11721659B2 (en) Package structure with warpage-control element
EP3154085A1 (en) Semiconductor package structure and method for forming the same
TWI360188B (en) A semiconductor package assembly and methods of fo
CN106601724A (zh) 半导体装置
TW201739032A (zh) 封裝結構
US20080142954A1 (en) Multi-chip package having two or more heat spreaders
TW201919190A (zh) 封裝結構及其製造方法
TW201119005A (en) Chip package and fabrication method thereof
TW201310586A (zh) 半導體結構及其製造方法
TW202113997A (zh) 半導體結構及其製造方法
TW201843780A (zh) 半導體封裝及其製造方法
TWI587464B (zh) 封裝結構及其製造方法
CN108962767A (zh) 半导体结构及其形成方法
KR20210152243A (ko) 반도체 칩, 반도체 장치, 및 이를 포함하는 반도체 패키지
US20220278069A1 (en) Structure and formation method of chip package with protective lid
US11393797B2 (en) Chip package with redistribution layers

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant