CN106601724A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN106601724A
CN106601724A CN201610004260.5A CN201610004260A CN106601724A CN 106601724 A CN106601724 A CN 106601724A CN 201610004260 A CN201610004260 A CN 201610004260A CN 106601724 A CN106601724 A CN 106601724A
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CN
China
Prior art keywords
semiconductor device
layer
semiconductor
chip
intermediary layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610004260.5A
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English (en)
Inventor
施信益
姜序
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Micron Technology Inc
Original Assignee
Micron Technology Inc
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Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to CN202010638985.6A priority Critical patent/CN111710664A/zh
Publication of CN106601724A publication Critical patent/CN106601724A/zh
Pending legal-status Critical Current

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Abstract

本发明公开了一种半导体装置，包含有：一中介层，具有一第一侧以及相对所述第一侧的一第二侧；一第一半导体裸晶，经由多个第一凸块固定设置在所述中介层的所述第一侧上的一第一芯片安置区域内；一第二半导体裸晶，设置在所述中介层的所述第一侧上的一第二芯片安置区域内，其中所述第二芯片安置区域邻近所述第一芯片安置区域；一环状支撑结构，设置在所述中介层的所述第一侧上且包围所述第一芯片安置区域以及所述第二芯片安置区域；以及多个锡球，设置在所述中介层的所述第二侧上。

Description

半导体装置
技术领域
本发明涉及半导体封装技术领域，特别是涉及一种具有无穿硅通孔(TSV-less)中介层的晶圆级封装。
背景技术
2.5D半导体封装，例如CoWoS(Chip-On-Wafer-On-Substrate)技术是本领域所已知的，CoWoS技术通常使用穿硅通孔(TSV)技术将多个芯片结合到单一装置中，此架构提供了更高密度的互连、降低整体互连长度以及减轻相关的电阻电容负载，使在更小的形状因子上提高性能及减少功耗。
如本领域所知的，2.5D半导体封装将多个裸晶并列放置在穿硅通孔硅中介层上，所述硅中介层是昂贵的，因为制造具有穿硅通孔的硅中介层是一复杂的过程。因此，在某些应用上可能不希望形成包括具有穿硅通孔中介层的晶圆级封装产品。
一般来说，可靠性测试及产量测试是在所有半导体裸晶被设置在中介层上及被模塑料包覆后进行，然而，此方法具有较高的已知合格裸晶损失(known good die loss)的风险。此外，由于热膨胀系数不匹配及封装的厚度，模塑料的厚层导致增加封装的翘曲。已知的是，芯片翘曲仍然是一个问题。
翘曲会导致裸晶-晶圆堆叠组装合格率降低，因为无法确保裸晶与晶圆的紧密接合。翘曲问题在大尺寸的晶圆特别严重，且在要求细间距重分布层的晶圆级半导体封装过程中形成一个阻碍。因此，本领域仍然需要一个改进的制造晶圆级封装的方法。
发明内容
本发明涉及提供一种改良的半导体装置及其制造方法，所述方法能减少已知合格裸晶损失的风险，并且能有效的解决翘曲问题。
根据本发明的一个实施例，提出一种半导体装置，其包括：一中介层，具有一第一侧以及相对所述第一侧的一第二侧；一第一半导体裸晶，经由多个第一凸块固定设置在所述中介层的所述第一侧上的一第一芯片安置区域内；一第二半导体裸晶，设置在所述中介层的所述第一侧上的一第二芯片安置区域内，其中所述第二芯片安置区域邻近所述第一芯片安置区域；一环状支撑结构，设置在所述中介层的所述第一侧上且包围所述第一芯片安置区域以及所述第二芯片安置区域；以及多个锡球，设置在所述中介层的所述第二侧上。
根据本发明的一实施例，所述中介层包含一重分布层，所述重分布层包含至少一介电层以及至少一金属层，其中，中介层不具有穿硅通孔或穿硅通孔基板。
根据本发明的另一实施例，所述环状支撑结构是一3D打印结构。本发明半导体装置可进一步包括一屏蔽结构，直接设置在第一半导体裸晶的一上表面以及侧壁面上。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来限制本发明。
附图说明
图1到图7以及图9到12是根据本发明的实施例所绘示的制造具有无穿硅通孔中介层的晶圆级封装的示例性方法，其中：
图8是晶圆级封装中间产品的顶视图；
图13是根据本发明的另一实施例所绘示的晶圆级封装中间产品的剖面结构；以及
图14以及图15显示支撑结构的示例性设计。
其中，附图标记说明如下：
300 载板
302 黏着层
310 钝化层
410 重分布层
412 介电层
414 金属层
418 焊盘
520 锡球
600 载板
602 黏着层
400 无穿硅通孔中介层
400a 第一侧
400b 第二侧
416a 凸块
416b 凸块
102 第一芯片安置区域
104 第二芯片安置区域
420a 第一裸晶
460 支撑结构
106 晶圆切割道区域
470 屏蔽结构
660 切割胶带
10 芯片封装
100 基板
120 锡球
420b 第二裸晶
1 多芯片封装
具体实施方式
在下文中，加以陈述本发明的具体实施方式，所述具体实施方式可参考相对应的附图，以使所述附图构成实施方式的一部分。同时也借由说明，公开本发明可据以施行的方式。所述实施例已被清楚地描述足够的细节，以使本技术领域的技术人员可据以实施本发明。其他实施例亦可被加以施行，且在结构上所做的改变仍属本发明所涵盖的范畴。
因此，下文的细节描述将不被视为一种限定，且本发明所涵盖的范畴仅被所附的权利要求以及其同意义的范围涵盖。
本发明的一或多个实施例将参照附图描述，其中，相同附图标记始终用以表示相同组件，且其中阐述的结构未必按比例所绘制。术语“裸晶”、“半导体芯片”及“半导体裸晶”在整个说明书中可互换使用。
文中所使用的术语“晶圆”及“基板”包括任何具有暴露表面的结构， 在其表面上根据本发明沉积一层，例如，形成如重分布层的回路结构。术语“基板”包括半导体晶圆，但不限于此。术语“基板”亦可用来指加工过程中的半导体结构，且可包括已被制造在其上的其他层。
请参考图1到图12。图1到图7以及图9到12是根据本发明的实施例所绘示的制造具有无穿硅通孔中介层的晶圆级封装的示例性方法。
如图1所示，首先提供一载板300。载板300可具有一黏着层302，作为一可被撕除的基材。之后，在载板300的上表面上形成至少一介电层或钝化层310。钝化层310可包含有机材料(例如：聚酰亚胺)或无机材料(例如：氮化硅、氧化硅或类似物)。
如图2所示，随后，于钝化层310上形成重分布层410。重分布层410是用作重分布层中介层，能够在半导体裸晶上扇出输入/输出垫。重分布层410可包含至少一个介电层412以及至少一金属层414。介电层412可包含有机材料(例如：聚酰亚胺)或无机材料(例如：氮化硅、氧化硅或类似物)，但不限于此。金属层414可包含铝、铜、钨、钛、氮化钛或类似物。根据本发明一实施例，金属层414可包含多个显露在介电层412上表面的焊盘418。
如图3所示，在形成重分布层410之后，在个别的焊盘418上形成凸块或锡球520。根据本发明一实施例，锡球520可包含控制崩塌芯片连接(C4)锡球。
如图4所示，将图中的晶圆级封装中间产品黏接到另一载板600。锡球520面向且接触载板600。载板600可包含玻璃基板，但不限于此。也可选择使用黏着层602。随后，载板300被移除以暴露出钝化层310的主表面。重分布层410及钝化层310构成一中介层或一无穿硅通孔中介层400。无穿硅通孔中介层400具有第一侧400a及相对所述第一侧400a的第二侧400b。载板300的剥离可通过激光处理或紫外线照射处理来执行，但不限于此。
如图5所示，在剥离载板300之后，可在钝化层310中形成开口，以暴露在无穿硅通孔中介层400的第一侧400a上的金属层414中各个凸块垫，然后凸块416a以及416b，例如：微凸块，可形成在个别的凸块垫上。凸块416a被设置在第一芯片安置区域102内，以及凸块416b被设置在邻近所述第一芯片安置区域102的第二芯片安置区域104内。
如图6所示，随后，个别的覆晶芯片或裸晶(第一裸晶)420a，使其有源面朝下面向重分布层410，经由第一芯片安置区域102内的凸块416a连接设置在重分布层410上，以形成芯片-晶圆(C2W)堆栈构造。这些个别的覆晶芯片或裸晶420a是具有一定功能的有源集成电路芯片，例如，绘图处理芯片或中央处理器芯片。可选择地，底胶(未示于图中)可被涂布于个别的芯片或裸晶420a之下。此时，由凸块416b所界定的第二芯片安置区域104是空出来的且没有芯片或裸晶被设置在其上。
如图7及图8所示，支撑结构460，例如，环状或环形支撑结构，形成于重分布层410上。更具体地，支撑结构460是形成在钝化层310的上表面上。个别的支撑结构460包围第一芯片安置区域102以及第二芯片安置区域104。根据本发明一实施例，支撑结构460是独立的且彼此不连接。然而，根据本发明另一实施例，支撑结构460可彼此连接，例如，如图14及图15所示，具有晶圆级的格状图案的支撑结构460。支撑结构460可完全与晶圆切割道区域106重叠。
根据本发明一实施例，支撑结构460可包含金属，但不限于此。在另一实施例中，支撑结构460可依据设计需求而包含非金属材料。
根据本发明一实施例，支撑结构460可借由3D打印方法形成，但不限于此。在一些实施例中，支撑结构460可预先制备，之后借由黏着层或其他手段设置在钝化层310上。根据本发明一实施例，支撑结构460具有足够的高度致使支撑结构460的上表面与芯片或裸晶420a的上表面齐平。
根据本发明另一实施例，如图13所示，除了支撑结构460，另有一屏蔽结构470，例如，电磁干扰(EMI)屏蔽结构，同时直接设置在芯片或裸晶420a的上表面以及侧壁面上。根据本发明一实施例，屏蔽结构470可借由3D打印方法形成，但不限于此。
如图9所示，随后，晶圆级封装中间产品可贴附在一切割胶带660，其中，支撑结构460及裸晶420a朝向且接触切割胶带660。之后，载板600及黏着层602被移除以暴露出锡球520。
如图10所示，在载板600及黏着层602被移除之后，晶圆级封装中间产品通过切割工艺被分割成个别的芯片封装10。此时，每个芯片封装10包含重分布层410、设置在重分布层410上的第一裸晶420a，以及支撑结构460。值得注意的是，第二芯片安置区域104在此阶段仍是空出的。
如图11所示，随后，个别的芯片封装10被设置在基板100(诸如封装基板或印刷电路基板)之上，由此形成一中间封装。芯片封装10被设置在基板100的上表面。在基板100的下表面可设置多个锡球120。中间封装而后被测试。测试过程，诸如，可靠性测试及产量测试被执行以测试中间封装。
如图12所示，在测试完中间封装后，第二芯片或裸晶420b，使其有源面朝下面向重分布层410，通过第二芯片安置区域104内的凸块416b设置在重分布层410上，以形成多芯片封装1。根据本发明一实施例，第二芯片或裸晶420b可为内存芯片，但不限于此。随后进行多芯片封装1的测试。可选择地，模塑料(未示于图中)可被应用以密封第一裸晶420a及第二裸晶420b。
综上所述，本发明提供一种改良的半导体装置及其制造方法，所述方法能减少已知合格裸晶损失的风险。支撑结构460的并入减轻或避免了翘曲问 题。
本发明的半导体装置包括：无穿硅通孔中介层400，其具有一第一侧400a以及相对所述第一侧400a的一第二侧400b；一第一半导体裸晶420a，经由多个第一凸块416a固定设置在所述中介层的所述第一侧400a上的一第一芯片安置区域内102；一第二半导体裸晶420b，设置在所述中介层的所述第一侧400a上的一第二芯片安置区域内104，其中所述第二芯片安置区域104邻近所述第一芯片安置区域102；一环状支撑结构460，设置在所述中介层的所述第一侧400a上，所述环状支撑结构包围所述第一芯片安置区域102以及所述第二芯片安置区域104；以及多个锡球520，设置在所述中介层的所述第二侧400b上。
中介层400包含一重分布层410。所述重分布层400包含至少一介电层412以及至少一金属层414。所述中介层400不具有穿硅通孔或穿硅通孔基板。
环状支撑结构460可为一3D打印结构。半导体装置可进一步包含有一屏蔽结构470(第13图)，直接设置在所述第一半导体裸晶420a的一上表面以及侧壁面上。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (11)

1.一种半导体装置，其特征在于，包括：
一中介层，具有一第一侧以及相对所述第一侧的一第二侧；
一第一半导体裸晶，经由多个第一凸块固定设置在所述中介层的所述第一侧上的一第一芯片安置区域内；
一第二半导体裸晶，设置在所述中介层的所述第一侧上的一第二芯片安置区域内，其中所述第二芯片安置区域邻近所述第一芯片安置区域；
一环状支撑结构，设置在所述中介层的所述第一侧上，所述环状支撑结构包围所述第一芯片安置区域以及所述第二芯片安置区域；以及
多个锡球，设置在所述中介层的所述第二侧上。
2.根据权利要求1所述的半导体装置，其特征在于，所述中介层包含一重分布层。
3.根据权利要求2所述的半导体装置，其特征在于，所述重分布层包含至少一介电层以及至少一金属层。
4.根据权利要求1所述的半导体装置，其特征在于，所述中介层不具有穿硅通孔或穿硅通孔基板。
5.根据权利要求1所述的半导体装置，其特征在于，所述第一半导体裸晶包含一绘图处理芯片或一中央处理器芯片。
6.根据权利要求5所述的半导体装置，其特征在于，所述第二半导体裸晶包含一内存芯片。
7.根据权利要求1所述的半导体装置，其特征在于，所述环状支撑结构是一3D打印结构。
8.根据权利要求1所述的半导体装置，其特征在于，还包括一屏蔽结构，直接设置在所述第一半导体裸晶的一上表面以及侧壁面上。
9.根据权利要求1所述的半导体装置，其特征在于，还包括一封装基板，连结所述中介层的所述第二侧上的所述多个锡球。
10.根据权利要求1所述的半导体装置，其特征在于在所述第一半导体裸晶与所述第二半导体裸晶之间没有设置模塑料。
11.根据权利要求1所述的半导体装置，其特征在于，所述环状支撑结构完全与一晶圆切割道区域重叠。
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