CN1089504C - 时钟恢复电路 - Google Patents
时钟恢复电路 Download PDFInfo
- Publication number
- CN1089504C CN1089504C CN98120012A CN98120012A CN1089504C CN 1089504 C CN1089504 C CN 1089504C CN 98120012 A CN98120012 A CN 98120012A CN 98120012 A CN98120012 A CN 98120012A CN 1089504 C CN1089504 C CN 1089504C
- Authority
- CN
- China
- Prior art keywords
- data
- clock
- input
- circuit
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000011084 recovery Methods 0.000 title claims abstract description 86
- 230000001360 synchronised effect Effects 0.000 claims abstract description 172
- 239000000284 extract Substances 0.000 claims description 16
- 230000003111 delayed effect Effects 0.000 claims description 9
- 230000000295 complement effect Effects 0.000 claims description 6
- 238000004904 shortening Methods 0.000 abstract 1
- 238000000605 extraction Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 17
- 230000000630 rising effect Effects 0.000 description 15
- 230000000694 effects Effects 0.000 description 4
- 241001269238 Data Species 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 230000001934 delay Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
- H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Dram (AREA)
Abstract
Description
Claims (16)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP253200/97 | 1997-09-18 | ||
JP25320097A JP3019814B2 (ja) | 1997-09-18 | 1997-09-18 | クロックリカバリ回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1211853A CN1211853A (zh) | 1999-03-24 |
CN1089504C true CN1089504C (zh) | 2002-08-21 |
Family
ID=17247953
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN98120012A Expired - Fee Related CN1089504C (zh) | 1997-09-18 | 1998-09-18 | 时钟恢复电路 |
Country Status (7)
Country | Link |
---|---|
US (1) | US6275547B1 (zh) |
EP (1) | EP0903885B1 (zh) |
JP (1) | JP3019814B2 (zh) |
KR (1) | KR100295121B1 (zh) |
CN (1) | CN1089504C (zh) |
DE (1) | DE69833715T2 (zh) |
TW (1) | TW437154B (zh) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0953982B1 (en) * | 1998-04-28 | 2008-08-13 | Matsushita Electric Industrial Co., Ltd. | Input circuit |
US6985547B2 (en) * | 1999-09-27 | 2006-01-10 | The Board Of Governors For Higher Education, State Of Rhode Island And Providence Plantations | System and method of digital system performance enhancement |
US6760392B1 (en) * | 1999-11-12 | 2004-07-06 | Advanced Micro Devices, Inc. | Method and apparatus to provide fixed latency early response in a system with multiple clock domains with fixable clock ratios |
US7187721B1 (en) * | 2000-02-09 | 2007-03-06 | Rambus Inc. | Transition-time control in a high-speed data transmitter |
JP3386031B2 (ja) * | 2000-03-06 | 2003-03-10 | 日本電気株式会社 | 同期遅延回路及び半導体集積回路装置 |
US6895188B1 (en) * | 2000-04-10 | 2005-05-17 | Sprint Communications Company L.P. | Optical signal reshaping to mitigate polarization mode dispersion |
US7233637B2 (en) * | 2000-04-17 | 2007-06-19 | Adaptive Networks, Inc. | Wideband communication using delay line clock multiplier |
US6864672B2 (en) * | 2000-05-24 | 2005-03-08 | John W. Bogdan | High resolution phase frequency detectors |
US6748027B1 (en) * | 2000-08-10 | 2004-06-08 | Intel Corporation | CMI signal timing recovery |
US6748039B1 (en) * | 2000-08-11 | 2004-06-08 | Advanced Micro Devices, Inc. | System and method for synchronizing a skip pattern and initializing a clock forwarding interface in a multiple-clock system |
US6904537B1 (en) | 2001-08-27 | 2005-06-07 | Network Elements, Inc. | Data transmission across asynchronous time domains using phase-shifted data packet |
CN1295902C (zh) * | 2003-07-08 | 2007-01-17 | 上海大学 | 高速突发式时钟和数据恢复器 |
US7091764B2 (en) * | 2004-11-05 | 2006-08-15 | Infineon Technologies Ag | Duty distortion detector |
US7102403B2 (en) | 2005-02-03 | 2006-09-05 | Mediatek Incorporation | Clock recovering circuit utilizing a delay locked loop for generating an output clock locked to an analog input signal and related method thereof |
KR100734263B1 (ko) * | 2005-06-14 | 2007-07-02 | 삼성전자주식회사 | 동기화회로 |
JP5397025B2 (ja) * | 2009-06-02 | 2014-01-22 | ソニー株式会社 | クロック再生装置および電子機器 |
CN101800062A (zh) * | 2010-04-02 | 2010-08-11 | 福州思迈特数码科技有限公司 | 实现音频升频的车载dvd导航影音装置 |
US8922150B1 (en) * | 2012-07-18 | 2014-12-30 | The Johns Hopkins University | Differential serial driver |
KR102151184B1 (ko) * | 2013-07-24 | 2020-09-02 | 삼성전자주식회사 | 클록 데이터 복원 회로 및 이를 포함하는 타이밍 컨트롤러 그리고 이의 구동 방법 |
KR102378768B1 (ko) * | 2018-08-21 | 2022-03-29 | 한국전자통신연구원 | 클럭의 위상을 조정하기 위한 전자 회로 |
KR102635773B1 (ko) * | 2018-09-13 | 2024-02-08 | 삼성전자주식회사 | 저장 장치 |
US10991426B2 (en) * | 2019-01-25 | 2021-04-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory device current limiter |
DE102019132067A1 (de) | 2019-01-25 | 2020-07-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strombegrenzer für speichervorrichtung |
CN113746427B (zh) * | 2021-11-05 | 2022-02-11 | 深圳飞骧科技股份有限公司 | 一种rc振荡电路 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4795988A (en) * | 1986-11-18 | 1989-01-03 | Britz William J | Low distortion oscillator |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4975929A (en) * | 1989-09-11 | 1990-12-04 | Raynet Corp. | Clock recovery apparatus |
US5237290A (en) * | 1992-05-08 | 1993-08-17 | At&T Bell Laboratories | Method and apparatus for clock recovery |
US5592519A (en) * | 1994-06-22 | 1997-01-07 | Alcatel Network Systems, Inc. | Dual frequency clock recovery using common multitap line |
DE19534693A1 (de) * | 1995-09-19 | 1997-03-20 | Phoenix Contact Gmbh & Co | Schaltungsanordnung zur Teilnehmersynchronisation bei asynchroner bitserieller Datenübertragung |
-
1997
- 1997-09-18 JP JP25320097A patent/JP3019814B2/ja not_active Expired - Fee Related
-
1998
- 1998-09-14 TW TW087115272A patent/TW437154B/zh not_active IP Right Cessation
- 1998-09-16 US US09/154,037 patent/US6275547B1/en not_active Expired - Lifetime
- 1998-09-17 KR KR1019980038455A patent/KR100295121B1/ko not_active IP Right Cessation
- 1998-09-18 DE DE69833715T patent/DE69833715T2/de not_active Expired - Lifetime
- 1998-09-18 EP EP98117775A patent/EP0903885B1/en not_active Expired - Lifetime
- 1998-09-18 CN CN98120012A patent/CN1089504C/zh not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4795988A (en) * | 1986-11-18 | 1989-01-03 | Britz William J | Low distortion oscillator |
Also Published As
Publication number | Publication date |
---|---|
DE69833715D1 (de) | 2006-05-04 |
EP0903885A2 (en) | 1999-03-24 |
JP3019814B2 (ja) | 2000-03-13 |
TW437154B (en) | 2001-05-28 |
JPH1198132A (ja) | 1999-04-09 |
DE69833715T2 (de) | 2006-11-23 |
EP0903885B1 (en) | 2006-03-08 |
CN1211853A (zh) | 1999-03-24 |
KR19990029900A (ko) | 1999-04-26 |
EP0903885A3 (en) | 2003-05-28 |
KR100295121B1 (ko) | 2001-07-12 |
US6275547B1 (en) | 2001-08-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: NEC ELECTRONICS TAIWAN LTD. Free format text: FORMER OWNER: NIPPON ELECTRIC CO., LTD. Effective date: 20030411 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20030411 Address after: Kanagawa, Japan Patentee after: NEC Corp. Address before: Tokyo, Japan Patentee before: NEC Corp. |
|
C56 | Change in the name or address of the patentee |
Owner name: RENESAS ELECTRONICS CORPORATION Free format text: FORMER NAME: NEC CORP. |
|
CP01 | Change in the name or title of a patent holder |
Address after: Kanagawa, Japan Patentee after: Renesas Electronics Corporation Address before: Kanagawa, Japan Patentee before: NEC Corp. |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20020821 Termination date: 20140918 |
|
EXPY | Termination of patent right or utility model |