CN108933081B - 过孔和跳孔结构 - Google Patents
过孔和跳孔结构 Download PDFInfo
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Abstract
本发明涉及过孔和跳孔结构。本发明一般地涉及半导体结构,更特别地,涉及过孔和跳孔结构以及制造的方法。所述方法包括:在硬掩模材料中形成多个开口;使用阻挡材料阻挡所述硬掩模材料中的多个开口中的至少一者;穿过未被所述阻挡材料阻挡的所述多个开口中的另一者,蚀刻到金属化特征叠层中的金属化特征的跳孔;以及通过自底向上填充方法至少部分地填充跳孔。
Description
技术领域
本发明一般地涉及半导体结构,更特别地,涉及过孔和跳孔(skip via)结构以及制造的方法。
背景技术
过孔是穿过一个或多个相邻层的平面的物理电子电路中的布线结构(例如,布线层)之间的电连接。例如,在集成电路设计中,过孔是绝缘氧化物层中的小开口,该开口允许不同布线层之间的导电连接。将金属的最下层连接到扩散或多晶的过孔通常被称为“接触”。
在过孔技术中,跳孔可以被形成为穿过许多绝缘体层,例如,绕过绝缘体层内的一个或多个布线结构,以便与下布线结构连接。这提供了改善的电阻特性、使下布线结构(例如,在M0层中)的电容最小化、以及提供芯片制造工艺中的面积效率。
使用跳孔存在许多挑战。例如,在制造工艺中,跳孔将落着在较低层级(例如,M0层级)的布线结构上,而常规的过孔将落着在较高层级(例如,M1或更高层级)的布线结构上。但是,由于跳孔蚀刻工艺,在较高层级的布线结构与过孔互连结构之间的界面处可能出现损坏。也就是说,由于蚀刻深度不同,跳孔蚀刻工艺将导致上层布线结构的表面损坏,例如,铜(Cu)材料。这种损坏导致较高的电阻率,进而降低器件性能。此外,可能不存在对下伏金属层的保护。
过孔结构的金属化,诸如过孔结构的Cu金属化,存在其他挑战。例如,在化学镀金属化期间,过孔填充高度可能不同。
发明内容
在本公开的一方面中,一种方法包括:在硬掩模材料中形成多个开口;使用阻挡材料阻挡所述硬掩模材料中的所述多个开口中的至少一者;穿过未被所述阻挡材料阻挡的所述多个开口中的另一者,蚀刻到金属化特征叠层中的金属化特征的跳孔;以及通过自底向上填充方法至少部分地填充所述跳孔。
在本公开的一方面中,一种方法包括:在硬掩模材料中形成具有不同宽度的多个开口;蚀刻第一过孔至少部分地进入到下伏的绝缘体层中,所述第一过孔将暴露所述硬掩模材料中的所述开口中的至少一者的侧壁;蚀刻第二过孔至少部分地进入到下伏的绝缘体层中,所述第二过孔将落在所述硬掩模材料中的所述开口中的至少另一者内;在所述硬掩模材料中的所述开口的所述至少一者的暴露的所述侧壁上生长阻挡材料,以防止所述第一过孔的持续过孔形成;在所述第一过孔保持被所述阻挡材料阻挡的同时,延伸所述第二过孔以形成跳孔,所述第二过孔被形成到下金属化特征;以及通过自底向上填充方法至少部分地填充所述跳孔。
在本公开的一方面中,一种结构包括:第一布线层,其具有一个或多个布线结构;位于所述第一布线层上方的第二布线层,所述第二布线层包括一个或多个布线结构;过孔结构,其包括延伸到所述第二布线层的所述一个或多个布线结构的导电材料;以及跳孔结构,其延伸穿过所述第二布线层,并且落在所述第一布线层的所述一个或多个布线结构上,所述跳孔包括与所述一个或多个布线结构接触的第一导电金属以及与所述第一导电材料电接触的第二导电材料。
附图说明
通过本公开的示例性实施例的非限制性实例并参考所述多个附图,在以下详细描述中描述本公开。
图1示出了除了其他特征之外的根据本公开的各方面的结构以及相应的制造工艺。
图2示出了除了其他特征之外的根据本公开的各方面的延伸到帽层的过孔以及相应的制造工艺。
图3示出了除了其他特征之外的根据本公开的各方面的生长在金属材料上的阻挡层以及相应的制造工艺。
图4示出了除了其他特征之外的根据本公开的各方面的跳孔以及相应的制造工艺。
图5示出了除了其他特征之外的根据本公开的各方面的在结构的第一层级处的过孔和在结构的较低层级处的跳孔以及相应的制造工艺。
图6示出了除了其他特征之外的根据本公开的各方面的跳孔内的自底向上填充的材料以及相应的制造工艺。
图7示出了除了其他特征之外的根据本公开的各方面的跳孔顶部的沟槽以及相应的制造工艺。
图8示出了除了其他特征之外的根据本公开的各方面的多个被填充的沟槽和过孔以及相应的制造工艺。
图9-12示出了根据本公开的替代方面的相应结构以及相应的制造工艺。
具体实施方式
本公开一般地涉及半导体结构,更特别地,涉及过孔和跳孔结构以及制造的方法。在实施例中,本文提供的工艺在蚀刻一个或多个跳孔结构的同时,使用阻挡层来延迟过孔形成。通过使用阻挡层,现在可以通过在控制用于跳孔的蚀刻时间的同时延迟用于常规过孔的过孔蚀刻,来调整蚀刻时间和过孔轮廓。通过实现本文描述的结构和工艺,还可以在仍然控制常规过孔的轮廓的同时,消除用于图案化跳孔的掩蔽层级。掩蔽层级的消除将显著降低成本并减少制造时间。
本公开的结构可以使用多种不同的工具以多种方式制造。但是,总体来说,这些方法和工具用于形成尺寸在微米和纳米级的结构。已从集成电路(IC)技术中采用用于制造本公开的结构的方法,即,技术。例如,这些结构构建在晶片上,并且以在晶片顶部上的通过光刻工艺图案化的材料的膜实现。特别地,结构的制造使用三个基本构建块:(i)在衬底上沉积材料的薄膜,(ii)通过光刻成像在膜的顶部施加图案化掩模,以及(iii)对照掩模选择性地蚀刻膜。
图1示出了根据本公开的各方面的结构以及相应的制造工艺。更具体地,图1示例出了包括在自对准过孔(SAV)方向100中的结构的多个图。在实施例中,该结构包括位于结构的不同金属化层处的由帽材料120隔开的几个层间电介质(ILD)层110、110'。在实施例中,除了其他的材料之外,ILD层110、110'可以由超低k电介质材料、或者包括致密氧化物材料或氮化硅的低k电介质材料形成。帽材料120可以是氮化硅(SiN)材料以及其他材料。
在实施例中,ILD层110、110'可以包括金属化,即,布线结构和过孔。例如,ILD层110可以包括包含布线结构的最底部的金属层M0、以及包含连接到叠层结构的不同层上的不同布线层的过孔V0的上金属层M1。金属层M0、M1可以通过常规的光刻和蚀刻技术形成,然后沉积金属或金属合金,例如,铜或铝等。在实施例中,可以通过化学机械抛光(CMP)工艺去除ILD层110的表面上的任何残余金属。
如图1进一步所示,硬掩模130和氧化物层140可以沉积在最上面的ILD层110'上。硬掩模130可以是通过任何常规沉积工艺,例如,物理气相沉积(PVD)工艺,来沉积的TiN材料。在沉积硬掩模130之后,通过常规沉积工艺,例如,化学气相沉积(CVD)工艺,将氧化物层(硬掩模)140沉积在硬掩模130上。
在图2中,多个开口145、145'、145”形成在硬掩模130、140之内以暴露ILD层110'的部分。在实施例中,硬掩模130、140中的开口145、145'、145”通过常规光刻和蚀刻工艺形成,例如,具有选择性化学(chemistry)的反应离子蚀刻(RIE)。如SAV方向100所示,硬掩模130、140中的开口145、145'、145”具有不同的轮廓,例如,宽度。具体地,与宽度W2相比,宽度W1更小或更窄,宽度W2宽于宽度W1。如本领域的技术人员应理解的,不同的宽度将通过允许阻挡材料的选择性生长来为随后的蚀刻工艺提供控制。
仍然参考图2,有机平面化层(OPL)150沉积在硬掩模140上。可以通过常规沉积工艺,例如,旋涂,来沉积OPL150,其将形成用于后续蚀刻过孔160、160'、160”的光刻叠层的部分,这些过孔至少部分地进入到ILD层110'中,落着在M1层和/或帽材料120(即,SiN材料)上。在实施例中,通过本文所述的具有选择性化学的常规蚀刻工艺,在上金属化层中,例如,在M1和M2中,形成过孔160、160'、160”。
如图2进一步所示,过孔160'与开口145'对准,暴露TiN材料的部分(侧壁);而过孔160”被设置在具有宽度W2的开口145”之内或之间,这样不会暴露硬掩模130的任何TiN材料。以这种方式,阻挡材料可以在开口145'的TiN材料的暴露部分上选择性地生长,以控制随后的跳孔形成中的蚀刻工艺。
图3示例出了形成在开口145'中的阻挡材料170。如本领域的技术人员应理解的,依赖于在先前制造步骤中的材料的暴露,阻挡材料170可以在一个以上的开口中形成。在实施例中,阻挡材料170可以是钴(Co)或钌(Ru),或者其他将在如SAV方向100所示的掩模130的TiN材料的暴露表面上生长的选择性生长材料。在实施例中,阻挡材料170将在用于常规过孔的过孔160'内生长;而阻挡材料170将不会在用于跳孔的过孔160”中生长。也就是说,如本领域的技术人员应理解的,因为过孔160”完全落在宽度W2内,例如,W2具有大于过孔160”的宽度,并且不暴露硬掩模130的任何TiN材料。因此,阻挡材料170不会在过孔160”内生长。
在图4中,通过蚀刻穿过帽层120,过孔(跳孔)160”延伸(蚀刻)到下布线层M0,落在金属化特征上,即,下金属化特征上。在实施例中,可以通过常规蚀刻工艺,例如,反应离子蚀刻(RIE),将跳孔160”形成到ILD材料和帽材料120。以此方式,蚀刻工艺将暴露下伏的布线层M0,而本领域的技术人员应理解,阻挡材料170将防止或延迟过孔160'形成,例如,防止在跳孔形成期间过孔160'进一步向下蚀刻。也就是说,阻挡材料170将保护过孔160',因此将延迟材料的任何蚀刻延伸,以便不会暴露下伏金属化特征M1。相比之下,未被阻挡材料170覆盖的过孔160”将被进一步蚀刻,延伸穿过M1层,落在M0层上并暴露该M0层。
在图5中,可以通过常规的稀盐酸(dHF)工艺去除阻挡材料170。此dHF工艺也可被用于清洁任何残余的RIE材料。但是,如所示出的,帽材料(层)120将保留在金属化特征M1上。
在图6中,通过常规氧灰化工艺或剥离剂(stripant)去除OPL150。在去除OPL150之后,可以使用化学镀自底向上填充工艺部分地填充跳孔160”。在实施例中,填充工艺可以是Co化学镀填充工艺,如参考标号180所示。在替代实施例中,除了其他材料之外,金属材料可以是能够从暴露的金属化特征M0生长的Ru。由于帽层120保留在金属化特征M1上,因此金属填充工艺将不填充过孔160'。
如图7所示,在跳孔160”的顶部形成沟槽160”'用于随后的金属布线沉积,并且沟槽160可以形成在ILD层中并与过孔160'连接。这些沟槽160和160”'通过对TiN硬掩模130具有选择性的RIE工艺形成。在RIE工艺期间,打开过孔160'下方的帽层120。
在实施例中,填充材料180的高度可以是可控的并且可以基于跳孔160”中的金属材料的所需最终高度来调整。在实施例中,例如,填充材料180的高度可以是任何高度,优选地低于或位于沟槽160”的底部表面的层级。作为具体示例,填充材料180的高度可以在约15nm-200nm的范围内。在实施例中,填充工艺防止夹断(pinch off),因此防止在填充材料中形成空气间隙。
在图8中,金属材料190,例如,金属化层M2,填充过孔结构160'以及沟槽160和160”(例如,其用作布线层)。可以通过常规沉积工艺,例如,PVD、CVD和/或电镀,来沉积金属材料190,然后通过CMP工艺来平坦化金属材料190。在实施例中,除了其他实例之外,金属材料190可以由任何合适的导电材料构成,例如,铜(Cu)。在实施例中,金属材料190将与由参考标号200表示的跳孔结构的金属材料直接接触。
图9-12示例出了根据本发明的各方面的替代实施例。在该替代实施例中,在ILD层中形成任何过孔结构之前,从硬掩模130的暴露的TiN材料生长阻挡材料170。如前所述并且如本领域的技术人员应理解的,在允许执行进一步的蚀刻以形成跳孔结构的同时,将在暴露的TiN(或其他材料)上选择性地生长阻挡材料170。
如图10所示,过孔160”可以通过到下伏帽层120'、直到金属化层M1的蚀刻工艺而形成。蚀刻工艺可以是选择性蚀刻工艺,以去除材料的任何中间层,包括例如ILD层110、110'和帽材料120、120'。在此工艺期间,阻挡材料170将防止在该结构的其他位置处的到金属化特征M1的过孔的蚀刻。
在图11中,去除阻挡材料170并且在结构的两侧继续蚀刻工艺以形成过孔160'和跳孔160”。在该实施例中,蚀刻工艺为选择性蚀刻工艺(例如,RIE),其将暴露两个层级M0和M1处的下伏金属化特征。更具体地,该蚀刻工艺将去除帽材料120、120',从而暴露不同层级上的金属化特征。
图12继续RIE工艺以形成沟槽160和160”'。然后形成镶嵌(damascene)结构,并且通过化学镀自底向上填充工艺例如使用Co或Ru填充过孔结构160'、160”。这是可能的,因为这样的事实:金属化特征在过孔160'、160”中暴露。如前所述,金属材料190,例如,上金属化层M2,填充过孔结构160'以及沟槽160和160”'(例如,用作布线层),然后执行CMP工艺以平坦化金属材料190。在实施例中,除了其他实例之外,金属材料190可以由任何合适的导电材料构成,例如,铜(Cu)。在实施例中,金属材料190将与由参考标号200表示的跳孔结构以及常规过孔结构的金属材料直接接触。
在实施例中,设想代替化学镀自底向上填充工艺,可以通过常规金属化沉积工艺,例如,CVD Cu工艺,来填充过孔(vies)。还设想可以通过化学镀自底向上填充工艺来填充任何过孔,同时使用铜(Cu)金属化来填充其他过孔,如图7所示,或者使用这两种填充组合来填充过孔。此外,如本领域的技术人员应理解的,使用阻挡材料170调整蚀刻时间和过孔轮廓,而消除使用多个掩模来形成跳孔的需要。
如上所述的方法用在集成电路芯片的制造中。所得到的集成电路芯片可以由制造商以作为裸芯片的原始晶片形式(即,作为具有多个未封装芯片的单个晶片)或者以封装形式分发。在后一种情况下,芯片被安装在单芯片封装(诸如塑料载体中,其引线固定到母板或其他更高级别的载体)或多芯片封装(诸如陶瓷载体中,其具有表面互连和/或掩埋互连中的一者或两者)中。在任何情况下,芯片然后与其他芯片、分立电路元件和/或其他信号处理设备集成,作为(a)中间产品(诸如母板)或者(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品,从玩具和其他低端应用,到具有显示器、键盘或其他输入设备以及中央处理器的高级计算机产品。
本公开的各种实施例的描述已为了示例的目的而给出,但并非旨在是穷举性的或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下,许多修改和变化对于本领域普通技术人员将是显而易见的。本文中所用术语的被选择以旨在最好地解释实施例的原理、实际应用或对市场中发现的技术的技术改进,或者使本技术领域的其他普通技术人员能理解本文公开的实施例。
Claims (19)
1.一种用于制造半导体结构的方法,包括:
在硬掩模材料中形成多个开口;
使用阻挡材料阻挡所述硬掩模材料中的所述多个开口中的至少一者;以及
穿过未被所述阻挡材料阻挡的所述多个开口中的另一者,蚀刻到金属化特征叠层中的金属化特征的跳孔,
其中所述阻挡材料被选择性地生长在所述硬掩模材料的暴露部分上。
2.根据权利要求1所述的方法,其中所述硬掩模材料是TiN。
3.根据权利要求1所述的方法,进一步包括通过自底向上填充方法至少部分地填充所述跳孔。
4.根据权利要求3所述的方法,其中所述自底向上填充方法是化学镀方法,并且包括使用Co或Ru填充所述跳孔。
5.根据权利要求3所述的方法,进一步包括去除所述阻挡材料,并形成到所述金属化特征上方的上金属化特征的过孔。
6.根据权利要求5所述的方法,其中在通过所述自底向上填充方法填充所述跳孔之后,完全形成所述过孔。
7.根据权利要求6所述的方法,其中完全形成所述过孔包括蚀刻穿过帽层以暴露所述上金属化特征。
8.根据权利要求3所述的方法,进一步包括在形成所述阻挡材料之前,部分地形成到所述金属化特征上方的上金属化特征的帽层的过孔。
9.根据权利要求8所述的方法,其中在通过所述自底向上填充方法填充所述跳孔的所述填充之后,通过蚀刻穿过所述帽层以暴露上部金属化特征来完全形成所述过孔。
10.根据权利要求9所述的方法,进一步包括使用与在所述自底向上填充方法中使用的材料不同的材料填充所述过孔。
11.根据权利要求1所述的方法,其中所述多个开口中的至少另一者比所述多个开口中的所述至少一者宽。
12.一种用于制造半导体结构的方法,包括:
在硬掩模材料中形成具有不同宽度的多个开口;
蚀刻第一过孔至少部分地进入到下伏绝缘体层中,所述第一过孔将暴露所述硬掩模材料中的所述开口中的至少一者的侧壁;
蚀刻第二过孔至少部分地进入到下伏绝缘体层中,所述第二过孔将落在所述硬掩模材料中的所述开口中的至少另一者内;
在所述硬掩模材料中的所述开口的所述至少一者的暴露的所述侧壁上选择性生长阻挡材料,以防止所述第一过孔的持续过孔形成;以及
在所述第一过孔保持被所述阻挡材料阻挡的同时,延伸所述第二过孔以形成跳孔,所述第二过孔被形成到下金属化特征。
13.根据权利要求12所述的方法,其中所述硬掩模材料是TiN。
14.根据权利要求13所述的方法,进一步包括通过作为化学镀方法的自底向上填充方法至少部分地填充所述跳孔。
15.根据权利要求14所述的方法,进一步包括去除所述阻挡材料,并继续形成到所述下金属化特征上方的上金属化特征的所述第一过孔。
16.根据权利要求15所述的方法,其中在通过所述自底向上填充方法填充所述跳孔之后,完全形成穿过帽层的所述第一过孔以暴露所述上金属化特征。
17.根据权利要求16所述的方法,进一步包括使用与在所述化学镀自底向上填充方法中使用的材料不同的材料填充所述第一过孔。
18.一种根据权利要求1到17中的任一项所述的方法制造的半导体结构,包括:
第一布线层,其具有一个或多个布线结构;
位于所述第一布线层上方的第二布线层,所述第二布线层包括一个或多个布线结构;
过孔结构,其包括延伸到所述第二布线层的所述一个或多个布线结构的导电材料;以及
跳孔结构,其延伸穿过所述第二布线层,并且落在所述第一布线层的所述一个或多个布线结构上,所述跳孔包括与所述一个或多个布线结构接触的第一导电材料以及与所述第一导电材料电接触的第二导电材料,所述第一导电材料位于所述跳孔结构的下部中,以及所述第二导电材料位于所述跳孔结构的上部中。
19.根据权利要求18所述的半导体结构,其中所述第一导电材料是钴,以及所述导电材料和所述第二导电材料是铜。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090200683A1 (en) * | 2008-02-13 | 2009-08-13 | International Business Machines Corporation | Interconnect structures with partially self aligned vias and methods to produce same |
CN102339790A (zh) * | 2011-10-29 | 2012-02-01 | 上海华力微电子有限公司 | 半导体器件制作方法 |
CN102751234A (zh) * | 2011-04-19 | 2012-10-24 | 索尼公司 | 半导体装置及其制造方法、固体摄像装置以及电子设备 |
US20130234336A1 (en) * | 2012-03-12 | 2013-09-12 | Globalfoundries Inc. | Processes for forming integrated circuits and integrated circuits formed thereby |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW430943B (en) * | 1999-01-08 | 2001-04-21 | Nippon Electric Co | Method of forming contact or wiring in semiconductor device |
US6391785B1 (en) | 1999-08-24 | 2002-05-21 | Interuniversitair Microelektronica Centrum (Imec) | Method for bottomless deposition of barrier layers in integrated circuit metallization schemes |
AU2001286432A1 (en) | 2000-08-14 | 2002-02-25 | Matrix Semiconductor, Inc. | Dense arrays and charge storage devices, and methods for making same |
US20060289202A1 (en) | 2005-06-24 | 2006-12-28 | Intel Corporation | Stacked microvias and method of manufacturing same |
US9236292B2 (en) | 2013-12-18 | 2016-01-12 | Intel Corporation | Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) |
JP2015185838A (ja) | 2014-03-26 | 2015-10-22 | イビデン株式会社 | パッケージ基板及びパッケージ基板の製造方法 |
US9679841B2 (en) | 2014-05-13 | 2017-06-13 | Qualcomm Incorporated | Substrate and method of forming the same |
US10049921B2 (en) | 2014-08-20 | 2018-08-14 | Lam Research Corporation | Method for selectively sealing ultra low-k porous dielectric layer using flowable dielectric film formed from vapor phase dielectric precursor |
KR102379370B1 (ko) | 2014-12-23 | 2022-03-28 | 인텔 코포레이션 | 비아 차단 층 |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090200683A1 (en) * | 2008-02-13 | 2009-08-13 | International Business Machines Corporation | Interconnect structures with partially self aligned vias and methods to produce same |
CN102751234A (zh) * | 2011-04-19 | 2012-10-24 | 索尼公司 | 半导体装置及其制造方法、固体摄像装置以及电子设备 |
CN102339790A (zh) * | 2011-10-29 | 2012-02-01 | 上海华力微电子有限公司 | 半导体器件制作方法 |
US20130234336A1 (en) * | 2012-03-12 | 2013-09-12 | Globalfoundries Inc. | Processes for forming integrated circuits and integrated circuits formed thereby |
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CN108933081A (zh) | 2018-12-04 |
TWI636516B (zh) | 2018-09-21 |
US20180342454A1 (en) | 2018-11-29 |
US10157833B1 (en) | 2018-12-18 |
TW201901820A (zh) | 2019-01-01 |
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