CN108922896A - 一种像素结构及其制作方法、阵列基板及tn型显示面板 - Google Patents
一种像素结构及其制作方法、阵列基板及tn型显示面板 Download PDFInfo
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Abstract
本发明提供了一种像素结构及其制作方法、阵列基板及TN型显示面板,该像素结构包括:基板;栅极层和公共电极层,形成于所述基板上;第一绝缘层,形成于所述栅极层、基板和公共电极层上;有源层,形成于所述第一绝缘层上且对应栅极层设置;源极层和漏极层,形成于所述有源层上;第二绝缘层,形成于所述源极层、漏极层、第一绝缘层上;透明电极层,形成于所述第一绝缘层上且与所述公共电极层电性连接;第三绝缘层,形成于所述第二绝缘层和透明电极层上;透明像素电极层,形成于所述第三绝缘层上并与所述漏极层电性连接,且与所述透明电极层位置重叠形成存储电容。本发明可以在保证像素结构开孔率的前提下有效增大存储电容。
Description
技术领域
本发明涉及了显示技术领域,特别是涉及了一种像素结构及其制作方法、阵列基板及TN型显示面板。
背景技术
随着TFT-LCD行业的不断发展,用户对显示面板的要求也越来越高,现有的显示面板一般包括TN型显示面板、IPS型显示面板等,在TN型显示面板的像素结构中,一般都是通过在同基板上形成重叠布置的像素电极层和公共电极层,从而形成存储电容,由于现有像素结构中像素电极层和公共电极层交叠位置不透光,从而为了保证开口率,如图1所示,现有的像素结构中公共电极层200’环绕像素电极层100’三面设置,像素的存储电容大小受到限制。
发明内容
本发明所要解决的技术问题是能够有效保证TN型显示面板中像素结构的开口率同时有效增大存储电容。
为解决上述技术问题,本发明提供了一种像素结构,应用于TN型显示面板中,其特征在于,包括:
基板;
栅极层和公共电极层,形成于所述基板上;
第一绝缘层,形成于所述栅极层、基板和公共电极层上;
有源层,形成于所述第一绝缘层上且对应栅极层设置;
源极层和漏极层,形成于所述有源层上;
第二绝缘层,形成于所述源极层、漏极层、第一绝缘层上;
透明电极层,形成于所述第二绝缘层上且与所述公共电极层电性连接;
第三绝缘层,形成于所述第二绝缘层和透明电极层上;
透明像素电极层,形成于所述第三绝缘层上并与所述漏极层电性连接,且与所述透明电极层位置重叠形成存储电容。
作为本发明的一种优选方案,所述透明电极层和透明像素电极层的材料为ITO、AZO或IGZO。
作为本发明的一种优选方案,所述透明电极层通过穿透第一绝缘层和第二绝缘层的双层过孔与所述公共电极层电性连接。
作为本发明的一种优选方案,所述透明像素电极层通过穿透第二绝缘层和第三绝缘层的双层过孔与所述漏极层电性连接。
作为本发明的一种优选方案,还包括与所述栅极层电性连接的栅极线和与所述源极层电性连接的数据线。
进一步地,提供一种阵列基板,包括以上任一项所述的像素结构。
进一步地,提供一种TN型显示面板,包括以上所述的阵列基板。
进一步地,提供一种像素结构的制作方法,包括以下步骤:
步骤1:提供一基板;
步骤2:在所述基板上沉积第一金属薄膜,通过构图工艺形成栅极层和公共电极层;
步骤3:在形成栅极层和公共电极层的基板上沉积第一绝缘层;
步骤4:在第一绝缘层上形成有源层;
步骤5:在完成上述步骤的基板上沉积第二金属薄膜,通过构图工艺形成源极层和漏极层;
步骤6:在完成上述步骤的基板上沉积第二绝缘层;
步骤7:在第二绝缘层上沉积第一透明电极薄膜,通过过孔与所述公共电极层电性连接形成透明电极层;
步骤8:在完成上述步骤的基板上沉积第三绝缘层;
步骤9:在第三绝缘层上沉积第二透明电极薄膜,形成透明像素电极层。
本发明具有如下技术效果:本发明提供的一种像素结构及其制作方法、阵列基板及TN型显示面板通过设置了第三绝缘层和透明电极层,并且通过使得透明电极层与公共电极层电性连接,且与透明像素电极层重叠形成存储电容,由于透明电极层与透明像素电极层的重叠面积增大不会影响到像素结构的开口率,从而可以在保证像素结构开孔率的前提下有效增大透明电极层与透明像素电极层的重叠面积,从而有效增大存储电容;此外,透明电极层的平面形状可以优选为四面环绕像素电极层且覆盖数据线设置,可以起到有效屏蔽电场作用,避免数据线与像素电极层形成边缘电场影响对液晶的控制,有效提高显示质量;而且可以有效减小避免数据线与像素电极层间的设置距离,优化像素结构。
附图说明
图1为现有技术提供的一种像素结构的公共电极层的平面布置示意图;
图2为本发明提供的一种像素结构的结构示意图;
图3为本发明提供的一种透明电极层的平面布置示意图;
图4为本发明提供的一种像素结构的制作方法的流程框图。
具体实施方式
为使本发明的目的,技术方案和优点更加清楚,下面结合附图对本发明实施方式作进一步详细说明。显然,所描述的实施例是本发明的一部分实施例,而不是全部的实施例。基于所描述的本发明的实施例,本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例,都属于本发明保护的范围。
除非另外定义,本发明使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。在本发明的描述中,需要理解的是,若有术语“上”、“下”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此附图中描述位置关系的用语仅用于示例性说明,不能理解为对本专利的限制,对于本领域的普通技术人员而言,可以根据具体情况理解上述术语的具体含义。
实施例一
如图1所示,其表示了本发明提供的一种像素结构。该像素结构应用于TN型显示面板中,包括:基板1;栅极层2和公共电极层3,形成于所述基板1上;第一绝缘层4,形成于所述栅极层2、基板1和公共电极层3上;有源层5,形成于所述第一绝缘层1上且对应栅极层2设置;源极层6和漏极层7,形成于所述有源层5上;第二绝缘层8,形成于所述源极层6、漏极层7、第一绝缘层4上;透明电极层9,形成于所述第二绝缘层8上且与所述公共电极层3电性连接;第三绝缘层10,形成于所述第二绝缘层8和透明电极层9上;透明像素电极层11,形成于所述第三绝缘层10上并与所述漏极层7电性连接,且与所述透明电极层9位置重叠形成存储电容。
这样,本发明提供的像素结构相较于普通应用于TN型显示面板的像素结构增加设置了第三绝缘层10和透明电极层9,并且通过使得透明电极层9与公共电极层3电性连接,且与透明像素电极层11重叠形成存储电容,由于透明电极层9与透明像素电极层11的重叠面积增大不会影响到像素结构的开口率,从而可以在保证像素结构开孔率的前提下有效增大透明电极层9与透明像素电极层11的重叠面积,从而有效增大存储电容。具体地,所述透明电极层9通过穿透第一绝缘层4和第二绝缘层8的双层过孔与所述公共电极层3电性连接。所述透明像素电极层11通过穿透第二绝缘层8和第三绝缘层10的双层过孔与所述漏极层7电性连接。具体地,如图3所示,还包括与所述栅极层2电性连接的栅极线12和与所述源极层6电性连接的数据线13,具体地,透明电极层9的平面形状可以优选为四面环绕像素电极层11且覆盖数据线13设置,既有效增大了与透明像素电极层11的重叠面积,又使得透明电极9起到有效屏蔽电场作用,避免数据线13与像素电极层11形成边缘电场影响对液晶的控制,有效提高显示质量;而且可以有效减小避免数据线13与像素电极层11间的设置距离,优化像素结构。具体地,所述透明电极层9和透明像素电极层11的材料均为ITO、AZO或IGZO,优选为ITO,具有良好的透光性能和导电性能。
进一步地,提供一种阵列基板,包括以上任一项所述的像素结构。进一步地,提供一种TN型显示面板,包括以上所述的阵列基板。
实施例二
如图4所示,其表示了本实施例提供的一种像素结构的制作方法,包括以下步骤:
步骤1:提供一基板;具体地,该基板可以是透光的玻璃基板;
步骤2:在所述基板上沉积第一金属薄膜,通过构图工艺形成栅极层和公共电极层;具体地,可以是通过磁控溅射的方式在基板上沉积第一金属薄膜,继而通过涂胶、掩膜、曝光、显影、刻蚀、剥离等构图工艺形成栅极层和公共电极层;
步骤3:在形成栅极层和公共电极层的基板上沉积第一绝缘层;具体地,可以是通过化学气相沉积方法沉积第一绝缘层;
步骤4:在第一绝缘层上形成有源层;具体地,可以是通过化学气相沉积方法沉积非晶硅半导体和掺杂非晶硅半导体薄膜通过光刻、刻蚀和剥离等构图工艺形成有源层;
步骤5:在完成上述步骤的基板上沉积第二金属薄膜,通过构图工艺形成源极层和漏极层;
步骤6:在完成上述步骤的基板上沉积第二绝缘层;具体地,可以是通过化学气相沉积方法沉积第二绝缘层;
步骤7:在第二绝缘层上沉积第一透明电极薄膜,通过过孔与所述公共电极层电性连接形成透明电极层;
步骤8:在完成上述步骤的基板上沉积第三绝缘层;具体地,可以是通过化学气相沉积方法沉积第二绝缘层;
步骤9:在第三绝缘层上沉积第二透明电极薄膜,形成透明像素电极层。
具体地,所述第一透明电极薄膜和第二透明电极薄膜的材料均可以为ITO、AZO或IGZO。优选为ITO,具体地,所述透明电极层可以是通过对所述第一透明电极薄膜进行涂胶、掩膜、曝光、显影、刻蚀、剥离等构图工艺形成,所述透明像素电极层可以是通过对所述第二透明电极薄膜进行涂胶、掩膜、曝光、显影、刻蚀、剥离等构图工艺形成。具体地,所述透明电极层也可以通过在所述第一透明电极薄膜上通过镀制第一DLC薄膜并激光烧刻第一DLC薄膜形成第一DLC图案层,继而进行刻蚀和等离子去除第一DLC图案层形成;所述透明像素电极层也可以通过在所述第二透明电极薄膜上通过镀制第二DLC薄膜并激光烧刻第二DLC薄膜形成第二DLC图案层,继而进行刻蚀和等离子去除第二DLC图案层形成,这样免除了曝光显影步骤,工艺简单且易于控制。
本发明提供的像素结构的制作方法形成了第三绝缘层和透明电极层,并且透明电极层与公共电极层电性连接,且与透明像素电极层重叠形成存储电容,由于透明电极层与透明像素电极层的重叠面积增大不会影响到像素结构的开口率,从而可以在保证像素结构开孔率的前提下有效增大透明电极层与透明像素电极层的重叠面积,从而有效增大存储电容;而且可以使得透明电极层的平面形状为四面环绕像素电极层且覆盖数据线设置,既有效增大了与透明像素电极层的重叠面积,又可以有效屏蔽数据线电场,有效避免数据线与像素电极层间的距离加大,提高显示质量。
以上所述实施例仅表达了本发明的实施方式,其描述较为具体和详细,但并不能因此而理解为对本发明专利范围的限制,但凡采用等同替换或等效变换的形式所获得的技术方案,均应落在本发明的保护范围之内。
Claims (8)
1.一种像素结构,应用于TN型显示面板中,其特征在于,包括:
基板;
栅极层和公共电极层,形成于所述基板上;
第一绝缘层,形成于所述栅极层、基板和公共电极层上;
有源层,形成于所述第一绝缘层上且对应栅极层设置;
源极层和漏极层,形成于所述有源层上;
第二绝缘层,形成于所述源极层、漏极层、第一绝缘层上;
透明电极层,形成于所述第二绝缘层上且与所述公共电极层电性连接;
第三绝缘层,形成于所述第二绝缘层和透明电极层上;
透明像素电极层,形成于所述第三绝缘层上并与所述漏极层电性连接,且与所述透明电极层位置重叠形成存储电容。
2.根据权利要求1所述的像素结构,其特征在于,所述透明电极层和透明像素电极层的材料为ITO、AZO或IGZO。
3.根据权利要求1所述的像素结构,其特征在于,所述透明电极层通过穿透第一绝缘层和第二绝缘层的双层过孔与所述公共电极层电性连接。
4.根据权利要求1所述的像素结构,其特征在于,所述透明像素电极层通过穿透第二绝缘层和第三绝缘层的双层过孔与所述漏极层电性连接。
5.根据权利要求1所述的像素结构,其特征在于,还包括与所述栅极层电性连接的栅极线和与所述源极层电性连接的数据线。
6.一种阵列基板,其特征在于,包括权利要求1-5任一项所述的像素结构。
7.一种TN型显示面板,其特征在于,包括权利要求6所述的阵列基板。
8.一种像素结构的制作方法,其特征在于,包括以下步骤:
步骤1:提供一基板;
步骤2:在所述基板上沉积第一金属薄膜,通过构图工艺形成栅极层和公共电极层;
步骤3:在形成栅极层和公共电极层的基板上沉积第一绝缘层;
步骤4:在第一绝缘层上形成有源层;
步骤5:在完成上述步骤的基板上沉积第二金属薄膜,通过构图工艺形成源极层和漏极层;
步骤6:在完成上述步骤的基板上沉积第二绝缘层;
步骤7:在第二绝缘层上沉积第一透明电极薄膜,通过过孔与所述公共电极层电性连接形成透明电极层;
步骤8:在完成上述步骤的基板上沉积第三绝缘层;
步骤9:在第三绝缘层上沉积第二透明电极薄膜,形成透明像素电极层。
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