CN108878461A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 51
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Abstract
本申请公开了一种半导体器件及其制造方法,涉及半导体技术领域。该器件包括:设置在器件晶片的电介质层中的金属连线;位于金属连线上方的第一开口,第一开口的深度与金属连线齐平;位于器件两端的第二开口,第二开口的深度与第一开口的深度相同;覆盖在第一开口和第二开口的侧壁上的隔离层,隔离层由滤色材料构成。该器件和方法能够简化焊盘引出和隔离的工艺步骤,满足背面密封环的技术需求。
Description
技术领域
本申请涉及半导体技术领域,特别涉及一种半导体器件及其制造方法。
背景技术
现有的BSI(Back-side illuminated,背照式)器件需要多道光刻层次及蚀刻工艺(如背面硅光刻或蚀刻、层间电介质沉积、布线沉积等)来实现焊盘引出和隔离,这种工艺的步骤繁琐且实现成本高。另外,缺乏针对于BSI器件的背面密封环的设计和工艺。
发明内容
本申请的发明人发现上述现有技术中存在的问题,并因此针对所述问题中的至少一个问题提出了一种新的技术方案。
本申请的一个目的是提供一种半导体器件的技术方案,能够简化焊盘引出和隔离的工艺步骤,并能够满足背面密封环的技术需求。
根据本申请的第一方面,提供了一种半导体器件,包括:设置在器件晶片的电介质层中的金属连线;位于所述金属连线上方的第一开口,所述第一开口的深度与所述金属连线齐平;覆盖在所述第一开口的侧壁上的第一隔离层,所述第一隔离层由第一滤色材料构成。
可选地,该器件还包括:位于所述器件两端的第二开口,所述第二开口的深度与所述第一开口的深度相同;覆盖在所述第二开口的侧壁上的第二隔离层,所述第二隔离层由第二滤色材料构成。
可选地,该器件还包括:位于所述器件晶片上的像素区,所述像素区包括由金属栅格隔开的填充有第三滤色材料的多个单元;位于所述多个单元上的微透镜。
可选地,所述第一滤色材料与所述第二滤色材料由一种或多种颜色的滤色材料构成。
可选地,所述第一开口和所述第二开口的开口深度小于或等于3μm;所述第一开口的宽度大于或等于40μm。
可选地,该器件还包括:用于承载所述器件晶片的载体晶片。
根据本申请的另一个方面,提供一种半导体器件的制造方法,包括:提供器件晶片,所述器件晶片的电介质层中形成有金属连线;在所述金属连线的上方形成第一开口,开口深度与所述金属连线平齐;在所述第一开口的侧壁上覆盖第一滤色材料以形成第一隔离层。
可选地,该方法还包括:在所述器件两端分别形成第二开口,其开口深度与所述第一开口的开口深度相同;在所述第二开口的侧壁上覆盖第二滤色材料分别形成第二隔离层。
可选地,该方法还包括:在所述器件晶片上形成图案化的金属栅格;在所述金属栅格之间的每个间隙中分别填充第三滤色材料;在每个所述间隙上方分别形成微透镜。
可选地,所述第一隔离层和所述第二隔离层均通过曝光显影一种或多种滤色材料来形成。
可选地,所述金属栅格由铝或者钨构成。
可选地,所述第一开口和所述第二开口的深度小于或等于3μm;所述第一开口的宽度大于或等于40μm。
可选地,该方法还包括:提供用于承载所述器件晶片的载体晶片。
本申请的一个优点在于,通过对滤色材料曝光显影来形成隔离层简化了焊盘引出和隔离的工艺步骤;通过在器件两端的开口形成划片道满足了背面密封环的技术需求。
附图说明
构成说明书的一部分的附图描述了本申请的实施例,并且连同说明书一起用于解释本申请的原理。
参照附图,根据下面的详细描述,可以更加清楚地理解本申请,其中:
图1示出本申请的半导体器件的一个实施例的结构图。
图2示出本申请的半导体器件的另一个实施例的结构图。
图3示出本申请的半导体器件制造方法的一个实施例的流程图。
图4示出本申请的半导体器件制造方法的一个步骤的示意图。
图5示出本申请的半导体器件制造方法的另一个步骤的示意图。
图6示出本申请的半导体器件制造方法的另一个实施例的流程图。
图7示出本申请的半导体器件制造方法的又一个实施例的流程图。
图8示出本申请的半导体器件制造方法的又一个步骤的示意图。
图9示出本申请的半导体器件制造方法的再一个步骤的示意图。
图10示出本申请的半导体器件制造方法的再一个步骤的示意图。
具体实施方式
现在将参照附图来详细描述本申请的各种示例性实施例。应注意到:除非另外具体说明,否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本申请的范围。
同时,应当明白,为了便于描述,附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的,决不作为对本申请及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论,但在适当情况下,所述技术、方法和设备应当被视为授权说明书的一部分。
在这里示出和讨论的所有示例中,任何具体值应被解释为仅仅是示例性的,而不是作为限制。因此,示例性实施例的其它示例可以具有不同的值。
应注意到:相似的标号和字母在下面的附图中表示类似项,因此,一旦某一项在一个附图中被定义,则在随后的附图中不需要对其进行进一步讨论。
图1示出本申请的半导体器件的一个实施例的结构图。
如图1所示,该器件包括:器件晶片11、金属连线13、第一开口14和第一隔离层15。
在一个实施例中,器件晶片11包括:硅层19和电介质层12,电介质层12中设置有金属连线13,位于金属连线13上方的第一开口14的深度与金属连线13平齐,第一开口14的侧壁上覆盖有第一隔离层15,第一隔离层15由一种颜色的滤色材料或多种颜色的滤色材料叠加而成,如红、黄和绿三种颜色的滤色材料。
在另一个实施例中,该器件还包括:第二开口16和第二隔离层17。
第二开口16位于器件两端,且开口深度与第一开口15相同,第二隔离层17覆盖于第二开口16的侧壁,第二隔离层16由一种颜色的滤色材料或多种颜色的滤色材料叠加而成,如红、黄和绿三种颜色的滤色材料。其中,构成第二隔离层16与第一隔离层15的滤色材料可以相同也可以不同。
在一个实施例中,器件晶片11下方还设置有由硅构成的载体晶片18。
上述实施例中,利用滤色材料在第一开口侧壁形成隔离层,简化了焊盘引出和隔离的工艺步骤;通过位于器件两端的开口,形成划片道满足了背面密封环的技术需求。
图2示出本申请的半导体器件的另一个实施例的结构图。
图2所示,在上一个实施例的基础上该器件上还设置有像素区,像素区包括:金属栅格21、滤色材料22和微透镜23。
金属栅格21的间隙形成了多个单元,在单元中填充有滤色材料22,微透镜23位于每个单元上面。在一个实施例中,在器件晶片11上沉积有氧化物层17,电介质层12中可以设置有多条由通孔26连通的金属连线25,金属栅格21由钨或者铝构成,滤色材料22可以是红、黄或绿色,与上述的第一滤色材料和第二滤色材料可以相同或不同。
上述实施例中,隔离层由滤色材料构成,具有良好的绝缘性和不透光性,金属连线可以实现焊盘引出,简化了焊盘引出和隔离的工艺步骤;器件两端的第二开口形成划片道,满足了背面密封环的技术需求。
图3示出本申请的半导体器件制造方法的一个实施例的流程图。
图3所示,该方法包括:步骤301,提供器件晶片,器件晶片的电介质层中形成有金属连线。
在一个实施例中,如图4所示,在电介质层中42中设置金属连线44,在电介质层42上沉积硅层43以得到器件晶片41,提供用于承载器件晶片41的载体晶片47。还可以在电解质层中设置多条由通孔46连接的金属连线45。
步骤302,在金属连线的上方形成第一开口,开口深度与金属连线平齐。
步骤303,在第一开口的侧壁上覆盖第一滤色材料以形成第一隔离层。
在一个实施例中,如图5所示,在金属连线44上方开口,以形成第一开口51,开口深度可以小于或等于3μm,宽度可以小于或等于40μm;通过对滤色材料进行曝光显影,在第一开口51的侧壁上形成第一隔离层52,滤色材料可以是一种颜色或多种颜色的叠加。
在另一个实施中,如图6所示,该方法还包括:步骤601,在器件两端分别形成第二开口,其开口深度与第一开口的开口深度相同。
步骤602,在第二开口的侧壁上覆盖第二滤色材料分别形成第二隔离层。
在一个实施例中,如图5所示,第二开口53的深度与第一开口51的深度相同,可以小于或等于3μm;通过对滤色材料进行曝光显影,在第二开口53的侧壁上形成第二隔离层54,滤色材料可以是一种颜色或多种颜色的叠加。其中,形成第一隔离层和第二隔离层的滤色材料可以相同也可以不同。
上述实施例中,利用滤色材料在第一开口侧壁形成隔离层,简化了焊盘引出和隔离的工艺步骤;通过位于器件两端的开口,形成划片道满足了背面密封环的技术需求。
图7示出本申请的半导体器件制造方法的又一个实施例的流程图。
图7所示,该方法包括:步骤701,在器件晶片上形成图案化的金属栅格。
在一个实施例中,如图8所示,在所述器件晶片41上沉积抗反射层82和缓冲氧化物层81,并在缓冲氧化物层81上形成金属栅格83,抗反射层82可以由铪的氧化物或铝的氧化物构成,金属栅格83可以由铝或者钨构成;沉积氧化物81并进行平坦化处理(如化学机械平坦化)。
如图9所示,移除金属栅格83间隙中的氧化物以形成单元91;在金属连线44上方以及器件两端开口以形成第一开口92和第二开口93,第一开口92的深度与金属连线44平齐,第二开口93与第一开口92的深度相同。
步骤702,在金属栅格的间隙中填充滤色材料。
步骤703,在间隙上方分别形成微透镜。
在一个实施例中,如图10所示,在金属栅格83的间隙内填充滤色材料101(可以是红色、黄色或绿色),在每个间隙上设置微透镜104;在第一开口92和第二开口93的侧壁上,分别对滤色材料进行曝光显影以形成第一隔离层102和第二隔离层103。其中,第一隔离层、第二隔离层与金属栅格间隙中填充的滤色材料可以相同也可以不同。
上述实施例中,通过对滤色材料曝光显影形成隔离层,不但具有良好的绝缘性和不透光性,而且简化了焊盘引出和隔离的工艺步骤;器件两端的第二开口形成划片道,满足了背面密封环的技术需求。
至此,已经详细描述了根据本申请的半导体器件及其制造方法。为了避免遮蔽本申请的构思,没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述,完全可以明白如何实施这里公开的技术方案。
可能以许多方式来实现本申请的方法和***。例如,可通过软件、硬件、固件或者软件、硬件、固件的任何组合来实现本申请的方法和***。用于所述方法的步骤的上述顺序仅是为了进行说明,本申请的方法的步骤不限于以上具体描述的顺序,除非以其它方式特别说明。此外,在一些实施例中,还可将本申请实施为记录在记录介质中的程序,这些程序包括用于实现根据本申请的方法的机器可读指令。因而,本申请还覆盖存储用于执行根据本申请的方法的程序的记录介质。
虽然已经通过示例对本申请的一些特定实施例进行了详细说明,但是本领域的技术人员应该理解,以上示例仅是为了进行说明,而不是为了限制本申请的范围。本领域的技术人员应该理解,可在不脱离本申请的范围和精神的情况下,对以上实施例进行修改。本申请的范围由所附权利要求来限定。
Claims (13)
1.一种半导体器件,包括:
设置在器件晶片的电介质层中的金属连线;
位于所述金属连线上方的第一开口,所述第一开口的深度与所述金属连线齐平;
覆盖在所述第一开口的侧壁上的第一隔离层,所述第一隔离层由第一滤色材料构成。
2.根据权利要求1所述的器件,还包括:
位于所述器件两端的第二开口,所述第二开口的深度与所述第一开口的深度相同;
覆盖在所述第二开口的侧壁上的第二隔离层,所述第二隔离层由第二滤色材料构成。
3.根据权利要求2所述的器件,还包括:
位于所述器件晶片上的像素区,所述像素区包括由金属栅格隔开的填充有第三滤色材料的多个单元;
位于所述多个单元上的微透镜。
4.根据权利要求2所述的器件,其中,
所述第一滤色材料与所述第二滤色材料由一种或多种颜色的滤色材料构成。
5.根据权利要求2所述的器件,其中,
所述第一开口和所述第二开口的开口深度小于或等于3μm;
所述第一开口的宽度大于或等于40μm。
6.根据权利要求1-5中任一项所述的器件,还包括:
用于承载所述器件晶片的载体晶片。
7.一种半导体器件的制造方法,包括:
提供器件晶片,所述器件晶片的电介质层中形成有金属连线;
在所述金属连线的上方形成第一开口,开口深度与所述金属连线平齐;
在所述第一开口的侧壁上覆盖第一滤色材料以形成第一隔离层。
8.根据权利要求7所述的方法,还包括:
在所述器件两端分别形成第二开口,其开口深度与所述第一开口的开口深度相同;
在所述第二开口的侧壁上覆盖第二滤色材料分别形成第二隔离层。
9.根据权利要求8所述的方法,还包括:
在所述器件晶片上形成图案化的金属栅格;
在所述金属栅格之间的间隙中填充第三滤色材料;
在所述间隙上方形成微透镜。
10.根据权利要求8所述的方法,其中,
所述第一隔离层和所述第二隔离层均通过曝光显影一种或多种滤色材料来形成。
11.根据权利要求9所述的方法,其中,
所述金属栅格由铝或者钨构成。
12.根据权利要求10所述的方法,其中,
所述第一开口和所述第二开口的深度小于或等于3μm;
所述第一开口的宽度大于或等于40μm。
13.据权利要求7-12任一项所述的方法,还包括:
提供用于承载所述器件晶片的载体晶片。
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