CN108809302A - A kind of phase-locked loop frequency integrator and control method for frequency - Google Patents
A kind of phase-locked loop frequency integrator and control method for frequency Download PDFInfo
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- CN108809302A CN108809302A CN201810595966.2A CN201810595966A CN108809302A CN 108809302 A CN108809302 A CN 108809302A CN 201810595966 A CN201810595966 A CN 201810595966A CN 108809302 A CN108809302 A CN 108809302A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
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Abstract
Present disclose provides a kind of phase-locked loop frequency integrator and control method for frequency, wherein the phase-locked loop frequency integrator includes：Control code generation module is configured to default correspondence, generates the first control code corresponding with the first signal received, the default correspondence includes signal frequency and control code correspondence；Phaselocked loop, it is configured to the lock operation that first control code executes the frequency of signal, so that the frequency of the second signal exported after lock operation is identical as the frequency of the first signal, wherein, the phaselocked loop includes voltage controlled oscillator, and the control code generation module is connect with the switched capacitor array in the voltage controlled oscillator, to adjust the capacitor value of the switched capacitor array by first control code.The embodiment of the present disclosure has simple in structure, and the technique effect that locking time is short.
Description
Technical field
This disclosure relates to communicate and integrated circuit fields, more particularly to a kind of phase-locked loop frequency integrator and FREQUENCY CONTROL side
Method.
Background technology
Digital electronic system needs clock reference to provide time reference for entire electronic system, and wireless communication system needs this
The signal that shakes completes frequency transformation to realize sending and receiving for wireless communication signals, when phase-locked loop frequency integrator is to provide above-mentioned
Between benchmark and local oscillation signal common module, the performance of phase-locked loop frequency integrator is to digital electronic system and wireless communication system
Influence it is very big, locking time is one of key index of phase-locked loop frequency integrator.
In the prior art, the locking time of phase-locked loop frequency integrator includes mainly that AFC (automatic frequency calibrator) is carried out
The locking time of frequency coarse adjustment and PLL (phaselocked loop) carry out the locking time of frequency trim.When AFC carries out the locking of frequency coarse adjustment
Between mainly determined by the structure of the control algolithm of AFC, the digit of control code and AFC, traditional way is, when communication system needs
When corresponding local frequency, AFC can search out the control code of suitable VCO switch arrays to generate as far as possible according to control algolithm
Close to the phase-locked loop frequency integrator output frequency of required local frequency, then generated by the frequency trim of PLL locking processes
Local frequency needed for accurate.In the locking process of frequency synthesizer, the frequency coarse tuning process of AFC occupies locking time
It is most of, therefore the disadvantage of locking time length exists in the prior art.
Invention content
In view of this, that the present disclosure proposes a kind of is comprehensive with simple in structure and with quick lock in function phase-locked loop frequency
Clutch and control method for frequency.
According to the disclosure in a first aspect, providing a kind of phase-locked loop frequency integrator comprising：
Control code generation module is configured to default correspondence, generates corresponding with the first signal of reception the
One control code, the default correspondence include signal frequency and control code correspondence；
Phaselocked loop is configured to the lock operation that first control code executes the frequency of signal so that locking behaviour
The frequency of the second signal exported after work is identical as the frequency of the first signal；
Wherein, the phaselocked loop includes voltage controlled oscillator, and the control code generation module and the voltage controlled oscillator
Interior switched capacitor array connection, to adjust the capacitor value of the switched capacitor array by first control code.
In some possible embodiments, the phaselocked loop includes：
Phase frequency detector is configured to obtain the difference of the first parameter between first signal and the third signal of feedback
Value；
Adjustment module is connect with the control code generation module and the phase frequency detector respectively, and is based on the difference
Value and first control code adjust the frequency of oscillation of the voltage controlled oscillator in it, to export fourth signal；
Frequency divider, is configured to carry out scaling down processing to the fourth signal to obtain the third signal, and by described the
Three signals feed back to the phase frequency detector,
Wherein, the second signal is the difference when being steady state value, the signal based on adjustment module output.
In some possible embodiments, the adjustment module includes：
Charge pump is configured to the difference and generates corresponding current controling signal；
Loop filter is configured to be filtered current controling signal execution, and by the letter after being filtered
Number be converted to voltage control signal；
Voltage controlled oscillator adjusts its frequency of oscillation based on the voltage control signal and first control code, and defeated
Go out the fourth signal.
In some possible embodiments, the adjustment module includes：
Charge pump is configured to the difference and generates corresponding current controling signal；
Loop filter is configured to be filtered current controling signal execution, and by the letter after being filtered
Number be converted to voltage control signal；
Voltage controlled oscillator adjusts its frequency of oscillation based on the voltage control signal and first control code, and defeated
Go out the 5th signal；
Two-divider is configured to carry out scaling down processing to the 5th signal, obtains the fourth signal, wherein described
The frequency of fourth signal is the half of the frequency of the 5th signal.
In some possible embodiments, the voltage controlled oscillator is further configured to adjust by first control code
The capacitor value of switched capacitor array in it, and the capacitor value of the tunable capacitor in it is adjusted by the voltage control signal,
To adjust its frequency of oscillation.
In some possible embodiments, further include：
Reference clock module is connect with the control code generation module and the phaselocked loop respectively, and exports described
One signal.
In some possible embodiments, the control code generation module includes：
Processing module is configured to transmit the second different control codes to the phaselocked loop, and obtains phaselocked loop and execute lock
The frequency of the output signal exported after fixed operation, and the frequency based on second control code and corresponding output signal establishes institute
State default correspondence.
According to the second aspect of the disclosure, a kind of control method for frequency is provided comprising：
Based on default correspondence, the first control corresponding with the first signal received is generated using control code generation module
Code, the default correspondence includes signal frequency and control code correspondence；
The lock operation of the frequency of signal is executed based on first control code by phaselocked loop so that defeated after lock operation
The frequency of the second signal gone out is identical as the frequency of the first signal；
Wherein, the phaselocked loop includes voltage controlled oscillator, and the control code generation module and the voltage controlled oscillator
Interior switched capacitor array connection, to adjust the capacitor value of the switched capacitor array by first control code.
In some possible embodiments, the frequency for executing signal based on first control code by phaselocked loop
Lock operation includes：
The difference of the first parameter between first signal and the third signal of feedback is obtained, first parameter includes
Phase and frequency；
Frequency of oscillation is adjusted based on the difference and the control code, to export fourth signal；
Scaling down processing is carried out to the fourth signal and obtains the third signal, and the third signal is fed back into locking phase
The input side of ring.
In some possible embodiments, further include：
The second different control codes is transmitted to the phaselocked loop；
After phaselocked loop executes lock operation, the frequency of the output signal of its output is obtained；
Frequency based on second control code and corresponding output signal establishes the default correspondence.
The embodiment of the present disclosure, the embodiment of the present disclosure can realize phase-locked loop frequency integrator quick lock in, in locking process
In, compared to the locking time that the traditional structure phase-locked loop frequency integrator can save automatic frequency calibrator so that phaselocked loop
The locking time of frequency synthesizer reduces by 40%~70% compared to traditional structure；For the phase-locked loop frequency integrator, into
The process of line frequency coarse adjustment is exactly by the control code indirect assignment in default correspondence to the switched capacitor array in phaselocked loop,
AFC can not be used during frequency coarse adjustment, thus reduces the power consumption of phase-locked loop frequency integrator；
In addition, since above-mentioned default correspondence can be pre-established in the embodiment of the present disclosure, without into line frequency
Corresponding frequency is tested to carry out frequency coarse adjustment by different control code when rate locks, thus avoid in the prior art due to
External environment changes the influence to frequency, frequency degree of regulation higher.
According to below with reference to the accompanying drawings to detailed description of illustrative embodiments, the other feature and aspect of the disclosure will become
It is clear.
Description of the drawings
Including in the description and the attached drawing of a part for constitution instruction and specification together illustrate the disclosure
Exemplary embodiment, feature and aspect, and for explaining the principles of this disclosure.
Fig. 1 shows the block diagram of the phase-locked loop frequency integrator according to the embodiment of the present disclosure；
Fig. 2 shows the block diagrams of the phaselocked loop in the phase-locked loop frequency integrator according to the embodiment of the present disclosure；
Fig. 3 shows the block diagram of the adjustment module in the phase-locked loop frequency integrator according to the embodiment of the present disclosure；
Fig. 4 shows the circuit structure diagram of the voltage controlled oscillator in the phase-locked loop frequency integrator according to the embodiment of the present disclosure；
Fig. 5 shows the block diagram according to the adjustment module in the phase-locked loop frequency integrator in the disclosure other embodiments；
Fig. 6 shows the phase-locked loop frequency integrator being made up of adjustment module shown in Fig. 5 according to the embodiment of the present disclosure
Structural schematic diagram；
Fig. 7 shows the block diagram of the phase-locked loop frequency integrator according to the embodiment of the present disclosure；
Fig. 8 shows the flow chart of the control method for frequency according to the embodiment of the present disclosure.
Specific implementation mode
Various exemplary embodiments, feature and the aspect of the disclosure are described in detail below with reference to attached drawing.It is identical in attached drawing
Reference numeral indicate functionally the same or similar element.Although the various aspects of embodiment are shown in the accompanying drawings, remove
It non-specifically points out, it is not necessary to attached drawing drawn to scale.
Dedicated word " exemplary " means " being used as example, embodiment or illustrative " herein.Here as " exemplary "
Illustrated any embodiment should not necessarily be construed as preferred or advantageous over other embodiments.
In addition, in order to better illustrate the disclosure, numerous details is given in specific implementation mode below.
It will be appreciated by those skilled in the art that without certain details, the disclosure can equally be implemented.In some instances, for
Method, means, element and circuit well known to those skilled in the art are not described in detail, in order to highlight the purport of the disclosure.
Fig. 1 shows the block diagram of the phase-locked loop frequency integrator according to the embodiment of the present disclosure.Wherein, in the embodiment of the present disclosure
Phase-locked loop frequency integrator may include：Control code generation module 10 and phaselocked loop connected to it 20.
Control code generation module 10 in the embodiment of the present disclosure is used to control the control code of the frequency of oscillation of phaselocked loop 20, should
Frequency of oscillation of the control code for phaselocked loop carries out coarse adjustment.Wherein, the control code generation module 10 in the embodiment of the present disclosure can
To be based on default correspondence, the first control code corresponding with the first signal received is generated, the default correspondence includes
Signal frequency and control code correspondence.
Wherein, the default correspondence in the embodiment of the present disclosure may include different signal frequency, and with each signal
The unique corresponding control code of frequency, i.e., can quickly and easily find corresponding control code by the frequency information of signal
Information.The sequence that the control code can be made of " 0 " and " 1 ", for control the corresponding electronic device of phaselocked loop connection and
Shutdown, to change the frequency of oscillation of phaselocked loop.
In addition, control code generation module 10 can receive the first signal in real time, and can when receiving the first signal,
The first corresponding control code is quickly found according to the frequency information of first signal, is further controlled phaselocked loop and is executed
Lock operation based on first signal.Wherein, the first signal can be the reference clock needed for communication system, and frequency can be with
It is the required local frequency of communication system.The communication system is the communication system where phase-locked loop frequency integrator.According to logical
Believe agreement, when needing the local oscillation signal of corresponding frequencies in communication process, controller generation module can inquire above-mentioned default correspondence
Then relationship directly exports switched capacitor array of first control code to the voltage controlled oscillator (VCO) of phaselocked loop, carry out frequency rough
It adjusts.The locking time of the frequency generation module of phase-locked loop frequency integrator is only the time of look-up table inquiry, without multiple
The corresponding signal frequency of different control codes is tested, the time that frequency synthesizer carries out output frequency coarse adjustment is greatly reduced.
In addition, the default correspondence of the embodiment of the present disclosure can be stored in control code generation module 10, can also deposit
Storage is in a memory 30, and the embodiment of the present disclosure is to this without limiting.
In the embodiment of the present disclosure, the mode that control code generation module 10 generates the first control code may include：At default pair
As found in relationship with the immediate second frequency of the first frequency of the first signal, i.e., each frequency in default correspondence can
Can be different from first frequency, but the embodiment of the present disclosure can determine that difference is minimum between first frequency in default correspondence
Second frequency corresponding first control is determined based on the second frequency that is, with the immediate second frequency of first frequency
Code, as the first control code corresponding with the first signal determined by control code generation module 10.
Based on above-mentioned configuration, since the control code generation module 10 in the embodiment of the present disclosure can be easily according to the first letter
Number frequency search to corresponding control code, without as AFC in the prior art (automatic frequency calibrator),
It needs to firstly generate a control code, obtains the frequency of oscillation in the corresponding phaselocked loop of the control code, to which constantly test is sought
Suitable control code is found to generate the frequency of oscillation as far as possible with phaselocked loop similar in local frequency.I.e. the embodiment of the present disclosure is logical
The setting for crossing default correspondence, can conveniently find the frequency of oscillation control code being close with local frequency, greatly
The earth shortens between frequency rough timing.
In addition, in the embodiments of the present disclosure, after communication system powers on, phase-locked loop frequency integrator will carry out powering on initial
Change, a task objective of initialization is that establish VCO switched capacitor arrays control code corresponding with frequency synthesizer output frequency
Relationship generates above-mentioned default correspondence (LUT).
For example, in initial configuration, control code generation module 10 can transmit the second different control to phaselocked loop 20
Code, and obtain phaselocked loop 20 and execute the frequency of output signal exported after lock operation, and based on second control code and right
The frequency for the output signal answered establishes the default correspondence.That is, control code generation module 10 can be by phaselocked loop 20
Transmit different control codes, the correspondence for then obtaining frequency of oscillation of the phaselocked loop based on the control code, and both establishing with
Above-mentioned default correspondence is generated, to complete to preset the initialization operation of correspondence.
Wherein, the mode for obtaining the frequency of the output signal in phaselocked loop may include by counter to phase-locked loop frequency
The output signal of synthesizer is counted, and obtains count value M, and compared with the count value N of reference-input signal during this period
Compared with, and then obtain the corresponding output frequency of phase-locked loop frequency integrator under different control codes.It then can be by control code and lock
The output frequency of phase ring frequency synthesizer is established default correspondence accordingly and is stored.In subsequent operating process, i.e.,
The coarse adjustment operation that correspondence executes phaselocked loop can be preset according to this.
Based on above-mentioned configuration, communication system after the power is turned on, needs to complete to initialize to establish frequency look-up table, is subsequently generated code control
Molding block can almost be ignored in the time for carrying out frequency coarse adjustment, and the locking time of frequency synthesizer is mainly the locking of phaselocked loop
Time substantially reduces the settling time of local frequency switches in communication process time and digital electronic system clock reference.
In addition, the phaselocked loop 20 in the embodiment of the present disclosure can execute the locking of the frequency of signal based on the first control code 10
Operation so that the frequency of the second signal exported after lock operation is identical as the frequency of the first signal.
Wherein, the phaselocked loop of the embodiment of the present disclosure may include voltage controlled oscillator, and control code generation module can be with
Switched capacitor array connection in the voltage controlled oscillator, to adjust the switched capacitor array by first control code
Capacitor value.Based on the configuration, frequency adjustment switch that can be easily and fast based on the first signal by generated code control module
The capacitor value of capacitor array, so as to fast implement the frequency coarse adjustment of frequency synthesizer.
Wherein, the phaselocked loop 20 in the embodiment of the present disclosure can execute the Frequency Locking operation of signal, you can be based on connecing
The first control code for receiving executes frequency coarse adjustment, at the same can also be between basis the first signal received and output signal the
Difference between one parameter, further into line frequency accurate adjustment section, to complete output signal frequency lock operation so that locking
The frequency of the second signal exported after operation is identical as the frequency of the first signal.Wherein, the first parameter includes frequency and phase
Position.
Fig. 2 shows the block diagrams of the phaselocked loop in the phase-locked loop frequency integrator according to the embodiment of the present disclosure.
Wherein, the phaselocked loop 20 in the embodiment of the present disclosure may include：Phase frequency detector 21, adjustment module 22 and frequency divider
23。
Wherein, phase frequency detector 21 can be used for obtaining the first parameter between the first signal and the third signal of feedback
Difference.Adjustment module 22 is connect with the control code generation module 10 and phase frequency detector 21 respectively, and based on the difference and
First control code adjusts frequency of oscillation, to export fourth signal.Frequency divider 23 can divide the fourth signal
Processing obtains the third signal, and the third signal is fed back to the phase frequency detector 21.Wherein, the second signal
When for the difference being steady state value (phase difference and difference on the frequency are constant), the signal that is exported based on the adjustment module 22.
As described in above-described embodiment, the first control code that the first control module 10 in the embodiment of the present disclosure is generated can be with
It is transferred to adjustment module 22, while difference between the first parameter between the first signal and the third signal of the output of frequency divider 23
It is also conveyed to adjustment module 22, adjustment module 22 further can then be adjusted the frequency of oscillation of phaselocked loop according to the difference
Section, until when the difference is invariable, the signal that adjustment module 22 exports is required second signal.
Wherein, due to the coarse adjustment of control code generation module, the initial oscillation of voltage controlled oscillator is close to the first letter
The initial oscillation signal can be fed back to frequency by the second frequency of number frequency values when phaselocked loop is adjusted into line frequency
The signal input part (phase frequency detector 21) of synthesizer, it at this time can be based on the difference of the first parameter between the first signal
The concussion frequency of voltage controlled oscillator is adjusted, until when the difference between first parameter is constant, the 4th letter of adjustment module output
Number be second signal identical with the first signal frequency.
In addition, the frequency divider 23 in the embodiment of the present disclosure can execute the frequency dividing behaviour of the fourth signal exported to Regulate signal
Make, you can to filter out the information of the interference band in fourth signal, have the function of denoising.The setting of frequency divider 23 can basis
The frequency range of first signal is set, and those skilled in the art can be configured according to demand, no longer be said herein
It is bright.
In addition, it can be AFC (automatic frequency calibrator) that the disclosure, which is control code generation module in embodiment, it can also
It is the control assembly (such as MCU) in the device using the phase-locked loop frequency integrator of the embodiment of the present disclosure, i.e., the device can not
AFC is set, inquiry and the generating process of control code are directly executed by the controller configured in device, can be further reduced into
Sheet and power consumption, and there is technique effect simple in structure.
Based on above-mentioned configuration, the embodiment of the present disclosure can in the case where control code generation module 10 carries out frequency coarse adjustment,
Further its output frequency is carried out according to the difference between the first parameter value of the first signal of the signal of phaselocked loop output
Accurate adjustment section, so as to be further ensured that the frequency of output signal.
Fig. 3 shows the block diagram of the adjustment module in the phase-locked loop frequency integrator according to the embodiment of the present disclosure.Wherein, it adjusts
Module 22 may include：Charge pump 221, loop filter 222 and voltage controlled oscillator 223.
Wherein, charge pump 221 can be based on the difference and generate corresponding current controling signal.That is embodiment of the present disclosure kind
Charge pump 221 can be generated according to the difference of the first parameter between the third signal that the first signal and frequency divider 23 export
Current controling signal for the frequency of oscillation for controlling voltage controlled oscillator 223.
Loop filter 222 can execute the current controling signal and be filtered, and by the signal after being filtered
Be converted to voltage control signal.Loop filter 222 can be used for decay the fast-changing phase error caused by noise and
The high fdrequency component smoothly revealed, you can to execute filtering operation, accurately to be estimated original signal in its output end,
The exponent number and noise bandwidth of loop filtering determine dynamic response of the loop filter to signal.In addition, since the disclosure is implemented
Voltage controlled oscillator 223 in example can control its frequency of oscillation by voltage value, therefore can convert current controling signal
At corresponding voltage control signal.
Voltage controlled oscillator 223 can adjust its frequency of oscillation according to voltage control signal and the first control code, and export institute
State fourth signal.Fig. 4 shows the circuit structure of the voltage controlled oscillator in the phase-locked loop frequency integrator according to the embodiment of the present disclosure
Figure, wherein voltage controlled oscillator 223 may include：Configurable bias voltage 2231, switched capacitor array 2232, LC oscillators 2233
With output driving 2234.
Wherein, it can configure bias voltage 2231 to be used to provide voltage electricity for voltage controlled oscillator 223, ensure voltage controlled oscillator
Normal work.
Switched capacitor array 2232 is connect with control code generation module 10, to execute correspondence according to the first control code of reception
Branch turns on and off, and then the capacitor value of regulating switch capacitor array 2232.As shown in figure 4, switched capacitor array 2232
In may include multiple branches parallel with one another (such as a, b, c, d and e), wherein each branch include a switching device and
The capacitor being connected in series with, wherein switching device may include the devices such as metal-oxide-semiconductor, and each switching device can give birth to control code respectively
It is connected at module 10, operation is turned on and off to be executed respectively according to the first control code.As described above, the first control code can be
The sequence being made of " 0 " and " 1 ".Shutdown operation can be executed by wherein receiving the switching device of " 0 " code word, correspond to branch
Capacitor will not be then linked into circuit, received the switching device of " 1 " and can be executed making operation, corresponding branch
Capacitor can be then linked into circuit, to corresponding adjust the capacitance being linked into circuit by the first control code
Device, with the capacitor value of regulating switch capacitor array 2232.And the oscillation of voltage controlled oscillator 223 can be executed based on the capacitor value
The coarse adjustment of frequency.
LC oscillators 2233 can be connect with adjustment module 222, and to receive the voltage control signal of its output, and being based on should
Voltage control signal adjust tunable capacitor capacitor value, to execute voltage controlled oscillator 223 frequency of oscillation accurate adjustment section.Pass through
Above-mentioned voltage control signal can be input to VtuneAt node, it can be adjusted by the size of the voltage value in voltage control signal
The capacitor value of variable capacitance capbank is saved, the accurate adjustment section to execute frequency of oscillation can by above-mentioned coarse adjustment and accurate adjustment section
To execute the adjusting of the frequency of oscillation of voltage controlled oscillator.Due to the configuration of coarse adjustment, frequency of oscillation and the first signal may be implemented
Frequency be close, identical with the frequency of the first signal frequency of oscillation of output that can be fast and accurately by accurate adjustment section.
Output driving 2234 is that voltage controlled oscillator 223 provides output driving electric power, and those skilled in the art can be according to need
It asks and is set, herein without repeating.
Based on above-mentioned configuration, the coarse adjustment based on the first control code may be implemented in voltage controlled oscillator, and is based on voltage control
The accurate adjustment section for making instruction, it is anti-after directly divided 23 scaling down processing of device of the fourth signal that voltage controlled oscillator 223 can be output it
It feeds phase frequency detector 21, voltage control is further adjusted to the difference of the first parameter based on third signal and the first signal
Signal, until when the difference is constant, the frequency of oscillation of voltage controlled oscillator is equal with the first signal.
Fig. 5 shows the block diagram according to the adjustment module in the phase-locked loop frequency integrator in the disclosure other embodiments,
And Fig. 6 shows the structure for the phase-locked loop frequency integrator being made up of the adjustment module shown in Fig. 5 according to the embodiment of the present disclosure
Schematic diagram.
Wherein, adjustment module 22 may include：Charge pump 221, loop filter 222, voltage controlled oscillator 223 and two divided-frequency
Device 224.
Wherein, the configuration of charge pump 221, loop filter 222 and voltage controlled oscillator 223 can be with above-described embodiment
Configure it is identical, herein without be described in detail.In the embodiments of the present disclosure, the oscillator signal that voltage controlled oscillator can be exported
Referred to as the 5th signal, two-divider 224 connected to it can carry out scaling down processing to the frequency of the 5th signal, obtain the 4th letter
Number, wherein the frequency of fourth signal is the half of the frequency of the 5th signal.
The fourth signal again by feeding back to phase frequency detector after 23 scaling down processing of frequency divider, to based on third signal and
The difference of first parameter of the first signal further adjusts voltage control signal, until when the difference of first parameter is constant, two
The frequency of the fourth signal of frequency divider output is equal with the frequency of the first signal.In addition, two distribution in the embodiment of the present disclosure
The signal (RX and TX) of device output can be provided separately to the local frequency of radio frequency sending set and radio-frequency transmitter.
By the embodiment of the present disclosure, the feedback regulation of signal may be implemented, to easily realize shaking for voltage controlled oscillator
The adjusting of frequency is swung, and required second signal identical with the first signal frequency is obtained based on the frequency of oscillation.
Further, Fig. 7 shows the block diagram of the phase-locked loop frequency integrator according to the embodiment of the present disclosure.Wherein, it is based on Fig. 1
Embodiment, can further include reference clock module 40, the reference clock module 40 can respectively with control code generate
Module 10 and the phaselocked loop 20 connect, and can generate and export first signal.It needs to adjust local oscillator in communication system
When signal, the first signal for adjusting reference clock module 40 and generating respective frequencies being adapted to can then pass through control code
Generation module 10 carries out coarse adjustment to phaselocked loop 20, while phaselocked loop realizes the accurate adjustment section of frequency of oscillation based on feedback regulation, until
Output second signal identical with the first signal frequency.
In conclusion the embodiment of the present disclosure can realize phase-locked loop frequency integrator quick lock in, in locking process, phase
Than the locking time that the traditional structure phase-locked loop frequency integrator can save automatic frequency calibrator so that phase-locked loop frequency is comprehensive
The locking time of clutch reduces by 40%~70% compared to traditional structure；For the phase-locked loop frequency integrator, into line frequency
The process of coarse adjustment is exactly by the control code indirect assignment in default correspondence to phaselocked loop, can be with during frequency coarse adjustment
It is not turned on AFC or opens the very short time, thus reduce the power consumption of phase-locked loop frequency integrator.
In addition, the embodiment of the present disclosure additionally provides a kind of control method for frequency, apply as described in above-described embodiment
In phase-locked loop frequency integrator, the corresponding technical solution of method and description may refer to the corresponding of phase-locked loop frequency integrator part
It records, repeats no more.
Fig. 8 shows the flow chart of the control method for frequency according to the embodiment of the present disclosure, wherein may include：
S100：Based on default correspondence, corresponding with the first signal of reception the is generated using control code generation module
One control code, the default correspondence include signal frequency and control code correspondence；
S200：The lock operation of the frequency of signal is executed based on first control code by phaselocked loop so that locking behaviour
The frequency of the second signal exported after work is identical as the frequency of the first signal, wherein the frequency includes frequency；
Wherein, the phaselocked loop includes voltage controlled oscillator, and the control code generation module and the voltage controlled oscillator
Interior switched capacitor array connection, to adjust the capacitor value of the switched capacitor array by first control code.
In a kind of possible embodiment, the frequency for executing signal based on first control code by phaselocked loop
Lock operation includes：
The difference of the first parameter between first signal and the third signal of feedback is obtained, first parameter includes
Phase and frequency；
Frequency of oscillation is adjusted based on the difference and the control code, to export fourth signal；
Scaling down processing is carried out to the fourth signal and obtains the third signal, and the third signal is fed back into locking phase
The input side of ring.
In a kind of possible embodiment, the frequency for executing signal based on first control code by phaselocked loop
Lock operation includes：
Obtain the difference of the first parameter between first signal and the third signal of feedback；
Frequency of oscillation is adjusted based on the difference and the control code, to export the 5th signal；
Two divided-frequency processing is carried out to the 5th signal by two-divider, obtains fourth signal；
Scaling down processing is carried out to the fourth signal and obtains the third signal, and the third signal is fed back into locking phase
The input side of ring.
In a kind of possible embodiment, the method further includes：
The second different control codes is transmitted to the phaselocked loop 23；
After phaselocked loop executes lock operation, the frequency of the output signal of its output is obtained；
Frequency based on second control code and corresponding output signal establishes the default correspondence.
In conclusion the embodiment of the present disclosure can realize phase-locked loop frequency integrator quick lock in, in locking process, phase
Than the locking time that the traditional structure phase-locked loop frequency integrator can save automatic frequency calibrator so that phase-locked loop frequency is comprehensive
The locking time of clutch reduces by 40%~70% compared to traditional structure；For the phase-locked loop frequency integrator, into line frequency
The process of coarse adjustment is exactly by the control code indirect assignment in default correspondence to phaselocked loop, can be with during frequency coarse adjustment
It is not turned on AFC or opens the very short time, thus reduce the power consumption of phase-locked loop frequency integrator.
The disclosure can be system, method and/or computer program product.Computer program product may include computer
Readable storage medium storing program for executing, containing for making processor realize the computer-readable program instructions of various aspects of the disclosure.
Computer readable storage medium can be can keep and store the instruction used by instruction execution equipment tangible
Equipment.Computer readable storage medium for example can be-- but be not limited to-- storage device electric, magnetic storage apparatus, optical storage
Equipment, electromagnetism storage device, semiconductor memory apparatus or above-mentioned any appropriate combination.Computer readable storage medium
More specific example (non exhaustive list) includes：Portable computer diskette, random access memory (RAM), read-only is deposited hard disk
It is reservoir (ROM), erasable programmable read only memory (EPROM or flash memory), static RAM (SRAM), portable
Compact disk read-only memory (CD-ROM), digital versatile disc (DVD), memory stick, floppy disk, mechanical coding equipment, for example thereon
It is stored with punch card or groove internal projection structure and the above-mentioned any appropriate combination of instruction.Calculating used herein above
Machine readable storage medium storing program for executing is not interpreted that instantaneous signal itself, the electromagnetic wave of such as radio wave or other Free propagations lead to
It crosses the electromagnetic wave (for example, the light pulse for passing through fiber optic cables) of waveguide or the propagation of other transmission mediums or is transmitted by electric wire
Electric signal.
Computer-readable program instructions as described herein can be downloaded to from computer readable storage medium it is each calculate/
Processing equipment, or outer computer or outer is downloaded to by network, such as internet, LAN, wide area network and/or wireless network
Portion's storage device.Network may include copper transmission cable, optical fiber transmission, wireless transmission, router, fire wall, interchanger, gateway
Computer and/or Edge Server.Adapter or network interface in each calculating/processing equipment are received from network to be counted
Calculation machine readable program instructions, and the computer-readable program instructions are forwarded, for the meter being stored in each calculating/processing equipment
In calculation machine readable storage medium storing program for executing.
For execute the disclosure operation computer program instructions can be assembly instruction, instruction set architecture (ISA) instruction,
Machine instruction, machine-dependent instructions, microcode, firmware instructions, condition setup data or with one or more programming languages
Arbitrarily combine the source code or object code write, the programming language include the programming language-of object-oriented such as
Smalltalk, C++ etc., and conventional procedural programming languages-such as " C " language or similar programming language.Computer
Readable program instructions can be executed fully, partly execute on the user computer, is only as one on the user computer
Vertical software package executes, part executes or on the remote computer completely in remote computer on the user computer for part
Or it is executed on server.In situations involving remote computers, remote computer can pass through network-packet of any kind
It includes LAN (LAN) or wide area network (WAN)-is connected to subscriber computer, or, it may be connected to outer computer (such as profit
It is connected by internet with ISP).In some embodiments, by using computer-readable program instructions
Status information carry out personalized customization electronic circuit, such as programmable logic circuit, field programmable gate array (FPGA) or can
Programmed logic array (PLA) (PLA), the electronic circuit can execute computer-readable program instructions, to realize each side of the disclosure
Face.
Referring herein to according to the flow chart of the method, apparatus (system) of the embodiment of the present disclosure and computer program product and/
Or block diagram describes various aspects of the disclosure.It should be appreciated that flowchart and or block diagram each box and flow chart and/
Or in block diagram each box combination, can be realized by computer-readable program instructions.
These computer-readable program instructions can be supplied to all-purpose computer, special purpose computer or other programmable datas
The processor of processing unit, to produce a kind of machine so that these instructions are passing through computer or other programmable datas
When the processor of processing unit executes, work(specified in one or more of implementation flow chart and/or block diagram box is produced
The device of energy/action.These computer-readable program instructions can also be stored in a computer-readable storage medium, these refer to
It enables so that computer, programmable data processing unit and/or other equipment work in a specific way, to be stored with instruction
Computer-readable medium includes then a manufacture comprising in one or more of implementation flow chart and/or block diagram box
The instruction of the various aspects of defined function action.
Computer-readable program instructions can also be loaded into computer, other programmable data processing units or other
In equipment so that series of operation steps are executed on computer, other programmable data processing units or miscellaneous equipment, with production
Raw computer implemented process, so that executed on computer, other programmable data processing units or miscellaneous equipment
Instruct function action specified in one or more of implementation flow chart and/or block diagram box.
Flow chart and block diagram in attached drawing show the system, method and computer journey of multiple embodiments according to the disclosure
The architecture, function and operation in the cards of sequence product.In this regard, each box in flowchart or block diagram can generation
One module of table, program segment or a part for instruction, the module, program segment or a part for instruction include one or more use
The executable instruction of the logic function as defined in realization.In some implementations as replacements, the function of being marked in box
It can occur in a different order than that indicated in the drawings.For example, two continuous boxes can essentially be held substantially in parallel
Row, they can also be executed in the opposite order sometimes, this is depended on the functions involved.It is also noted that block diagram and/or
The combination of each box in flow chart and the box in block diagram and or flow chart can use function or dynamic as defined in executing
The dedicated hardware based system made is realized, or can be realized using a combination of dedicated hardware and computer instructions.
The presently disclosed embodiments is described above, above description is exemplary, and non-exclusive, and
It is not limited to disclosed each embodiment.Without departing from the scope and spirit of illustrated each embodiment, for this skill
Many modifications and changes will be apparent from for the those of ordinary skill in art field.The selection of term used herein, purport
In the principle, practical application or technological improvement to the technology in market for best explaining each embodiment, or this technology is made to lead
Other those of ordinary skill in domain can understand each embodiment disclosed herein.
Claims (10)
1. a kind of phase-locked loop frequency integrator, which is characterized in that including：
Control code generation module is configured to default correspondence, generates the first control corresponding with the first signal received
Code processed, the default correspondence include signal frequency and control code correspondence；
Phaselocked loop is configured to the lock operation that first control code executes the frequency of signal so that after lock operation
The frequency of the second signal of output is identical as the frequency of the first signal；
Wherein, the phaselocked loop includes voltage controlled oscillator, and in the control code generation module and the voltage controlled oscillator
Switched capacitor array connects, to adjust the capacitor value of the switched capacitor array by first control code.
2. phase-locked loop frequency integrator according to claim 1, which is characterized in that the phaselocked loop further includes：
Phase frequency detector is configured to obtain the difference of the first parameter between first signal and the third signal of feedback,
First parameter includes frequency and phase；
Adjustment module is connect with the control code generation module and the phase frequency detector respectively, and based on the difference and
First control code adjusts the frequency of oscillation of the voltage controlled oscillator in it, to export fourth signal；
Frequency divider is configured to obtain the third signal to fourth signal progress scaling down processing, and the third is believed
Number the phase frequency detector is fed back to,
Wherein, the second signal is the difference when being steady state value, the signal based on adjustment module output.
3. phase-locked loop frequency integrator according to claim 2, which is characterized in that the adjustment module includes：
Charge pump is configured to the difference and generates corresponding current controling signal；
Loop filter is configured to be filtered current controling signal execution, and the signal after being filtered is turned
It is changed to voltage control signal；
Voltage controlled oscillator adjusts its frequency of oscillation based on the voltage control signal and first control code, and exports institute
State fourth signal.
4. the phase-locked loop frequency integrator described in claim 2, which is characterized in that the adjustment module includes：
Charge pump is configured to the difference and generates corresponding current controling signal；
Loop filter is configured to be filtered current controling signal execution, and the signal after being filtered is turned
It is changed to voltage control signal；
Voltage controlled oscillator adjusts its frequency of oscillation based on the voltage control signal and first control code, and exports the
Five signals；
Two-divider is configured to carry out scaling down processing to the 5th signal, the fourth signal is obtained, wherein the described 4th
The frequency of signal is the half of the frequency of the 5th signal.
5. phase-locked loop frequency integrator according to claim 3 or 4, which is characterized in that the voltage controlled oscillator is further
It is configured to adjust the capacitor value of the tunable capacitor in it by the voltage control signal, to adjust its frequency of oscillation.
6. phase-locked loop frequency integrator according to claim 1, which is characterized in that further include：
Reference clock module is connect with the control code generation module and the phaselocked loop respectively, and exports first letter
Number.
7. phase-locked loop frequency integrator according to claim 1, which is characterized in that the control code generation module includes：
Processing module is configured to transmit the second different control codes to the phaselocked loop, and obtains phaselocked loop and execute locking behaviour
The frequency of the output signal exported after work, and the frequency based on second control code and corresponding output signal establish it is described pre-
If correspondence.
8. a kind of control method for frequency, which is characterized in that including：
Based on default correspondence, the first control code corresponding with the first signal received is generated using control code generation module,
The default correspondence includes signal frequency and control code correspondence；
The lock operation of the frequency of signal is executed based on first control code by phaselocked loop so that exported after lock operation
The frequency of second signal is identical as the frequency of the first signal；
Wherein, the phaselocked loop includes voltage controlled oscillator, and in the control code generation module and the voltage controlled oscillator
Switched capacitor array connects, to adjust the capacitor value of the switched capacitor array by first control code.
9. according to the method described in claim 8, it is characterized in that, described executed by phaselocked loop based on first control code
The lock operation of the frequency of signal includes：
The difference of the first parameter between first signal and the third signal of feedback is obtained, first parameter includes phase
And frequency；
Frequency of oscillation is adjusted based on the difference and the control code, to export fourth signal；
Scaling down processing is carried out to the fourth signal and obtains the third signal, and the third signal is fed back into phaselocked loop
Input side.
10. according to the method described in claim 8, it is characterized in that, further including：
The second different control codes is transmitted to the phaselocked loop；
After phaselocked loop executes lock operation, the frequency of the output signal of its output is obtained；
Frequency based on second control code and corresponding output signal establishes the default correspondence.
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