CN108808445A - A kind of shared VCSEL and HBT integrated morphologies and production method - Google Patents
A kind of shared VCSEL and HBT integrated morphologies and production method Download PDFInfo
- Publication number
- CN108808445A CN108808445A CN201810713719.8A CN201810713719A CN108808445A CN 108808445 A CN108808445 A CN 108808445A CN 201810713719 A CN201810713719 A CN 201810713719A CN 108808445 A CN108808445 A CN 108808445A
- Authority
- CN
- China
- Prior art keywords
- gaas
- shaped
- vcsel
- algaas
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/06—Arrangements for controlling the laser output parameters, e.g. by operating on the active medium
- H01S5/062—Arrangements for controlling the laser output parameters, e.g. by operating on the active medium by varying the potential of the electrodes
- H01S5/06203—Transistor-type lasers
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Lasers (AREA)
Abstract
A kind of shared VCSEL and HBT integrated morphologies and production method, belong to compound semiconductor materials and device arts.VCSEL and HBT shares N-shaped InGaP emitter region, the base areas p-type GaAs and N-shaped GaAs collecting zones in the structure, and VCSEL is connected in vertical direction formation with HBT to reduce chip area.It is etched to N-shaped InGaP corrosion barrier layers using wet etching, it recycles wet oxidation to form annular oxidation to limit to provide electric current and light field, it is sequentially etched N-shaped InGaP corrosion barrier layers, N-shaped GaAs collecting zones and the base areas p-type GaAs again, successively base electrode and emitter electrode are made in the base areas p-type GaAs and N-shaped InGaP emitter region, it recycles BCB to fill etching groove, then makes the faces VCSEL p electrode.VCSEL connects in vertical direction formation with HBT and reduces chip area.
Description
Technical field
The invention belongs to compound semiconductor materials and device arts, specifically design a kind of vertical cavity surface-emitting laser
The structure of device (VCSEL) and Heterojunction Bipolar Transistors (HBT).
Background technology
VCSEL is a kind of emergent light perpendicular to the semiconductor laser of substrate surface, is had the following advantages：Circular light spot
It is easy to fiber coupling；Threshold current is small, and low energy consumption；Chamber length can realize single longitudinal mode operation；With higher relaxation oscillation frequency
It can obtain larger modulation bandwidth；Testing cost can be saved with On-wafer measurement.Main devices of the HBT as laser modulation circuit
One of part has many advantages, such as that power density is high, current gain is big, phase noise is low and the linearity is good.Typically by VCSEL and drive
Dynamic circuit separates, and this considerably increases costs.It is in Unexamined Publication patent application 104752952, VCSEL is simple with HBT
It is integrated VCSEL and HBT form parallel-connection structure on the same substrate, be unfavorable for reducing chip area cost.Therefore by VCSEL
With HBT shared structures, and VCSEL and HBT connect in vertical direction formation can reduce chip area, reduce cost.In U.S.'s public affairs
It opens and provides a kind of HBT and VCSEL integrated morphologies in patent application 1993/5216686, but due to no InGaP corrosion barrier layers,
Therefore etching depth is difficult control, and yield rate is relatively low；And non-oxidation limiting layer, good electric current and light field limitation cannot be provided.
Invention content
The purpose of the present invention is to provide a kind of shared VCSEL and HBT integrated morphologies and production method, reduce and integrate core
Piece area improves yield rate, reduces cost.
The present invention is in order to achieve the above object, the technical solution used is as follows：
A kind of sharing VCSEL and HBT integrated morphologies, it is characterised in that：VCSEL and HBT has shared N-shaped InGaP and emits
Area, the base areas p-type GaAs and N-shaped GaAs collecting zones, structure are followed successively by p-type GaAs cap layers, p-type AlGaAs/ from top to bottom
AlGaAs upper DBR, Al0.98Ga0.02As oxide layers and AlxOyComposite layer, InGaAs/AlGaAs Quantum Well, upper and lower limiting layer, N-shaped
The cylindrical structure of InGaP corrosion barrier layers, N-shaped GaAs collecting zones composition, Al0.98Ga0.02As oxide layers and AlxOyComposite layer：
Al0.98Ga0.02As oxide layers are circle center, AlxOyIn Al0.98Ga0.02As oxide layer outer shrouds；The lower layer of N-shaped GaAs collecting zones according to
It is secondary that the side of the base areas p-type GaAs is longer than N-shaped GaAs collecting zones for the base areas p-type GaAs, N-shaped InGaP emitter region, thereon for
Base electrode；The side of N-shaped InGaP emitter region is longer than the base areas p-type GaAs, there is emitter electrode thereon；N-shaped InGaP hairs
The downward lower layer for penetrating area is followed successively by DBR under unintentional doping AlGaAs/AlAs, unintentional doping GaAs buffer layers, semi-insulating
GaAs substrates；The upper surface of DBR fills material other than N-shaped InGaP emitter region for planarization under unintentional doping AlGaAs/AlAs
Expect BCB, planarizing fill material BCB upwards the upper surface of flushed with p-type GaAs cap layers；Upward in planarizing fill material BCB
Above with the faces p electrode is equipped in p-type GaAs cap layers.
In said program, the unintentional doping GaAs buffer layers be used to inhibit dislocation in half-insulating GaAs substrate to
Extend in epitaxial layer, thickness is preferably 1000nm.
In said program, DBR under the unintentional doping AlGaAs/AlAs, by 30.5 couples of λ0/ 4 optical thicknesses
Al0.12Ga0.88As/AlAs is constituted, and overall thickness is preferably 3988nm, doping concentration 2e18cm-3。
In said program, the N-shaped InGaP emitter region thickness is preferably 196nm, doping concentration 2e18cm-3。
In said program, the base areas the p-type GaAs thickness is preferably 59nm, doping concentration 1e19cm-3。
In said program, the N-shaped GaAs collecting zone thickness is preferably 118nm, doping concentration 1e18cm-3。
In said program, the N-shaped InGaP corrosion barrier layers, InGaP has different corrosion rates from GaAs,
Play the role of selective corrosion.The thickness on the barrier layer is preferably 65nm, doping concentration 2e18cm-3。
In said program, the limiting layer up and down is by Al0.60Ga0.40As materials are constituted, and thickness is preferably 110nm.
In said program, the InGaAs/AlGaAs Quantum Well photoluminescence wavelength ratio λ0Small 10-20nm, including 4 couples
In0.10Ga0.90As/Al0.37Ga0.63As materials, thickness are preferably 45nm.
In said program, the Al0.98Ga0.02As oxide layers, it is characterised in that：Oxide layer is through wet process oxidation technology oxygen
After change, electric current and light field restriction effect are played, oxidated layer thickness is preferably 30nm.
In said program, DBR is by 22.5 couples of λ on the p-type AlGaAs/AlGaAs0/ 4 optical thicknesses
Al0.12Ga0.88As/Al0.90Ga0.10As is constituted, and overall thickness is preferably 2942nm, doping concentration 2e18cm-3。
In said program, the GaAs cap layers thickness is preferably 50nm, doping concentration 1e20cm-3。
The specific preparation process of shared VCSEL and HBT integrated morphologies described above includes following：
(1) the MOCVD unintentional doping GaAs buffer layers of extension, unintentional doping successively is utilized on half-insulating GaAs substrate
DBR under AlGaAs/AlAs, N-shaped InGaP emitter region, the base areas p-type GaAs, N-shaped GaAs collecting zones, N-shaped InGaP corrosion barrier layers,
Lower limit layer, InGaAs/AlGaAs Quantum Well, upper limiting layer, Al0.98Ga0.02DBR in As oxide layers, p-type AlGaAs/AlGaAs
With p-type GaAs cap layers；
(2) N-shaped InGaP corrosion barrier layers are etched to using wet etching；Recycle wet oxidation formed annular oxidation with
Electric current and light field limitation are provided；
(3) it is sequentially etched N-shaped InGaP corrosion barrier layers, N-shaped GaAs collecting zones and the base areas p-type GaAs again；Successively in p-type
The base areas GaAs and N-shaped InGaP emitter region make base electrode and emitter electrode；
(4) it recycles BCB to fill etching groove, makes the faces VCSEL p electrode.
The present invention beneficial outcomes be：
It can be seen from the above technical proposal that shared VCSEL provided by the invention and HBT integrated morphologies, are conventional
VCSEL and HBT has shared N-shaped InGaP emitter region, the base areas p-type GaAs and N-shaped GaAs collecting zones, and VCSEL and HBT is in vertical side
Chip area is reduced to series connection is formed；InGaP corrosion barrier layers play the role of selective corrosion, reduce etching technics
Difficulty improves yield rate.
Description of the drawings
The above-mentioned and/or additional aspect and advantage of the present invention will become in the description from combination following accompanying drawings to embodiment
Obviously and it is readily appreciated that, wherein：
Fig. 1 is the structural schematic diagram of the shared VCSEL and HBT devices of the embodiment of the present invention.
Fig. 2 is the epitaxial structure schematic diagram of the embodiment of the present invention.
Fig. 3 is structural schematic diagram of the embodiment through primary etching and wet oxidation.
Fig. 4 is the structural schematic diagram that etched embodiment, vapor deposition and sputtering make base electrode and emitter electrode thickness.
DBR under half-insulating GaAs substrate 101, unintentional doping GaAs buffer layers 102, unintentional doping AlGaAs/AlAs
103, N-shaped InGaP emitter region 104, the base areas p-type GaAs 105, N-shaped GaAs collecting zones 106, N-shaped InGaP corrosion barrier layers 107,
Upper and lower limiting layer 108, InGaAs/AlGaAs Quantum Well 109, Al0.98Ga0.02In As oxide layers 110, p-type AlGaAs/AlGaAs
DBR 111, p-type GaAs cap layers 112, AlxOy201, planarizing fill material BCB 301, base electrode 401, emitter electrode
The faces 402 and p electrode 403.
Specific implementation mode
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, and is only used for explaining the present invention, and is not considered as limiting the invention.
A kind of shared VCSEL and HBT structure provided according to embodiments of the present invention below with reference to Fig. 1 descriptions.It includes：
DBR 103, N-shaped under half-insulating GaAs substrate 101, unintentional doping GaAs buffer layers 102, unintentional doping AlGaAs/AlAs
InGaP emitter region 104, the base areas p-type GaAs 105, N-shaped GaAs collecting zones 106, N-shaped InGaP corrosion barrier layers 107, up and down limitation
Layer 108, InGaAs/AlGaAs Quantum Well 109, Al0.98Ga0.02DBR 111, p in As oxide layers 110, p-type AlGaAs/AlGaAs
Type GaAs cap layers 112, AlxOy201, planarizing fill material BCB 301, base electrode 401, emitter electrode 402 and the faces p electricity
Pole 403.
The present invention also provides a kind of methods making shared VCSEL and HBT, include the following steps：
Step 1：As shown in Fig. 2, half-insulating GaAs substrate is positioned in MOCVD boards, successively each epitaxial layer.Exist first
H in 600 DEG C -800 DEG C2The above-mentioned epitaxial wafer surface 20min~40min of high-temperature cleaning in atmosphere, and it is passed through AsH3, remove surface
Water.TMGa and AsH are passed through into MOCVD3, grow GaAs buffer layers；Thickness is 1000nm.TMGa, TMAl are passed through into MOCVD
And AsH3, grow lower DBR, thickness 3988nm, doping concentration 2e18cm-3；It is passed through TMIn, TMGa, PH3And Si2H4, growth hair
Penetrate area, thickness 196nm, doping concentration 2e18cm-3；It is passed through TMGa, AsH3And CBr4, growth emitter region, thickness 59nm,
Doping concentration is 1e19cm-3；It is passed through TMIn, TMGa, PH3And Si2H6, grow corrosion barrier layer, thickness 65nm, doping concentration
For 1e18cm-3；It is passed through TMGa, TMAl and AsH3, grow lower limit layer, thickness 110nm；Be passed through TMIn, TMGa, TMAl and
AsH3, grown quantum trap, thickness 45nm, photoluminescence wavelength ratio λ0Small 10-20nm, wherein λ0For excitation wavelength；It is passed through
TMGa, TMAl and AsH3, grow upper limiting layer, thickness 110nm；It is passed through TMGa, TMAl, AsH3And CBr4, grow lower oxidation
Layer, thickness 30nm, doping concentration 2e18cm-3；It is passed through TMGa, TMAl, AsH3And CBr4, DBR in growth, thickness is
2942nm, doping concentration 2e18cm-3；It is passed through TMGa, AsH3And CBr4, cap layers, thickness 30nm are grown, doping concentration is
1e20cm-3。
Step 2：Through photoetching and wet etching, epitaxial layer is etched to InGaP corrosion barrier layers, forms the first table top, platform
A diameter of 20-30 μm of face.Epitaxial wafer is placed in oxidation furnace, N is passed through2And H2O, the temperature inside oxidation furnace are 400 DEG C -450
DEG C, oxide layer aoxidizes inwards from side, forms the Al of insulationxOy, the size of oxide-aperture is 5 μm -8 μm, as shown in Figure 3.
Step 3：Through photoetching and wet etching, it is etched to collecting zone, recycles ICP to be etched to base area, utilizes magnetron sputtering
Make base electrode；It recycles wet etching to be etched to emitter, makes emitter electrode using electron beam evaporation technique, such as scheme
Shown in 4.
Step 4：It is coated using non-photosensitivity BCB materials, is then cured in anaerobic baking oven, utilize SiO2It carries out
Mask etches BCB figures using ICP, then etches BCB again until base electrode and emitter electrode；Utilize magnetron sputtering system
Make the faces p electrode, as shown in Figure 1.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " illustrative examples ",
The description of " example ", " specific example " or " some examples " etc. means specific features described in conjunction with this embodiment or example, knot
Structure, material or feature are included at least one embodiment or example of the invention.In the present specification, to above-mentioned term
Schematic representation may not refer to the same embodiment or example.Moreover, specific features, structure, material or the spy of description
Point can be combined in any suitable manner in any one or more of the embodiments or examples.
Although an embodiment of the present invention has been shown and described, it will be understood by those skilled in the art that：Not
In the case of being detached from the principle of the present invention and objective a variety of change, modification, replacement and modification can be carried out to these embodiments, this
The range of invention is limited by claim and its equivalent.
Claims (10)
1. a kind of sharing VCSEL and HBT integrated morphologies, it is characterised in that：VCSEL and HBT have shared N-shaped InGaP emitter region,
The base areas p-type GaAs and N-shaped GaAs collecting zones, structure are followed successively by p-type GaAs cap layers, on p-type AlGaAs/AlGaAs from top to bottom
DBR、Al0.98Ga0.02As oxide layers and AlxOyComposite layer, InGaAs/AlGaAs Quantum Well, upper and lower limiting layer, N-shaped InGaP are rotten
Lose barrier layer, the cylindrical structure that N-shaped GaAs collecting zones form, Al0.98Ga0.02As oxide layers and AlxOyComposite layer：
Al0.98Ga0.02As oxide layers are circle center, AlxOyIn Al0.98Ga0.02As oxide layer outer shrouds；The lower layer of N-shaped GaAs collecting zones according to
It is secondary that the side of the base areas p-type GaAs is longer than N-shaped GaAs collecting zones for the base areas p-type GaAs, N-shaped InGaP emitter region, thereon for
Base electrode；The side of N-shaped InGaP emitter region is longer than the base areas p-type GaAs, there is emitter electrode thereon；N-shaped InGaP hairs
The downward lower layer for penetrating area is followed successively by DBR under unintentional doping AlGaAs/AlAs, unintentional doping GaAs buffer layers, semi-insulating
GaAs substrates；The upper surface of DBR fills material other than N-shaped InGaP emitter region for planarization under unintentional doping AlGaAs/AlAs
Expect BCB, planarizing fill material BCB upwards the upper surface of flushed with p-type GaAs cap layers；Upward in planarizing fill material BCB
Above with the faces p electrode is equipped in p-type GaAs cap layers.
2. a kind of sharing VCSEL described in accordance with the claim 1 and HBT integrated morphologies, it is characterised in that：Described is unintentional
Doping GaAs buffer layers are used to inhibit to extend in the dislocation epitaxial layers in half-insulating GaAs substrate, and thickness is preferably 1000nm.
3. a kind of sharing VCSEL described in accordance with the claim 1 and HBT integrated morphologies, it is characterised in that：Described is unintentional
DBR under AlGaAs/AlAs is adulterated, by 30.5 couples of λ0The Al of/4 optical thicknesses0.12Ga0.88As/AlAs is constituted, and overall thickness is preferably
3988nm, doping concentration 2e18cm-3。
4. a kind of sharing VCSEL described in accordance with the claim 1 and HBT integrated morphologies, it is characterised in that：The N-shaped
InGaP emitter region thickness is preferably 196nm, doping concentration 2e18cm-3；The base areas the p-type GaAs thickness is preferably 59nm,
Doping concentration is 1e19cm-3。
5. a kind of sharing VCSEL described in accordance with the claim 1 and HBT integrated morphologies, it is characterised in that：The N-shaped
GaAs collecting zone thickness is preferably 118nm, doping concentration 1e18cm-3。
6. a kind of sharing VCSEL described in accordance with the claim 1 and HBT integrated morphologies, it is characterised in that：The N-shaped
InGaP corrosion barrier layers, InGaP have different corrosion rates from GaAs, play the role of selective corrosion；The barrier layer
Thickness be preferably 65nm, doping concentration 2e18cm-3。
7. a kind of sharing VCSEL described in accordance with the claim 1 and HBT integrated morphologies, it is characterised in that：The bound
Preparative layer is by Al0.60Ga0.40As materials are constituted, and thickness is preferably 110nm.
8. a kind of sharing VCSEL described in accordance with the claim 1 and HBT integrated morphologies, it is characterised in that：Described
InGaAs/AlGaAs Quantum Well photoluminescence wavelength ratio λ0Small 10-20nm, including 4 couples of In0.10Ga0.90As/Al0.37Ga0.63As materials
Material, thickness is preferably 45nm.
9. a kind of sharing VCSEL described in accordance with the claim 1 and HBT integrated morphologies, it is characterised in that：Described
Al0.98Ga0.02As oxide layers, oxide layer play electric current and light field restriction effect after wet process oxidation technology aoxidizes, aoxidize thickness
Degree is preferably 30nm；DBR is by 22.5 couples of λ on the p-type AlGaAs/AlGaAs0/ 4 optical thickness Al0.12Ga0.88As/
Al0.90Ga0.10As is constituted, and overall thickness is preferably 2942nm, doping concentration 2e18cm-3；The GaAs cap layers thickness is preferably
50nm, doping concentration 1e20cm-3。
10. claim 1-9 any one of them sharing VCSEL obtain preparation method with HBT integrated morphologies, which is characterized in that
Specific preparation process includes following：
(1) the MOCVD unintentional doping GaAs buffer layers of extension, unintentional doping successively is utilized on half-insulating GaAs substrate
DBR under AlGaAs/AlAs, N-shaped InGaP emitter region, the base areas p-type GaAs, N-shaped GaAs collecting zones, N-shaped InGaP corrosion barrier layers,
Lower limit layer, InGaAs/AlGaAs Quantum Well, upper limiting layer, Al0.98Ga0.02DBR in As oxide layers, p-type AlGaAs/AlGaAs
With p-type GaAs cap layers；
(2) N-shaped InGaP corrosion barrier layers are etched to using wet etching；Wet oxidation is recycled to form annular oxidation to provide
Electric current and light field limitation；
(3) it is sequentially etched N-shaped InGaP corrosion barrier layers, N-shaped GaAs collecting zones and the base areas p-type GaAs again；Successively in p-type GaAs
Base area and N-shaped InGaP emitter region make base electrode and emitter electrode；
(4) it recycles BCB to fill etching groove, makes the faces VCSEL p electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810713719.8A CN108808445A (en) | 2018-07-03 | 2018-07-03 | A kind of shared VCSEL and HBT integrated morphologies and production method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810713719.8A CN108808445A (en) | 2018-07-03 | 2018-07-03 | A kind of shared VCSEL and HBT integrated morphologies and production method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108808445A true CN108808445A (en) | 2018-11-13 |
Family
ID=64074028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810713719.8A Pending CN108808445A (en) | 2018-07-03 | 2018-07-03 | A kind of shared VCSEL and HBT integrated morphologies and production method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108808445A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108736316A (en) * | 2018-06-08 | 2018-11-02 | 北京嘉圣光通科技有限公司 | Make the method and vertical cavity surface emitting laser of vertical cavity surface emitting laser |
| CN111162451A (en) * | 2019-12-26 | 2020-05-15 | 浙江博升光电科技有限公司 | Bottom emitting vertical cavity surface emitting laser |
| CN111628022A (en) * | 2019-02-28 | 2020-09-04 | 中国科学院物理研究所 | GaAs-based photoelectric device and preparation method of array thereof |
| CN112563378A (en) * | 2020-12-11 | 2021-03-26 | 西安立芯光电科技有限公司 | Manufacturing method of oxidation intensifying diode |
| CN117594644A (en) * | 2024-01-18 | 2024-02-23 | 常州承芯半导体有限公司 | Semiconductor device and method of forming the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104319626A (en) * | 2014-10-11 | 2015-01-28 | 北京工业大学 | Microwave carrier directly modulated vertical-cavity surface-emitting laser |
| CN104752952A (en) * | 2015-03-11 | 2015-07-01 | 北京工业大学 | GaAs-based HBT and vertical-cavity surface emitting laser |
| CN105070751A (en) * | 2015-08-18 | 2015-11-18 | 成都嘉石科技有限公司 | Gaas hbt device |
| CN208767611U (en) * | 2018-07-03 | 2019-04-19 | 北京工业大学 | A kind of shared VCSEL and HBT integrated morphology |
-
2018
- 2018-07-03 CN CN201810713719.8A patent/CN108808445A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104319626A (en) * | 2014-10-11 | 2015-01-28 | 北京工业大学 | Microwave carrier directly modulated vertical-cavity surface-emitting laser |
| CN104752952A (en) * | 2015-03-11 | 2015-07-01 | 北京工业大学 | GaAs-based HBT and vertical-cavity surface emitting laser |
| CN105070751A (en) * | 2015-08-18 | 2015-11-18 | 成都嘉石科技有限公司 | Gaas hbt device |
| CN208767611U (en) * | 2018-07-03 | 2019-04-19 | 北京工业大学 | A kind of shared VCSEL and HBT integrated morphology |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108736316A (en) * | 2018-06-08 | 2018-11-02 | 北京嘉圣光通科技有限公司 | Make the method and vertical cavity surface emitting laser of vertical cavity surface emitting laser |
| CN111628022A (en) * | 2019-02-28 | 2020-09-04 | 中国科学院物理研究所 | GaAs-based photoelectric device and preparation method of array thereof |
| CN111628022B (en) * | 2019-02-28 | 2022-07-15 | 中国科学院物理研究所 | GaAs-based photoelectric device and preparation method of array thereof |
| CN111162451A (en) * | 2019-12-26 | 2020-05-15 | 浙江博升光电科技有限公司 | Bottom emitting vertical cavity surface emitting laser |
| CN112563378A (en) * | 2020-12-11 | 2021-03-26 | 西安立芯光电科技有限公司 | Manufacturing method of oxidation intensifying diode |
| CN112563378B (en) * | 2020-12-11 | 2022-02-25 | 西安立芯光电科技有限公司 | Manufacturing method of oxidation intensifying diode |
| CN117594644A (en) * | 2024-01-18 | 2024-02-23 | 常州承芯半导体有限公司 | Semiconductor device and method of forming the same |
| CN117594644B (en) * | 2024-01-18 | 2024-05-28 | 常州承芯半导体有限公司 | Semiconductor device and method of forming the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108808445A (en) | A kind of shared VCSEL and HBT integrated morphologies and production method | |
| US7732237B2 (en) | Quantum dot based optoelectronic device and method of making same | |
| CN101667716B (en) | Double-sided bonding long-wavelength vertical cavity surface emitting laser and manufacturing method thereof | |
| JP3540042B2 (en) | Manufacturing method of semiconductor device | |
| US6639927B2 (en) | Surface emitting semiconductor laser, and its fabrication method | |
| JPH05506333A (en) | top emitting diode laser | |
| CN111564756B (en) | Silicon-based non-phosphorus laser and preparation method thereof | |
| KR100397371B1 (en) | Long wavelength vertical-cavity surface emitting laser having oxide-aperture and method for fabricating the same | |
| CN114649742B (en) | Efficient vertical cavity surface EML chip and preparation method thereof | |
| JP2009252839A (en) | Semiconductor laser and manufacturing method therefor | |
| CN208767611U (en) | A kind of shared VCSEL and HBT integrated morphology | |
| WO2003007445A1 (en) | Semiconductor quantum dot⋅device | |
| CN111092366B (en) | Semiconductor laser with double-sided current limiting structure and preparation method | |
| US6920167B2 (en) | Semiconductor laser device and method for fabricating thereof | |
| KR100726324B1 (en) | Oxide aperture long-wavelength vertical cavity surface emitting lasers and method of manufacturing the same | |
| WO2002050968A1 (en) | Surface-emitting laser, method of manufacture thereof, and surface-emitting laser array | |
| CN208272356U (en) | A kind of electric current guided VCSEL | |
| CN108539577A (en) | A kind of electric current guided VCSEL and preparation method thereof | |
| WO2020248509A1 (en) | Electric-injection micro-disk resonant cavity light-emitting device and preparation method therefor | |
| JPS6349396B2 (en) | ||
| JP2566955B2 (en) | Semiconductor laser and manufacturing method thereof | |
| CN118040470A (en) | Multi-junction VCSEL laser, manufacturing method thereof and VCSEL array | |
| CN118040469A (en) | Multi-junction VCSEL laser, manufacturing method thereof and VCSEL array | |
| CN114976864A (en) | High-efficiency vertical cavity surface EML chip with embossment | |
| CN114865452A (en) | Efficient vertical cavity surface EML chip with oxidation isolation layer and preparation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |