CN114976864A

CN114976864A - High-efficiency vertical cavity surface EML chip with embossment

Info

Publication number: CN114976864A
Application number: CN202210544748.2A
Authority: CN
Inventors: 杨奕; 鄢静舟; 李伟; 薛婷; 王坤; 洪斌; 谢福时
Original assignee: Fujian Huixin Laser Technology Co ltd
Current assignee: Fujian Huixin Laser Technology Co ltd
Priority date: 2022-05-19
Filing date: 2022-05-19
Publication date: 2022-08-30

Abstract

A high-efficiency vertical cavity surface EML chip with a relief relates to the technical field of semiconductor photoelectron and comprises a VCSEL unit, an oxidation isolation layer, an EOM unit and the relief, wherein the oxidation isolation layer is arranged between the VCSEL unit and the EOM unit and used for preventing the electric potential at the contact part of the two units from influencing the working current in each unit; the relief is arranged above the EOM unit and used for suppressing a high-order transverse mode so as to realize mode control. The invention breakthroughs an oxidation isolation layer with an electrical insulation effect arranged between the VCSEL unit and the EOM unit to isolate the high-frequency modulation signal applied to the EOM unit, so that the VCSEL unit and the EOM unit are relatively independent, the high-frequency modulation signal is prevented from influencing the current in the VCSEL unit, and the stable output of the VCSEL unit is ensured. The embossment of the invention enables the specular reflectivity of the high-order transverse mode to be relatively reduced, thereby achieving the purpose of inhibiting the high-order transverse mode, ensuring the realization of stable output of the basic transverse mode, optimizing the quality of light beams, reducing the threshold current and the insertion loss, and meeting the single-mode application requirements of the VCSEL chip.

Description

High-efficiency vertical cavity surface EML chip with embossment

Technical Field

The invention relates to the technical field of semiconductor photoelectron, in particular to a high-efficiency vertical cavity surface EML chip with embossment.

Background

With the rapid development of the data communication era, Vertical Cavity Surface Emitting Laser (VCSEL) chips are widely used in the optical communication fields, such as optical interconnection, optical sensing, optical storage, and application scenarios such as data center short-distance communication, 5G base station, HDMI ultra high definition video transmission, etc., due to their excellent characteristics, such as small chip volume, circular light spot output, low working threshold, high coupling efficiency, and convenient integration. The VCSEL chip has good economical efficiency, practicability and reliability, and brings great convenience for information exchange in various industries.

As the amount of data increases, higher requirements are placed on the rate and quality of data transmission. At present, a VCSEL chip mostly adopts a direct modulation working mode to carry out signal transmission, namely, high-speed radio frequency electric signals are adopted for direct modulation. With the increase of the modulation rate, the directly modulated VCSEL chip is prone to generate a Chirp (Chirp) phenomenon during its operation, which may limit the transmission rate of the laser chip, and when the transmission distance increases, transmission Crosstalk (Crosstalk) and optical power attenuation may also be generated, thereby reducing the transmission quality of the signal. If a higher modulation rate is to be achieved, the current density needs to be increased by multiple times without changing the modulation mode, which leads to the problems of increased chip power consumption and shortened lifetime.

Similar to the edge-emitting EML chip, which is a type of edge-emitting laser chip monolithically integrated with a light-emitting unit DFB and a modulation unit, the conventional vertical cavity surface EML is a type of vertical-emitting laser chip monolithically integrated with a light-emitting unit (VCSEL unit) and a modulation unit (EOM unit), and generally has a structure of "NDBR-active region-oxide confinement layer-PDBR-absorption region-NDBR", and the VCSEL unit and the EOM unit respectively achieve optical resonance of the VCSEL unit and enhance light absorption of the EOM unit by sharing the PDBR. However, since there is no electrical isolation between the VCSEL unit and the EOM unit, when a high frequency modulation signal is applied to the EOM unit, the current in the VCSEL unit is affected, thereby affecting the stable output of the VCSEL unit.

In addition, the conventional VCSEL chip is generally a single longitudinal mode, a beam with multiple transverse modes, the number of the transverse modes is usually 3-6, and in the operating state of the multiple transverse modes, mode competition is easily caused by superposition of multiple modes of mixed oscillation, resulting in unstable optical power and spectrum. However, since the stable fundamental transverse mode output can meet the requirements of high-density optical storage and reading, free optical interconnection, data transmission in single-mode optical fiber, and the like, the VCSEL chip is expected to have stable fundamental transverse mode output operating characteristics in many application scenarios.

Based on this, we provide a high-efficiency vertical-cavity surface EML chip with relief.

Disclosure of Invention

The invention provides a high-efficiency vertical cavity surface EML chip with a relief, which mainly aims to solve the problems in the prior art.

The invention adopts the following technical scheme:

the utility model provides a take high-efficient vertical cavity surface EML chip of relief (sculpture), includes VCSEL unit, oxidation isolation layer, EOM unit and relief (sculpture), wherein: the VCSEL unit comprises a substrate, a buffer layer, a first DBR, a resonant cavity and a second DBR from bottom to top; the EOM unit comprises a third DBR, an absorption region and a fourth DBR from bottom to top; the oxidation isolation layer is arranged between the VCSEL unit and the EOM unit and used for preventing the electric potential of the contact position of the two units from influencing the working current in the respective units; the relief is arranged above the EOM unit and used for restraining a high-order transverse mode so as to realize mode control.

The invention breakthroughs an oxidation isolation layer with an electrical insulation effect arranged between the VCSEL unit and the EOM unit to isolate the high-frequency modulation signal applied to the EOM unit, so that the VCSEL unit and the EOM unit are relatively independent, the high-frequency modulation signal is prevented from influencing the current in the VCSEL unit, and the stable output of the VCSEL unit is ensured. Compared with the mode that the VCSEL unit and the EOM unit are in direct contact in the prior art, the electrical isolation can reduce RC delay in the high-frequency signal transmission process, is beneficial to improving transmission performance, and realizes a better modulation effect.

For the VCSEL plus EOM cell design of the present invention, the top fourth DBR absorbs light, especially light with long wavelengths (1310 and 1550 nm), especially greatly, thus causing problems of high threshold current and large insertion loss. According to the invention, the embossment is arranged above the EOM unit, so that the specular reflectivity of the high-order transverse mode is relatively reduced, the purpose of inhibiting the high-order transverse mode is achieved, the stable output of the basic transverse mode is ensured, the beam quality is optimized, the threshold current and the insertion loss are reduced, and the single-mode application requirements of the VCSEL chip are met.

The embossment is of an annular structure with a hollow middle part, and in specific application, the annular structure can be designed to be a circular ring or a square ring. During manufacturing, the fourth DBR surface is formed into a relief by dry etching or wet etching. The relief is made of polymer material, medium material or semiconductor material, wherein the polymer material can be PI or BCB and the like; the dielectric material can be selected from silicon nitride, silicon oxide or aluminum oxide; the semiconductor material may be GaAs or AlGaAs. The design can be selected according to actual requirements in application, and is not limited herein.

The substrate is made of GaAs, and the thickness of the oxidation isolation layer is 5-5000nm, and the thickness of the oxidation isolation layer can be designed by referring to the thickness of an oxidation limiting layer of a traditional VCSEL structure in specific application. The GaAs material system has higher reliability, and when the resonant cavity of the VCSEL unit and the absorption region of the EOM unit both adopt the GaAs material system, the physical properties of the materials of the two units are similar, so that the stability of epitaxial deposition of a chip can be greatly improved, and the difficulty of mass production is reduced.

The GaAs-based material system, and the material of the oxidation isolation layer is Al ₂ O ₃ Which is made of Al _x Ga _1-x The As prefabricated layer is formed by oxidation through a wet oxidation process, wherein x is more than or equal to 0.97. Al (Al) ₂ O ₃ Has good electrical insulation effect and is an ideal material for oxidizing the isolation layer. The material of the oxidation isolation prefabricated layer is AlGaAs material, which is matched with the crystal lattice of the GaAs substrate system, thus realizing continuous epitaxial growth, reducing the difficulty of epitaxial production and being beneficial to mass production. Meanwhile, the epitaxial crystal quality of the VCSEL unit and the EOM unit is ensured, and the reliability of the device is improved.

The first DBR, the second DBR, the third DBR and the fourth DBR are made of Al _i Ga _1-i As/Al _j Ga _1-j The As material has a periodic structure, and i and j are not more than 0.92. Because the oxidation isolation prefabricated layer adopts Al with higher aluminum content _x Ga _1-x The As material, on the one hand, in order to prevent the first DBR, the second DBR, the third DBR and the fourth DBR from being excessively oxidized, and on the other hand, since the device resistance is larger due to the larger aluminum content, it should be ensured that the aluminum content of the material constituting the first DBR, the second DBR, the third DBR and the fourth DBR is not more than 92%. In addition, care should be taken in applications to avoid the use of aluminum arsenide materials.

The resonant cavity is of a sandwich structure of a lower waveguide, an active region and an upper waveguide, optical and electrical limitation is carried out by adopting a buried tunnel junction, and the cavity length of the resonant cavity is integral multiple of the half-lasing wavelength. The gain structure of the quantum well of the resonant cavity can be a single quantum well, a multiple quantum well, a tunnel junction cascade quantum well or a quantum dot, and the quantum well can be one of InGaAs/GaAs, InGaAs/AlGaAs, InGaAs/GaAsP, GaAs/AlGaAs, AlInGaAs/AlGaAs, InGaAsP/AlGaAs and AlGaInP/GaAs.

With the quantum well of the resonant cavity, the quantum well material of the absorption region can also be one of InGaAs/GaAs, InGaAs/AlGaAs, InGaAs/GaAsP, GaAs/AlGaAs, AlInGaAs/AlGaAs, InGaAsP/AlGaAs and AlGaInP/GaAs, but in order to realize modulation, the wavelength of the quantum well of the absorption region should be controlled to be 5-99nm shorter than that of the quantum well of the resonant cavity.

The absorption region is of a single quantum well or multiple quantum well structure. When the absorption region is of a single quantum well structure, a third waveguide layer is arranged between the absorption region and the third DBR, and a fourth waveguide layer is arranged between the absorption region and the fourth DBR. This is due to the fact that the single quantum well structure requires the formation of the FP cavity as the VCSEL unit, but the FP cavity in the absorption region is a passive F-P to enhance absorption, rather than an active F-P as in the VCSEL unit.

When the absorption region adopts a pair of quantum well structures, the EOM unit realizes the modulation of the light intensity of the VCSEL unit based on Quantum Confinement Stark Effect (QCSE). By modulating the bias voltage of the EOM unit, the movement of the absorption sideband of the absorption region is directly realized, and the high-speed modulation of the output light intensity of the VCSEL is indirectly realized. Compared with the traditional direct modulation mode, the high-efficiency modulation using the EOM modulation unit can reduce the design limitation of the VCSEL unit, thereby being beneficial to improving the photoelectric conversion efficiency and optimizing the structural design of the VCSEL unit.

When the absorption region adopts a multi-pair quantum well structure, the EOM unit realizes the modulation of the light intensity of the VCSEL unit based on the reflectivity deviation of the top reflector and the bottom reflector. The bias voltage of the EOM unit is modulated, so that the absorption state of the absorption region is directly influenced, the integral reflectivity of the top reflector is further controlled, and the high-speed modulation of the output light intensity of the VCSEL is indirectly realized.

With respect to the specific structure of the resonant cavity, the present invention provides the following two specific embodiments for selection:

as a first embodiment: the resonant cavity comprises a first limiting layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second limiting layer, a P-type limiting layer and a buried tunnel junction from bottom to top; the first DBR is a first N-type doped DBR; the second DBR is a second N-type doped DBR; the third DBR is a third N-type doped DBR; the fourth DBR is a P-type doped DBR.

The reason why the buried tunnel junction is provided is that: firstly, because the PDBR has higher free carrier absorption and resistance, the problems of increasing light absorption loss and heat loss and reducing the electrical conversion efficiency of the VCSEL unit exist, and the VCSEL unit of the invention adopts a buried tunnel junction to reverse the polarity of the PDBR, thereby avoiding the light absorption loss and heat loss increased by the higher free carrier absorption and resistance brought by setting the PDBR and being beneficial to improving the light extraction efficiency of the VCSEL unit; secondly, in the process technology, in the oxidation process of the oxidation limiting layer, point-like defects and dislocations are generated on the interface of the oxidation limiting layer and the semiconductor, and the thermal expansion coefficients of the oxidation limiting layer and the semiconductor are different, so that the oxidation process is usually very difficult to control, the process window is ultra-narrow, and the interface of the oxidation limiting layer and the semiconductor is easy to crack or peel off after the oxidation process. The buried tunnel junction replaces an oxidation limiting layer of a VCSEL unit in the prior art to realize electrical and optical limitation, the problem of yield loss of the traditional oxidation limiting VCSEL in a key process of wet oxidation can be avoided, the production difficulty can be reduced, the production process is simplified, the uniformity of the buried tunnel junction prepared by adopting a photoetching process is good, and the yield is greatly improved.

Specifically, the buried tunnel junction comprises a P-type heavily doped layer and an N-type heavily doped layer from bottom to top, and the aperture of the buried tunnel junction is 2-100 μm. Specifically, the material of the P-type heavily doped layer is GaInP, GaAs or AlGaAs, and the material of the N-type heavily doped layer is GaInP, GaAs or AlGaAs; the thickness range of the P-type heavily doped layer is 8-50 nm, and the thickness range of the N-type heavily doped layer is 10-50 nm; the doping atoms of the P-type heavily doped layer can Be C, Mg, Zn or Be, and the doping atoms of the N-type heavily doped layer can Be Te or Se; the doping concentration of the P-type heavily doped layer and the N-type heavily doped layer is 10 ¹⁹ -10 ²⁰ cm ^-3 Orders of magnitude.

The epitaxial structure of the invention adopts an NP-TJ-N-O-NP structure, but in practical application, the epitaxial structure can be adjusted into NP-TJ-N-O-PN, PN-TJ-P-O-NP, PN-TJ-P-O-PN and structures according to requirements, wherein N refers to an N-shaped limiting layer or an N-type doped DBR, P refers to a P-shaped limiting layer or a P-type doped DBR, TJ refers to a buried tunnel junction, and O refers to an oxidation isolation layer.

As a second embodiment: the resonant cavity comprises a first limiting layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second limiting layer and an oxidation limiting layer from bottom to top; the first DBR is a first N-type doped DBR; the second DBR is a first P-type doped DBR; the third DBR is a second N-type doped DBR; the fourth DBR is a second P-type doped DBR. It can be seen that the epitaxial structure provided by the present invention is an NP-O-NP structure, but in practical applications, the epitaxial structure can be further adjusted to be an NP-O-PN, PN-O-NP or PN-O-PN structure as required, where N refers to an N-type doped DBR, P refers to a P-type doped DBR, and O refers to an oxide isolation layer.

When the substrate is made of a GaAs system, the thickness of the oxidation limiting layer is 5-5000 nm. The oxidation limiting layer is formed by wet oxidation of an oxidation limiting prefabricated layer, and the oxidation region is formed by Al with optical and electrical limiting functions ₂ O ₃ The pore diameter of the unoxidized area ranges from 2 to 100 mu m; the oxidation limiting prefabricated layer is doped or undoped Al _y Ga _1-y As, wherein 0.92 < y < x. Since the oxidation processes of the oxidation-limiting prefabricated layer and the oxidation-isolating prefabricated layer are simultaneously carried out, and the oxidation-limiting prefabricated layer needs to be partially oxidized to form the photoelectric-limiting aperture, Al adopted by the oxidation-limiting prefabricated layer _y Ga _1-y The Al content of As material is between DBR and oxide isolation layer, so 0.92 < y < x. As can be seen, the prefabricated layer materials of the oxidation limiting layer and the oxidation isolating layer are AlGaAs materials and are matched with the crystal lattices of the GaAs substrate system, so that the epitaxial crystal quality of the VCSEL unit and the EOM unit is ensured, and the reliability of the device is improved. In addition, the invention innovatively creates a differential oxidation method, and the alumina content deviation of the oxidation isolation prefabricated layer and the oxidation limiting prefabricated layer is accurately designed, so that the oxidation isolation layer and the oxidation limiting layer can be formed in the same oxidation process, the chip process is greatly simplified, and the production cost is reduced.

The high-efficiency vertical cavity surface EML chip further comprises a first electrode, a second annular electrode, a third annular electrode and a fourth annular electrode, wherein: the first electrode is a first planar electrode arranged on the lower surface of the substrate or a first annular electrode arranged on the upper surface of the first DBR; the second annular electrode is arranged on the upper surface of the second DBR; the third ring electrode is arranged on the upper surface of the third DBR; the fourth ring-shaped electrode is disposed on an upper surface of the fourth DBR.

Since an oxidation isolation layer having an electrical isolation effect is disposed between the VCSEL unit and the EOM unit, the electrodes cannot be shared, and a four-electrode structure is required. In practical applications, the first electrode can be configured as a first planar electrode or a first ring electrode as required to meet different application scenarios, such as TOP-TOP contact type and TOP-BOTTOM contact type applications.

Compared with the prior art, the invention has the beneficial effects that:

1. the invention breakthroughs an oxidation isolation layer with an electrical insulation effect arranged between the VCSEL unit and the EOM unit to isolate the high-frequency modulation signal applied to the EOM unit, so that the VCSEL unit and the EOM unit are relatively independent, the high-frequency modulation signal is prevented from influencing the current in the VCSEL unit, and the stable output of the VCSEL unit is ensured. Compared with the mode that the VCSEL unit and the EOM unit are in direct contact in the prior art, the electrical isolation can reduce RC delay in the high-frequency signal transmission process, is beneficial to improving transmission performance, and realizes a better modulation effect.

2. Based on the structure of the VCSEL unit, the oxidation isolation layer and the EOM unit, the embossment is arranged above the EOM unit, so that the specular reflectivity of a high-order transverse mode is relatively reduced, the aim of inhibiting the high-order transverse mode is fulfilled, stable output of a basic transverse mode is ensured, the light beam quality is optimized, the threshold current and the insertion loss are reduced, and the single-mode application requirements of the VCSEL chip are met.

Drawings

Fig. 1 is a schematic cross-sectional view of a chip according to a first embodiment of the invention.

Fig. 2 is a schematic diagram of a resonant cavity structure of a VCSEL unit according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a modulation principle provided in an embodiment of the present invention.

Fig. 4 is a schematic structural diagram of a relief provided in the first embodiment of the present invention.

Fig. 5 is a top view of a relief provided in accordance with one embodiment of the present invention.

Fig. 6 is a schematic diagram of the transverse mode control principle of the embossment provided by the first embodiment of the invention.

Fig. 7 is a diagram illustrating the effect of controlling the transverse mode of the relief according to an embodiment of the present invention.

Fig. 8 is a schematic diagram of a resonant cavity structure of a VCSEL unit according to a second embodiment of the present invention.

Fig. 9 is a schematic diagram of a modulation principle provided in a second embodiment of the present invention.

In the figure:

10. substrate 11, buffer layer

12. First N-type doped DBR 13 and resonant cavity

14. Second N-type doped DBR 15, oxide spacer

16. A third N-doped DBR 17, a third waveguide layer

18. Absorption region 19, fourth waveguide layer

110. P-type doped DBR 111, first planar electrode

111', a first ring electrode 112, a second ring electrode

113. Third annular electrode 114, fourth annular electrode

116. Relief (sculpture)

21. A first confinement layer 22, a first waveguide layer

23. Quantum well layer 24, second waveguide layer

25. Second confinement layer 26, buried tunnel junction

27. P-type confinement layer 28, oxide confinement layer

20. A top mirror 30, a bottom mirror.

Detailed Description

The following describes embodiments of the present invention with reference to the drawings. Numerous details are set forth below in order to provide a thorough understanding of the present invention, but it will be apparent to those skilled in the art that the present invention may be practiced without these details.

The first embodiment is as follows:

as shown in fig. 1 and 4, the present embodiment provides a high-efficiency vertical-cavity surface EML chip with a relief, which includes a VCSEL unit, an oxide isolation layer 15, an EOM unit, and a relief 116, where the oxide isolation layer 15 is disposed between the VCSEL unit and the EOM unit, and is used to prevent an electric potential at a contact of the two units from affecting an operating current in the respective units. The relief 116 is disposed above the EOM unit for suppressing high-order transverse modes to realize mode control.

As shown in fig. 1, the VCSEL unit includes, from bottom to top, a substrate 10, a buffer layer 11, a first DBR12, a resonant cavity 13, and a second DBR 14. The EOM cell includes, from bottom to top, a third DBR16, a third waveguide layer 17, an absorption region 18, a fourth waveguide layer 19, and a fourth DBR 110.

As shown in fig. 1, the chip further includes a first electrode, a second ring electrode 112, a third ring electrode 113, and a fourth ring electrode 114. Specifically, in the present embodiment, the first electrode is a first planar electrode 111 disposed on the lower surface of the substrate 10, and in other embodiments, the first electrode may also be a first annular electrode 111' disposed on the upper surface of the first DBR; the second ring electrode 112 is disposed on the upper surface of the second DBR 14; the third ring electrode 113 is disposed on the upper surface of the third DBR 16; the fourth ring-shaped electrode 114 is disposed on an upper surface of the fourth DBR 110.

Preferably, the substrate 10 is a Si-doped GaAs substrate with a doping concentration of 1.5e ¹⁸ cm ^-3 。

Preferably, the buffer layer 11 is a Si-doped GaAs layer with a doping concentration of 2e ¹⁸ cm ^-3 And the thickness is 200 nm.

Preferably, the first DBR12 is a first N-doped DBR, the second DBR14 is a second N-doped DBR, the third DBR16 is a third N-doped DBR, and the first, second and third N-doped DBRs are high index/low index/high index/low index … …/high index structures, the high index material is Si-doped Al _0.12 Ga _0.88 As layer of Si-doped Al As low refractive index material _0.9 Ga _0.1 And an As layer. Si-doped Al _0.12 Ga _0.88 The thickness of As layer is 60nm, the doping concentration is 2e ¹⁸ cm ^-3 Si-doped Al _0.9 Ga _0.1 The As layer thickness was 69.4nm and a doping concentration of 2e ¹⁸ cm ^-3 。

As shown in fig. 2, the optical thickness of the resonant cavity 13 is one wavelength, and the resonant cavity 13 includes, from bottom to top, a first confinement layer 21, a first waveguide layer 22, a quantum well layer 23, a second waveguide layer 24, a second confinement layer 25, a P-type confinement layer 27, and a buried tunnel junction 26.

Preferably, the first confinement layer 21 is Si-doped Al _0.6 Ga _0.4 As with a thickness of 22nm and a doping concentration of 2e ¹⁷ cm ^-3 。

Preferably, the first waveguide layer 22 is Al _0.45 Ga _0.55 As, 18nm thick.

Preferably, the quantum well layer 23 is made of barrier layer Al with a thickness of 10nm _0.35 Ga _0.65 As and a well layer GaAs with the thickness of 8nm, and the lasing wavelength is 850 nm.

Second waveguide layer 24 is preferably Al _0.45 Ga _0.55 As, 30nm thick.

Preferably, the second confinement layer 25 is Si-doped Al _0.6 Ga _0.4 As with a thickness of 62.5nm and a doping concentration of 2e ¹⁸ cm ^-3 。

Preferably, the P-type confinement layer 27 is C-doped AlGaAs or 1-2 pair P-doped DBR with a doping concentration of 2e ¹⁸ cm ^-3 。

Preferably, the buried tunnel junction 26 comprises, from bottom to top, Al _0.2 Ga _0.8 As heavily doped C layer and Al _0.2 Ga _0.8 And the As is heavily doped with the Te layer. Wherein, Al _0.2 Ga _0.8 The thickness of the As heavily-doped C layer is 15nm, and the doping concentration is 1.5e ²⁰ cm ^-3 ；Al _0.2 Ga _0.8 The thickness of the As heavily doped Te layer is 15nm, and the doping concentration is 2e ¹⁹ cm ^-3 The pore size of the buried tunnel junction is 8 μm.

Preferably, the oxide spacer 15 is made of undoped Al with a thickness of 30nm _0.98 Ga _0.02 The As oxidation isolation prefabricated layer is formed into Al with electrical insulation effect by wet oxidation process ₂ O ₃ An isolation layer, thereby effectively preventing the contact between the VCSEL unit and the EOM unitInfluences the current in the VCSEL unit, further improving the performance of the VCSEL.

Preferably, third waveguide layer 17 is Si-doped Al _0.45 Ga _0.55 As with a thickness of 77nm and a doping concentration of 2e ¹⁷ cm ^-3 。

Preferably, the absorption zone 18 is a pair of Al _0.35 Ga _0.65 Quantum well with As As barrier and GaAs well, Al _0.35 Ga _0.65 The thickness of the As barrier layer is 5nm, the thickness of the GaAs well layer is 6nm, the thickness of the absorption region 18 is 450nm, and the wavelength of a quantum well of the absorption region 18 is 830 nm.

Preferably, fourth waveguide layer 19 is C-doped Al _0.45 Ga _0.55 As with a thickness of 77nm and a doping concentration of 2e ¹⁷ cm ^-3 . The third waveguide layer 17 and the fourth waveguide layer 19 are doped N-type and P-type, respectively, to form PN junctions, and the absorption region 18 is formed between the PN junctions.

Preferably, the fourth DBR110 is a P-doped DBR, and the P-doped DBR is a periodically stacked high refractive index/low refractive index/high refractive index/low refractive index …/high refractive index structure, and the high refractive index material is C-doped Al _0.12 Ga _0.88 As layer, low refractive index material is C-doped Al _0.9 Ga _0.1 And an As layer. C-doped Al _0.12 Ga _0.88 The thickness of As layer is 60nm, the doping concentration is 2e ¹⁸ cm ^-3 (ii) a C-doped Al _0.9 Ga _0.1 The thickness of the As layer is 69.4nm, and the doping concentration is 2e ¹⁸ cm ^-3 。

The principle of operation of the buried tunnel junction 26 is: buried in a degenerated heavily doped semiconductor, the fermi level of the n-type semiconductor enters the conduction band and the fermi level of the p-type semiconductor enters the valence band. Due to quantum mechanical tunneling, electrons of the n-region conduction band may cross the forbidden band to the p-type valence band, and electrons of the p-region valence band may also cross the forbidden band to the n-region conduction band, thereby possibly generating a tunneling current. Here, in one aspect, the electrical and optical confinement is achieved by replacing the oxidized confinement layer with a buried tunnel junction 26. On the other hand, the buried tunnel junction 26 reverses the polarity of the PDBR, thereby avoiding light absorption loss and heat loss caused by high free carrier absorption and resistance due to the PDBR, and facilitating the improvement of the light extraction efficiency of the VCSEL unit; on the other hand, in the process, because point defects and dislocations are generated at the interface between the oxide layer and the semiconductor during the oxidation process of the oxidation limiting layer, and the thermal expansion coefficients of the oxide layer and the semiconductor are different, the oxidation process is usually very difficult to control, the process window is very narrow, and the oxide layer-semiconductor interface is easy to crack or peel off after the oxidation process. Replacing the oxide confinement layer of prior art VCSEL cells with a buried tunnel junction helps to improve manufacturing yield. Therefore, the buried tunnel junction is used for replacing the oxidation limiting layer to realize optical and electrical limitation, which is beneficial to improving the light extraction efficiency and the manufacturing yield of the VCSEL.

As shown in fig. 3, the modulation principle of this embodiment is: when the third ring electrode 113 and the fourth ring electrode 114 are not biased or are biased at a lower voltage, the absorption curve of the EOM unit is in a blue shift direction compared with the emission wavelength of the VCSEL unit, and the light beam excited by the VCSEL unit does not suffer absorption loss after passing through the EOM unit. When a higher bias voltage is applied to the EOM unit, the absorption spectrum sideband of the EOM unit can rapidly drift to a long wavelength due to Quantum Confinement Stark Effect (QCSE) and covers the emission wavelength of the VCSEL unit, so that the high-speed electrical modulation signal applied to the EOM unit directly influences the movement of the absorption sideband, and the high-speed modulation of the light intensity of the VCSEL light is realized. In this embodiment, the EOM cells are isolated from the VCSEL cells by the oxide isolation layer 15, which is relatively independent, and helps to achieve a better modulation effect.

As shown in fig. 4 to 7, the material on the upper surface of the P-type DBR is selectively etched to form a relief 116, the middle of the relief 116 has a ring-shaped region with a certain size, which can be designed into a ring shape or a square ring shape with a certain width and depth according to the actual optical field, the ring-shaped etched region corresponds to the high-order lateral mode exit region, the central region of the light exit hole is kept unchanged, and the central portion of the light exit hole presents an unetched region in a shape of a boss, which is the exit region of the fundamental lateral mode. The reflectivity of the etched area and the non-etched area has a thickness difference, which causes the reflectivity of the two areas to the light beam to change, so the reflectivity of the etched area is lower than that of the non-etched area, and the high-order transverse mode corresponding to the etched area is inhibited. Therefore, the mirror loss of the high-order mode can be increased by optimally designing the width, the depth and the height of the embossment, so that the mirror reflectivity of the high-order mode is relatively reduced, the aim of inhibiting the lasing of the high-order mode is fulfilled, and the stable output of the fundamental transverse mode is effectively realized. Preferably, in the present embodiment, the shape of the relief 116 is a circular ring structure, and the material of the relief 116 is GaAs.

The preparation method of the embodiment comprises the following steps:

1. a buffer layer 11, a first N-type doped DBR and a resonant cavity 13 are sequentially deposited on a substrate 10 by adopting an MOCVD method, and the resonant cavity 13 comprises a first limiting layer 21, a first waveguide layer 22, a quantum well layer 23, a second waveguide layer 24, a second limiting layer 25, a P-type limiting layer 27 and a tunnel junction layer.

2. Forming a tunneling junction etching mask SiNx on the surface of the tunneling junction layer by using an enhanced plasma chemical vapor deposition method, photoetching and reactive ion etching processes, then etching the tunneling junction layer by using inductively coupled plasma to form a buried tunneling junction 26 with the aperture of 8 mu m, and finally removing the tunneling junction etching mask SiNx by using BOE.

3. Adopting MOCVD method to continuously grow a second N-type doped DBR and an oxidation isolation prefabricated layer (Al) on the surface of the buried tunnel junction in sequence _0.98 Ga _0.02 As), a third N-doped DBR, a third waveguide layer 17, an absorption region 18, a fourth waveguide layer 19 and a P-doped DBR.

4. The substrate 10 is etched using ICP to expose the buffer layer 11, and a first planar electrode 111 is prepared on the surface of the buffer layer 11 away from the first N-doped DBR.

5. Firstly, forming a contact layer selective mask SiNx on the top of the second N-type doping DBR through a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, photoetching and Reactive Ion Etching (RIE) process, then performing selective edge etching through ICP etching, so that an epitaxial structure above the top of the second N-type doping DBR is etched to the upper surface of the second N-type doping DBR, and then removing the contact layer selective mask SiNx through BOE; finally, a second ring electrode 112 is formed on the upper surface of the second N-type doped DBR by a photolithography process, an electron beam evaporation metal layer process, and a lift-off process.

6. By wet oxidationThe process pair comprises Al _0.98 Ga _0.02 Oxidizing the As oxidation isolation prefabricated layer to form Al As component ₂ O ₃ The oxide isolation layer 15.

7. Referring to the method of step 5, a third ring electrode 113 is formed on the upper surface of the third N-type doped DBR, but it should be noted that in the ICP etching, a selective edge etching must be performed on the epitaxial structure above 200nm from the bottom of the third N-type doped DBR to prevent the oxide isolation layer 15 from being etched through, which may cause the oxide isolation layer 15 to fail. A fourth ring electrode 114 is then fabricated on the upper surface of the P-doped DBR using known techniques.

8. A surface relief 116 is formed on the upper surface of the P-type doped DBR by dry etching or wet etching.

It should be noted that, in step 6, the reason for selecting the oxidation process for oxidizing the isolation pre-layer after the first planar electrode 111 and the second annular electrode 112 are prepared is that: firstly, the advantage that the alignment of the metal layer (namely the first planar electrode 111 and the second annular electrode 112 is more accurate) can be fully utilized in the oxidation process, the oxidation process is accurate and controllable, secondly, the oxidation area of the oxidation process can be reduced by the etching process of the first planar electrode 111 and the second annular electrode 112, the oxidation time can be greatly saved, and the uniformity of the oxidation can be improved, thirdly, the oxidation isolation prefabricated layer can generate stress after being oxidized, certain influence can be generated on the etching step of the metal electrode part, and therefore the metal electrode part needs to be manufactured firstly.

The reason why the third annular electrode 113 and the fourth annular electrode 114 are selectively prepared after the oxidation process is that, in the oxidation process, whether the oxidation isolation prefabricated layer is sufficiently oxidized to form the oxidation isolation layer 15 needs to be observed under an infrared microscope, and if the oxidation is performed on the metal layer above the oxidation isolation prefabricated layer, the appearance of the oxidation isolation layer 15 is not favorable to be observed.

Example two:

as shown in fig. 1 and 4, the structural design of this embodiment is substantially the same as that of the first embodiment, but the structure of the resonant cavity 13, the modulation principle of the EOM unit, and the fabrication method of the VCSEL chip are different. First, the structure of the resonant cavity 13 in this embodiment will be explained:

as shown in fig. 8, the resonant cavity 13 includes, from bottom to top, a first confinement layer 21, a first waveguide layer 22, a quantum well layer 23, a second waveguide layer 24, a second confinement layer 25, and an oxidation confinement layer 28.

Preferably, the oxide confinement layer 28 is formed of undoped Al having a thickness of 30nm _0.93 Ga _0.07 The As oxidation limiting prefabricated layer is formed by a wet oxidation process, the aperture of an unoxidized area is reserved by 8 mu m, and an oxidized area forms Al with optical and electrical limiting functions ₂ O ₃ 。

As shown in fig. 1, the first to fourth DBRs in this embodiment are different from the first embodiment in terms of the difference of the resonant cavity 13:

the first DBR12 is a first N-doped DBR, the third DBR16 is a second N-doped DBR, and the first and second N-doped DBRs are of high/low/high/low … …/high index structure, the high index material is Si-doped Al _0.12 Ga _0.88 As layer, low refractive index material is Si-doped Al _0.9 Ga _0.1 And an As layer. Si-doped Al _0.12 Ga _0.88 The thickness of As layer is 60nm, the doping concentration is 2e ¹⁸ cm ^-3 Si-doped Al _0.9 Ga _0.1 The thickness of As layer is 69.4nm, the doping concentration is 2e ¹⁸ cm ^-3 。

The second DBR14 is a first P-type doped DBR, the fourth DBR110 is a second P-type doped DBR, the first P-type doped DBR and the second P-type doped DBR are periodically overlapped high refractive index/low refractive index/high refractive index/low refractive index …/high refractive index structures, and the high refractive index material is C-doped Al _0.12 Ga _0.88 As layer, low refractive index material is C-doped Al _0.9 Ga _0.1 And an As layer. C-doped Al _0.12 Ga _0.88 The thickness of As layer is 60nm, the doping concentration is 2e ¹⁸ cm ^-3 (ii) a C-doped Al _0.9 Ga _0.1 The thickness of the As layer is 69.4nm, and the doping concentration is 2e ¹⁸ cm ^-3 。

The modulation method in this embodiment is explained in detail below:

in this embodiment, the third waveguide layer 17 and the fourth wave are not providedA conductive layer 19 and an absorbing region 18 of a plurality of pairs of Al _0.35 Ga _0.65 Quantum well with As As barrier and GaAs well, Al _0.35 Ga _0.65 The thickness of the As barrier layer is 5nm, the thickness of the GaAs well layer is 6nm, and the thickness of the absorption region is 450 nm. Increasing the number of quantum wells of the absorbing region 18 reduces the number of cycles of the top P-doped DBR 110.

As shown in fig. 1, the bottom mirror 30 is all the part below the resonator 13, and the top mirror 20 is all the part above the resonator 13. The overall reflectivity of the bottom mirror 30 can be designed to be 99.995% and the overall reflectivity of the top mirror 20 can be designed to be 99.89% for the lasing wavelength of the resonant cavity 13 of 850 nm. The absorption region 18 of the EOM cell is placed where the light intensity of the top mirror 20 is maximum.

As shown in fig. 9, the modulation principle of this embodiment is: when no bias voltage or low bias voltage is applied between the third ring electrode 113 and the fourth ring electrode 114, the absorption region 18 in the EOM unit is in an unabsorbed state, at this time, the reflectivity of the bottom mirror 30 is 99.995%, the reflectivity of the top mirror 20 is 99.89%, photons emitted from the quantum well 23 can form continuous and stable back-and-forth oscillation in the resonant cavity 13, and light output can be formed through the top mirror 20 after the gain reaches a certain value; when a higher bias voltage is applied between the third ring electrode 113 and the fourth ring electrode 114, the absorption effect of the absorption region 18 in the EOM unit is enhanced, the reflectivity of the top mirror 20 is reduced to 99.68%, and at this time, photons emitted from the quantum well 23 cannot continuously and stably oscillate in the resonant cavity 13, or the gain is insufficient, the light intensity cannot penetrate through the top mirror 20 to stabilize the light output, or the output laser power is reduced. Therefore, by modulating the bias level of the EOM cell and changing the operating state of the absorption region 18, the reflectivity of the top DBR can be affected, thereby achieving high-speed modulation of the light intensity of the VCSEL unit.

The method for manufacturing the VCSEL chip of the present embodiment is described in detail below: which comprises the following steps:

1. a buffer layer 11, a first N-type doped DBR, a resonant cavity 13, a first P-type doped DBR, an oxidation isolation prefabricated layer, a second N-type doped DBR, a third waveguide layer 17, an absorption region 18, a fourth waveguide layer 19 and a second P-type doped DBR are sequentially grown on a substrate 10 by adopting an MOCVD method; the resonant cavity 13 includes a first confinement layer 21, a first waveguide layer 22, a quantum well layer 23, a second waveguide layer 24, a second confinement layer 25, and an oxidation confinement pre-fabricated layer.

2. The substrate 10 is etched by ICP to expose the buffer layer 11, and a first planar electrode is prepared on the surface of the buffer layer 11 away from the first N-type doped DBR.

3. Firstly, forming a contact layer selective mask SiNx on the upper surface of a first P-type doping DBR through a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, photoetching and Reactive Ion Etching (RIE) process, then performing selective edge etching through ICP etching, so that an epitaxial structure above the top of the first P-type doping DBR is etched to the upper surface of the first P-type doping DBR, and then removing the contact layer selective mask SiNx through BOE; finally, a second ring electrode 112 is formed on the upper surface of the first P-type doped DBR through a photolithography process, an electron beam evaporation metal layer process, and a lift-off process.

4. Adopts a wet oxidation process to prepare Al _0.98 Ga _0.02 As oxidation isolation prefabricated layer and Al component _0.93 Ga _0.07 Oxidizing the As oxidation limiting preform layer to form Al ₂ O ₃ Oxide isolation layer 15 and oxide confinement layer 28.

5. Referring to the method of step 4, a third ring electrode 113 is formed on the upper surface of the second N-type doped DBR, but it should be noted that in the ICP etching, a selective edge etching must be performed on the epitaxial structure above 200nm from the bottom of the second N-type doped DBR to prevent the oxide isolation layer 15 from being etched through, which may cause the oxide isolation layer 15 to fail. A fourth ring electrode 114 is then fabricated on the upper surface of the second P-doped DBR using known techniques.

6. On the upper surface of the second P-type doped DBR, a relief 116 is formed by dry etching or wet etching.

The above description is only an embodiment of the present invention, but the design concept of the present invention is not limited thereto, and any insubstantial modifications made by using the design concept should fall within the scope of infringing the present invention.

Claims

1. The utility model provides a take high-efficient vertical cavity surface EML chip of relief (sculpture), its characterized in that: the device comprises a VCSEL unit, an oxidation isolation layer, an EOM unit and a relief, wherein:

the VCSEL unit comprises a substrate, a buffer layer, a first DBR, a resonant cavity and a second DBR from bottom to top;

the EOM unit comprises a third DBR, an absorption region and a fourth DBR from bottom to top;

the oxidation isolation layer is arranged between the VCSEL unit and the EOM unit and used for preventing the electric potential of the contact position of the two units from influencing the working current in the respective units;

the relief is arranged above the EOM unit and used for restraining a high-order transverse mode so as to realize mode control.

2. The high-efficiency vertical-cavity surface EML chip with relief of claim 1, wherein: the material of the oxidation isolation layer is Al ₂ O ₃ Which is made of Al _x Ga _1-x The As prefabricated layer is formed by oxidation through a wet oxidation process, wherein x is more than or equal to 0.97; the first DBR, the second DBR, the third DBR and the fourth DBR are made of Al _i Ga _1-i As/Al _j Ga _1-j The As material has a periodic structure, and i and j are not more than 0.92.

3. The high-efficiency vertical-cavity surface EML chip with relief of claim 2, wherein: the resonant cavity comprises a first limiting layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second limiting layer, a P-type limiting layer and a buried tunnel junction from bottom to top; the first DBR is a first N-type doped DBR; the second DBR is a second N-type doped DBR; the third DBR is a third N-type doped DBR; the fourth DBR is a P-type doped DBR.

4. The high-efficiency vertical-cavity surface EML chip with relief of claim 2, wherein: the resonant cavity comprises a first limiting layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second limiting layer and an oxidation limiting layer from bottom to top; the first DBR is a first N-type doped DBR; the second DBR is a first P-type doped DBR; the third DBR is a second N-type doped DBR; the fourth DBR is a second P-type doped DBR.

5. The high-efficiency vertical-cavity surface EML chip with relief of claim 4, wherein: the oxidation limiting layer is formed by an oxidation limiting prefabricated layer through a wet oxidation process, and the aperture range of an unoxidized area is 2-100 mu m; the oxidation limiting prefabricated layer is doped or undoped Al _y Ga _1-y As, wherein 0.92 < y < x.

6. The high-efficiency vertical-cavity surface EML chip with relief of claim 1, wherein: the wavelength of the quantum well of the absorption region is 5-99nm shorter than that of the quantum well of the resonant cavity.

7. The high-efficiency vertical-cavity surface EML chip with relief of claim 1, wherein: still include first electrode, second annular electrode, third annular electrode and fourth annular electrode, wherein: the first electrode is a first planar electrode arranged on the lower surface of the substrate or a first annular electrode arranged on the upper surface of the first DBR; the second annular electrode is arranged on the upper surface of the second DBR; the third ring electrode is arranged on the upper surface of the third DBR; the fourth ring-shaped electrode is disposed on an upper surface of the fourth DBR.

8. The high-efficiency vertical-cavity surface EML chip with relief of claim 1, wherein: the embossment is of an annular structure with a hollow middle part.

9. The high-efficiency vertical-cavity surface EML chip with relief of claim 8, wherein: the relief is in a circular ring structure or a square ring structure.

10. The embossed high-efficiency vertical-cavity surface EML chip of claim 9, wherein: the relief is made of a polymer material, a dielectric material or a semiconductor material, wherein the polymer material is PI or BCB; the dielectric material is silicon nitride, silicon oxide or aluminum oxide; the semiconductor material is GaAs or AlGaAs.