CN108807532B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN108807532B
CN108807532B CN201710290101.0A CN201710290101A CN108807532B CN 108807532 B CN108807532 B CN 108807532B CN 201710290101 A CN201710290101 A CN 201710290101A CN 108807532 B CN108807532 B CN 108807532B
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dielectric layer
layer
fin
gate
dummy gate
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CN108807532A (zh
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李勇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to US15/918,693 priority patent/US20180315857A1/en
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Abstract

本申请公开了一种半导体装置及其制造方法，涉及半导体技术领域。其中，所述方法包括：提供衬底结构，所述衬底结构包括：衬底；在所述衬底上的鳍片；在所述鳍片上的硬掩模层；以及在所述衬底上用于隔离所述鳍片的第一隔离材料层，所述第一隔离材料层的上表面与所述硬掩模层的上表面基本齐平；对所述第一隔离材料层进行回刻，从而形成上表面高于所述硬掩模层的底表面的第二隔离材料层；在对所述第一隔离材料层进行回刻之后，执行氧化工艺或退火工艺；在执行氧化工艺或退火工艺之后，去除所述硬掩模层；对所述第二隔离材料层进行回刻，从而形成上表面低于所述鳍片的上表面的隔离区。本申请可以实现鳍片顶部的边角的圆形化。

Description

半导体装置及其制造方法
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体装置及其制造方法。
背景技术
随着金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor FieldEffect Transistor，MOSFET)关键尺寸的缩小，短沟道效应(Short Channel Effect，SCE)越来越严重。鳍式场效应晶体管(Fin Field Effect Transistor，FinFET)具有良好的栅控能力，能够有效地抑制SCE。
本申请的发明人发现：鳍片顶部的边角的圆形化(corner rounding)对FinFET的性能很重要。如果边角的圆形化处理比较差，则会带来诸如FinFET的IV曲线出现驼峰(dump)、反短沟道效应(Reverse Short Channel Effect，RSCE)、栅漏电流大和可靠性差等问题。
现有的FinFET的制造工艺还不能实现鳍片顶部的边角的圆形化，因此，有必要提出一种实现鳍片顶部的边角的圆形化的方案。
发明内容
本申请的一个目的在于提供一种半导体装置的制造方法，能够实现鳍片顶部的边角的圆形化。
根据本申请的一方面，提供了一种半导体装置的制造方法，包括：提供衬底结构，所述衬底结构包括：衬底；在所述衬底上的鳍片；在所述鳍片上的硬掩模层；以及在所述衬底上用于隔离所述鳍片的第一隔离材料层，所述第一隔离材料层的上表面与所述硬掩模层的上表面基本齐平；对所述第一隔离材料层进行回刻，从而形成上表面高于所述硬掩模层的底表面的第二隔离材料层；在对所述第一隔离材料层进行回刻之后，执行氧化工艺或退火工艺；在执行氧化工艺或退火工艺之后，去除所述硬掩模层；对所述第二隔离材料层进行回刻，从而形成上表面低于所述鳍片的上表面的隔离区。
在一个实施例中，所述第二隔离材料层的上表面与所述硬掩模层的底表面之间的距离为3-15nm。
在一个实施例中，所述氧化工艺包括干法氧化工艺、湿法氧化工艺或现场水汽生成工艺。
在一个实施例中，所述退火工艺的工艺条件包括：退火气氛包括氢气或氦气；退火温度为600-800℃；退火压强为1torr-1atm；退火时间为10mins-240mins。
在一个实施例中，所述鳍片包括用于第一器件的第一鳍片和用于第二器件的第二鳍片。
在一个实施例中，所述方法还包括：形成第一栅极结构和第二栅极结构；其中，所述第一栅极结构包括在所述第一鳍片暴露的表面上的栅极电介质层、在所述栅极电介质层上的第一高K电介质层和在所述第一高K电介质层上的第一栅极；所述第二栅极结构包括在所述第二鳍片暴露的表面上的界面层、在所述界面层上的第二高K电介质层和在所述第二高K电介质层上的第二栅极。
在一个实施例中，所述形成第一栅极结构和第二栅极结构包括：在所述第一鳍片暴露的表面上形成第一伪栅电介质层，并在所述第二鳍片暴露的表面上形成第二伪栅电介质层，所述第一伪栅电介质层的厚度大于所述第二伪栅电介质层的厚度；在所述第一伪栅电介质层和所述第二伪栅电介质层上形成伪栅；沉积层间电介质层并进行平坦化工艺，以露出所述伪栅；去除所述伪栅；去除所述第二伪栅电介质层；在所述第二鳍片暴露的表面上形成界面层；在所述界面层和所述第一伪栅电介质层上形成高K电介质层，其中，所述第一伪栅电介质层作为所述栅极电介质层，所述第一伪栅电介质层上的高K电介质层作为所述第一高K电介质层，所述界面层上的高K电介质层作为所述第二高K电介质层；在所述第一高K电介质层上形成所述第一栅极，在所述第二高K电介质层上形成所述第二栅极。
在一个实施例中，所述第一器件包括输入/输出器件，所述第二器件包括内核器件。
根据本申请的另一方面，提供了一种半导体装置，包括：衬底；在所述衬底上的鳍片；在所述鳍片上的硬掩模层；以及在所述衬底上用于隔离所述鳍片的隔离区；其中，所述隔离区上表面高于所述硬掩模层的底表面；所述鳍片的顶部具有圆形化的边角。
在一个实施例中，所述隔离区的上表面与所述硬掩模层的底表面之间的距离为3-15nm。
根据本申请的又一方面，提供了一种半导体装置，包括：衬底；在所述衬底上的鳍片；以及在所述衬底上用于隔离所述鳍片的隔离区；其中，所述隔离区上表面低于所述鳍片的上表面；所述鳍片的顶部具有圆形化的边角。
在一个实施例中，所述鳍片包括用于第一器件的第一鳍片和用于第二器件的第二鳍片。
在一个实施例中，所述装置还包括：第一栅极结构以及第二栅极结构；其中，第一栅极结构包括：在所述第一鳍片暴露的表面上的栅极电介质层；在所述栅极电介质层上的第一高K电介质层；和在所述第一高K电介质层上的第一栅极；第二栅极结构包括：在所述第二鳍片暴露的表面上的界面层；在所述界面层上的第二高K电介质层；和在所述第二高K电介质层上的第二栅极。
在一个实施例中，所述第一器件包括输入/输出器件，所述第二器件包括内核器件。
本申请提供的半导体装置的制造方法通过两次回刻工艺形成隔离区，并且，在第一次回刻工艺后执行氧化工艺或退火工艺，如此可以使得鳍片的顶部的边角圆形化，改善了器件的RSCE、栅漏电流大和可靠性差的问题。另外，氧化工艺还可以使得隔离区变得更致密化，从而可以减小后续工艺(例如湿法刻蚀工艺)对隔离区造成的损失。
通过以下参照附图对本申请的示例性实施例的详细描述，本申请的其它特征、方面及其优点将会变得清楚。
附图说明
附图构成本说明书的一部分，其描述了本申请的示例性实施例，并且连同说明书一起用于解释本申请的原理，在附图中：
图1是根据本申请一个实施例的半导体装置的制造方法的流程图；
图2A-图2E示出了根据本申请一个实施例的半导体装置的制造方法的各个阶段的示意图；
图3A-图3I示出了根据本申请另一个实施例的半导体装置的制造方法的各个阶段的示意图。
具体实施方式
现在将参照附图来详细描述本申请的各种示例性实施例。应理解，除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不应被理解为对本申请范围的限制。
此外，应当理解，为了便于描述，附图中所示出的各个部件的尺寸并不必然按照实际的比例关系绘制，例如某些层的厚度或宽度可以相对于其他层有所夸大。
以下对示例性实施例的描述仅仅是说明性的，在任何意义上都不作为对本申请及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和装置可能不作详细讨论，但在适用这些技术、方法和装置情况下，这些技术、方法和装置应当被视为本说明书的一部分。
应注意，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义或说明，则在随后的附图的说明中将不需要对其进行进一步讨论。
图1是根据本申请一个实施例的半导体装置的制造方法的流程图。图2A-图2E示出了根据本申请一个实施例的半导体装置的制造方法的各个阶段的示意图。
下面结合图1、图2A-图2E对根据本申请一个实施例的半导体装置的制造方法进行详细说明。
如图1所示，首先，在步骤102，提供衬底结构。如图2A所示，衬底结构包括衬底201、在衬底201上的鳍片202、在鳍片202上的硬掩模层203以及在衬底201上用于隔离鳍片202的第一隔离材料层204。这里，第一隔离材料层204的上表面与硬掩模层203的上表面基本齐平，也即，在半导体制造工艺偏差范围内的齐平。在一个实施例中，在鳍片202和硬掩模层203之间可以有缓存层207，也可以称为垫氧化物层(pad oxide)，缓存层207的存在可以增加鳍片202和硬掩模层203之间的结合力。
衬底201例如可以是硅衬底、III-V族半导体衬底等。鳍片202的材料可以是与衬底201的材料相同的半导体材料，也可以是与衬底201的材料不同的半导体材料。硬掩模层203典型地可以是硅的氮化物、硅的氧化物或硅的氮氧化物等。第一隔离材料层204例如可以是硅的氧化物等电介质材料。
在一个实施例中，鳍片202可以包括用于第一器件的第一鳍片212和用于第二器件的第二鳍片222。在一个实施例中，第一器件可以是输入输出(I/O)器件，第二器件可以是内核器件。应理解，虽然图2A及后面的图中示出了一个第一鳍片212和两个第二鳍片222，但这仅仅是示意性的，并不用于限制本申请的范围。
在一个实现方式中，可以通过如下方式形成衬底结构：首先，在初始衬底上形成图案化的硬掩模层203。然后，以硬掩模层203为掩模对初始衬底进行刻蚀，从而形成衬底201和鳍片202。之后，沉积隔离材料以填充各个鳍片之间的空间并覆盖鳍片202和鳍片202上的硬掩模层203。例如，可以通过诸如流式化学气相沉积(Flowable Chemical VapourDeposition,FCVD)的CVD技术等沉积隔离材料。之后，对隔离材料进行平坦化，例如化学机械平坦化(CMP)，以使剩余的隔离材料(也即第一隔离材料层204)的上表面与硬掩模层203的上表面基本齐平，从而形成衬底结构。优选地，在沉积隔离材料之前还可以在鳍片202的表面形成衬垫层，以修复刻蚀形成鳍片202时对鳍片202造成的损伤。优选地，在沉积隔离材料的步骤与平坦化步骤之间还可以进行退火工艺。
回到图1，接下来，在步骤104，对第一隔离材料层204进行回刻，从而形成上表面高于硬掩模层203的底表面的第二隔离材料层205，如图2B所示。这里，回刻后剩余的第一隔离材料层204即为第二隔离材料层205。优选地，为了防止后续氧化工艺中的氧以及退火工艺中的气氛中的某些元素(例如氢等)过多地进入鳍片202中，第二隔离材料层205的上表面与硬掩模层203的底表面之间的距离可以为3-15nm，例如5nm、8nm、10nm、12nm等。
然后，在步骤106，在对第一隔离材料层204进行回刻之后，执行氧化工艺或退火工艺。氧化工艺和退火工艺可以使得鳍片202的边角变得圆形化，如图2C所示。
在一个实现方式中，上述氧化工艺可以包括干法氧化工艺、湿法氧化工艺或现场水汽生成(ISSG)工艺等。在氧化工艺中，鳍片202的顶部的边角被氧化，从而使得边角变得圆形化。
在一个实现方式中，退火工艺的工艺条件包括：退火气氛包括氢气或氦气；退火温度为600-800℃，例如650℃、700℃；退火压强为1torr-1atm，例如50torr、100torr、300torr等；退火时间为10mins-240mins，例如20mins、60mins、120mins等。在退火工艺中，鳍片202边角的材料会发生迁移，从而使得边角变得圆形化。
之后，在步骤108，在执行氧化工艺或退火工艺之后，去除硬掩模层203，如图2D所示。
之后，在步骤110，对第二隔离材料层205进行回刻，从而形成上表面低于鳍片202的上表面的隔离区206，如图2E所示。这里，回刻后剩余的第二隔离材料层205即为隔离区206。需要说明的是，在鳍片202与硬掩模层203之间具有缓存层207的情况下，对第二隔离材料层205进行回刻时还可以同时将缓存层207去除，或者通过额外的工艺将缓存层207去除。
如上描述了根据本申请一个实施例的半导体装置的制造方法。该方法通过两次回刻工艺形成隔离区，并且，在第一次回刻工艺后执行氧化工艺或退火工艺，如此可以使得鳍片的顶部的边角圆形化，改善了器件的RSCE、栅漏电流大和可靠性差的问题。另外，氧化工艺还可以使得隔离区变得更致密化，从而可以减小后续工艺(例如湿法刻蚀工艺)对隔离区造成的损失。
之后，可以在第一鳍片212上形成第一栅极结构，在第二鳍片222上形成第二栅极结构。
下面介绍一种形成第一栅极结构和第二栅极结构的具体实现方式。
首先，在第一鳍片212暴露的表面上形成第一伪栅电介质层301，并在第二鳍片222暴露的表面上形成第二伪栅电介质层302，这里，第一伪栅电介质层301的厚度大于第二伪栅电介质层302的厚度。
在一个实现方式中，可以通过如图3A和图3B所示的方式形成第一伪栅电介质层301和第二伪栅电介质层302：
如图3A所示，例如可以通过ISSG工艺在第一鳍片212和第二鳍片222暴露的表面上形成第一伪栅电介质层301，例如硅的氧化物层。
如图3B所示，去除第二鳍片222的表面上的第一伪栅电介质层301，然后在第二鳍片222暴露的表面上形成厚度小于第一伪栅电介质层301的第二伪栅电介质层302。例如，可以通过ISSG工艺在第二鳍片222暴露的表面上形成硅的氧化物层作为第二伪栅电介质层302。
然后，如图3C所示，在第一伪栅电介质层301和第二伪栅电介质层302上形成伪栅303，例如多晶硅伪栅。
在一个实现方式中，可以先在图3B所示的结构上沉积伪栅材料，然后对伪栅材料进行平坦化，之后在平坦化后的伪栅材料上形成图案化的硬掩模304，之后以硬掩模304为掩模对伪栅材料对进行图案化，从而形成伪栅303，之后可以去除硬掩模304。
接下来，如图3D所示，沉积层间电介质层305并进行平坦化工艺，以露出伪栅303。这里，层间电介质层305例如可以是硅的氧化物。
然后，如图3E所示，去除伪栅303，以形成沟槽。
之后，如图3F所示，去除第二伪栅电介质层302，以露出第二鳍片222的表面。
例如，可以在沟槽中形成图案化的掩模层306，以覆盖第一伪栅电介质层301，而使得第二伪栅电介质层302暴露；然后，可以通过干法或湿法刻蚀去除第二伪栅电介质层302；之后去除掩模层306。
需要说明的是，在一个实施例中，去除第二伪栅电介质层202时可能会去除未被掩模层306覆盖的隔离区206的一部分，造成了隔离区的损失，使得被掩模层306覆盖的隔离区206与未被掩模层306覆盖的隔离区206的高度不同。如上所述，如果进行了氧化工艺，则可以减小隔离区206的损失。
之后，如图3G所示，在第二鳍片222的表面上形成界面层307，例如可以通过热生长的方式形成硅的氧化物层作为界面层307。优选地，在形成界面层307之前还可以进行预清洗，以去除在去除第二伪栅电介质层302留下的残余物。
之后，如图3H所示，在界面层307和第一伪栅电介质层301上形成高K电介质层308，例如氧化铪等。这里，高K电介质层308还可以形成在沟槽的侧壁以及隔离区206的表面上。第一伪栅电介质层301作为用于第一器件的栅极电介质层，第一伪栅电介质层301上的高K电介质层308作为第一高K电介质层318，界面层307上的高K电介质层308作为第二高K电介质层328。
此外，在形成高K电介质层308后，还可以进行退火工艺。
之后，如图3I所示，可以在第一高K电介质层318上形成第一栅极319，在第二高K电介质层328上形成第二栅极329。
例如，可以在高K电介质层308上沉积栅极材料309，例如金属，然后对栅极材料309进行图案化，从而形成第一栅极319和第二栅极329。
如上，根据图3A-图3I所示工艺形成了第一栅极结构和第二栅极结构。所形成的第一栅极结构包括在第一鳍片212暴露的表面(也即位于隔离区206以上的部分的表面)上的栅极电介质层301、在栅极电介质层301上的第一高K电介质层318和在第一高K电介质层318上的第一栅极319。所形成的第二栅极结构包括在第二鳍片322暴露的表面(也即位于隔离区206以上的部分的表面)上的界面层307、在界面层307上的第二高K电介质层328和在第二高K电介质层328上的第二栅极329。
本申请还公开了一种半导体装置，参见图2C，半导体装置可以包括：衬底201、在衬底上的鳍片202、在鳍片202上的硬掩模层203以及在衬底201上用于隔离鳍片202的隔离区205(对应第二隔离层)。这里，隔离区205上表面高于硬掩模层203的底表面，并且，鳍片202的顶部具有圆形化的边角。优选地，隔离区205的上表面与硬掩模层203的底表面之间的距离为3-15nm，例如5nm、8nm、10nm、12nm等。
本申请还公开了另一种半导体装置，参见图2E，半导体装置包括：衬底201、在衬底201上的鳍片202以及在衬底201上用于隔离鳍片202的隔离区206。这里，隔离区206上表面低于鳍片202的上表面，并且，鳍片202的顶部具有圆形化的边角。在一个实施例中，鳍片202包括用于第一器件的第一鳍片212和用于第二器件的第二鳍片222。在一个实施例中，第一器件包括输入/输出器件，第二器件包括内核器件。
本申请还公开了另一种半导体装置，参见图3I，与图2E所示半导体装置相比，图3I所示半导体装置还包括在第一鳍片212上的第一栅极结构和在第二鳍片222上的第二栅极结构。第一栅极结构和第二栅极结构的具体结构可以参照上面的描述，在此不再赘述。
至此，已经详细描述了根据本申请实施例的半导体装置及其制造方法。为了避免遮蔽本申请的构思，没有描述本领域所公知的一些细节，本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。另外，本说明书公开所教导的各实施例可以自由组合。本领域的技术人员应该理解，可以对上面说明的实施例进行多种修改而不脱离如所附权利要求限定的本申请的精神和范围。

Claims (8)

1.一种半导体装置的制造方法，其特征在于，包括：
提供衬底结构，所述衬底结构包括：衬底；在所述衬底上的鳍片；在所述鳍片上的硬掩模层；以及在所述衬底上用于隔离所述鳍片的第一隔离材料层，所述第一隔离材料层的上表面与所述硬掩模层的上表面基本齐平；
对所述第一隔离材料层进行回刻，从而形成上表面高于所述硬掩模层的底表面的第二隔离材料层；
在对所述第一隔离材料层进行回刻之后，执行氧化工艺或退火工艺；
在执行氧化工艺或退火工艺之后，去除所述硬掩模层；
对所述第二隔离材料层进行回刻，从而形成上表面低于所述鳍片的上表面的隔离区。
2.根据权利要求1所述的方法，其特征在于，所述第二隔离材料层的上表面与所述硬掩模层的底表面之间的距离为3-15nm。
3.根据权利要求1所述的方法，其特征在于，所述氧化工艺包括干法氧化工艺、湿法氧化工艺或现场水汽生成工艺。
4.根据权利要求1所述的方法，其特征在于，所述退火工艺的工艺条件包括：
退火气氛包括氢气或氦气；
退火温度为600-800℃；
退火压强为1torr-1atm；
退火时间为10mins-240mins。
5.根据权利要求1所述的方法，其特征在于，所述鳍片包括用于第一器件的第一鳍片和用于第二器件的第二鳍片。
6.根据权利要求5所述的方法，其特征在于，还包括：
形成第一栅极结构和第二栅极结构；
其中，所述第一栅极结构包括在所述第一鳍片暴露的表面上的栅极电介质层、在所述栅极电介质层上的第一高K电介质层和在所述第一高K电介质层上的第一栅极；
所述第二栅极结构包括在所述第二鳍片暴露的表面上的界面层、在所述界面层上的第二高K电介质层和在所述第二高K电介质层上的第二栅极。
7.根据权利要求6所述的方法，其特征在于，所述形成第一栅极结构和第二栅极结构包括：
在所述第一鳍片暴露的表面上形成第一伪栅电介质层，并在所述第二鳍片暴露的表面上形成第二伪栅电介质层，所述第一伪栅电介质层的厚度大于所述第二伪栅电介质层的厚度；
在所述第一伪栅电介质层和所述第二伪栅电介质层上形成伪栅；
沉积层间电介质层并进行平坦化工艺，以露出所述伪栅；
去除所述伪栅；
去除所述第二伪栅电介质层；
在所述第二鳍片暴露的表面上形成界面层；
在所述界面层和所述第一伪栅电介质层上形成高K电介质层，其中，所述第一伪栅电介质层作为所述栅极电介质层，所述第一伪栅电介质层上的高K电介质层作为所述第一高K电介质层，所述界面层上的高K电介质层作为所述第二高K电介质层；
在所述第一高K电介质层上形成所述第一栅极，在所述第二高K电介质层上形成所述第二栅极。
8.根据权利要求5所述的方法，其特征在于，所述第一器件包括输入/输出器件，所述第二器件包括内核器件。
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